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nanoFIP - Gateware
Commit 9c7ea984 authored by egousiou's avatar egousiou
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wf_model_constr_decoder unit corrected 

wf_rx and wf_engine_control state machines changes from mealy to moore

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@74 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent a702526a
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nanofip.vhd
View file @ 9c7ea984
......@@ -140,12 +140,12 @@ entity nanofip is
-- USER INTERFACE, WISHBONE SLAVE
wclk_i : in std_logic; --! Wishbone clock. May be independent of UCLK.
wclk_i : in std_logic; --! WISHBONE clock. May be independent of UCLK.
dat_i : in std_logic_vector (15 downto 0); --! Data in
dat_o : out std_logic_vector (15 downto 0); --! Data out
adr_i : in std_logic_vector ( 9 downto 0); --! Address
rst_i : in std_logic; --! Wishbone reset. Does not reset other internal logic.
rst_i : in std_logic; --! WISHBONE reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
ack_o : out std_logic; --! Acknowledge
cyc_i : in std_logic;
......@@ -215,7 +215,7 @@ architecture struc of nanofip is
signal s_slone_data_i_d1, s_slone_data_i_d2 : std_logic_vector (15 downto 0);
signal s_stb_r_edge, s_stb_d1, s_stb_d2, s_stb_d3 : std_logic;
signal s_we_d1, s_we_d2, s_cyc_d1, s_cyc_d2, s_reset_rx_unit_p : std_logic;
signal s_ctrl_byte_received, s_pdu_byte_received, s_length_byte_received, s_wb_dati : std_logic_vector (7 downto 0);
signal s_ctrl_byte_received, s_pdu_byte_received, s_length_byte_received : std_logic_vector (7 downto 0);
begin
--=================================================================================================
......@@ -313,7 +313,6 @@ begin
var_i => s_var_from_control,
byte_index_i => s_add_offset_from_control,
byte_i => s_byte_from_rx,
wb_rst_i => rst_i,
wb_clk_i => wclk_i,
wb_adr_i => s_adr_d2,
wb_stb_r_edge_p_i => s_stb_r_edge,
......@@ -338,7 +337,6 @@ begin
slone_i => slone_i,
nostat_i => nostat_i,
nFIP_rst_i => s_rst,
wb_rst_i => rst_i,
wb_clk_i => wclk_i,
wb_adr_i => s_adr_d2,
wb_stb_r_edge_p_i => s_stb_r_edge,
......
wf_consumed_vars.vhd
View file @ 9c7ea984
This diff is collapsed.
wf_engine_control.vhd
View file @ 9c7ea984
This diff is collapsed.
wf_model_constr_decoder.vhd
View file @ 9c7ea984
......@@ -23,8 +23,15 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- unit name wf_model_constr_decoder
--
--
--! @brief Decoding of the inputs S_ID and M_ID and construction of the nanoFIP output S_ID
--! (identification selection)
--! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
--! The output S_ID0 is a clock and the S_ID1 is the opposite clock (it is '0' when
--! S_ID0 is '1' and '1' when S_ID0 is '0').
--! Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd,
--! S_ID1 or S_ID0. Like this (after 2 clock ticks) the 8 bits of the Model and
--! Constructor words take a value, according to the table: Gnd 00
--! S_ID1 01
--! S_ID0 10
--! Vcc 11
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
......@@ -49,13 +56,14 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/09/2009 v0.01 EB First version \n
--! -> 20/08/2010 v0.02 EG code cleaned-up \n
--! -> 20/08/2010 v0.02 EG S_ID corrected so that at any moment S_ID0 is the opposite of S_ID1
--! "for" loop replaced with signals concatenation; Counter is of 8 bits;
--! Code cleaned-up \n
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! -> understand whazz goin on!
--! -> chane name of the unit
--!
--
---------------------------------------------------------------------------------------------------
......@@ -80,10 +88,10 @@ entity wf_model_constr_decoder is
-- OUTPUTS
-- WorldFIP settings nanoFIP output
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- Output to wf_produced_vars
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
);
......@@ -98,57 +106,67 @@ end entity wf_model_constr_decoder;
architecture rtl of wf_model_constr_decoder is
signal s_load_val : std_logic;
signal s_c, s_c_n : unsigned(8 downto 0);
signal s_m_even, s_m_odd : std_logic_vector (3 downto 0);
signal s_c_even, s_c_odd : std_logic_vector (3 downto 0);
signal s_load_model_constr : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_even, s_model_odd : std_logic_vector (3 downto 0);
signal s_constr_even, s_constr_odd : std_logic_vector (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
--!@brief The counter (s_counter) after 2 uclk ticks signals that the M_ID and C_ID can be
--! recalculated. On the first uclk tick, the values of all the odd bits of M_ID and C_ID are
--! loaded on the registers s_model_odd/ s_constr_odd and on the second uclk tick, the values of all
--! the even bits are loaded on the registers s_model_even/ s_constr_even.
--! The output S_ID gives two opposite clocks using as reference the LSB of the counter.
begin
s_c_n <= s_c + 1;
s_load_val <= s_c_n(s_c_n'left) and (not s_c(s_c'left));
s_load_model_constr <= '1' when s_counter = "10"
else '0'; -- C_ID, M_ID recalculated after 2 uclk ticks
P_dec:process(uclk_i)
Model_Constructor_Decoder:process(uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge(uclk_i) then -- initializationss
if nFIP_rst_i = '1' then
m_id_dec_o <= (others => '0');
c_id_dec_o <= (others => '0');
s_m_even <= (others => '0');
s_m_odd <= (others => '0');
s_c_odd <= (others => '0');
s_c_even <= (others => '0');
s_c <= (others => '0');
s_counter <= (others => '0');
m_id_dec_o <= (others => '0');
c_id_dec_o <= (others => '0');
s_model_odd <= (others => '0');
s_model_even <= (others => '0');
s_constr_odd <= (others => '0');
s_constr_even <= (others => '0');
else
s_m_odd <= m_id_i;
s_m_even <= s_m_odd;
s_c_odd <= c_id_i;
s_c_even <= s_c_odd;
s_counter <= s_counter +1; -- when the counter is full, the C_ID
-- and M_ID are recalculated
s_model_odd <= m_id_i; -- 1st clock tick for the loading of the
s_model_even <= s_model_odd; -- odd bits; 2nd clock tick for the even
s_c <= s_c_n;
s_constr_odd <= c_id_i; -- same for the constructor
s_constr_even <= s_constr_odd;
if s_load_val = '1' then
for I in 0 to 3 loop
if s_load_model_constr = '1' then
m_id_dec_o(I*2) <= s_m_even(I);
m_id_dec_o(I*2+1) <= s_m_odd(I);
m_id_dec_o <= s_model_even(3) & s_model_odd(3) & -- putting together odd and even bits
s_model_even(2) & s_model_odd(2) &
s_model_even(1) & s_model_odd(1) &
s_model_even(0) & s_model_odd(0);
c_id_dec_o(I*2) <= s_c_even(I);
c_id_dec_o(I*2+1) <= s_c_odd(I);
end loop;
end if;
c_id_dec_o <= s_constr_even(3) & s_constr_odd(3) &
s_constr_even(2) & s_constr_odd(2) &
s_constr_even(1) & s_constr_odd(1) &
s_constr_even(0) & s_constr_odd(0);
end if;
end if;
end if;
end process;
s_id_o <= std_logic_vector (s_c((s_c'left - 1) downto (s_c'left - 2))); -- 2 msb of s_c
s_id_o <= ((not s_counter(0)) & s_counter(0)); -- S_ID0: |--|__|--|__|--|__|--|__
-- S_ID1: __|--|__|--|__|--|__|--|
end architecture rtl;
......
wf_package.vhd
View file @ 9c7ea984
......@@ -6,7 +6,7 @@
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> egousiou: base_add unsigned(8 downto 0) instead of std_logic_vector (9 downto 0),
--! -> egousiou: base_addr unsigned(8 downto 0) instead of std_logic_vector (9 downto 0),
--! to simplify calculations
--
---------------------------------------------------------------------------------------------------
......@@ -65,11 +65,11 @@ package wf_package is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the position of certain bytes in the frame structure
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LENGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DAT_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DAT_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LENGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_CONSTR_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000110"; -- 6
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
......@@ -134,9 +134,10 @@ package wf_package is
response : t_var_response;
hexvalue : std_logic_vector (7 downto 0);
var : t_var;
base_add : unsigned(8 downto 0);
array_length : unsigned(7 downto 0);
byte_array : t_byte_array(0 to 15);
base_addr : unsigned (8 downto 0);
last_addr : std_logic_vector (8 downto 0);
array_length : unsigned (7 downto 0);
byte_array : t_byte_array (0 to 15);
end record;
type t_var_array is array (natural range <>) of t_var_record;
......@@ -154,7 +155,8 @@ package wf_package is
(c_PRESENCE_VAR_INDEX => (var => presence_var,
hexvalue => x"14",
response => produce,
base_add => "---------",
base_addr => "---------",
last_addr => "---------",
array_length => "00000111", -- 8 bytes in total including the Control byte
-- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
......@@ -167,7 +169,8 @@ package wf_package is
response => produce,
array_length => "00001010", -- 11 bytes in total including the Control byte
-- (counting starts from 0)
base_add => "---------",
base_addr => "---------",
last_addr => "---------",
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00", 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00", 9 => x"00", 10 => x"00",
......@@ -177,7 +180,8 @@ package wf_package is
c_VAR_3_INDEX => (var => var_3,
hexvalue => x"06",
response => produce,
base_add => "100000000",
base_addr => "100000000",
last_addr => "101111101",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
......@@ -187,7 +191,8 @@ package wf_package is
c_VAR_1_INDEX => (var => var_1,
hexvalue => x"05",
response => consume,
base_add => "000000000",
base_addr => "000000000",
last_addr => "001111111",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
......@@ -197,7 +202,8 @@ package wf_package is
c_VAR_2_INDEX => (var => var_2,
hexvalue => x"04",
response => consume,
base_add => "010000000",
base_addr => "010000000",
last_addr => "011111111",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
......@@ -206,7 +212,8 @@ package wf_package is
c_RESET_VAR_INDEX => (var => reset_var,
hexvalue => x"e0",
response => reset,
base_add => "010000000",
base_addr => "010000000",
last_addr => "011111111",
array_length => "00000001", -- only the Control byte is predefined
-- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
......@@ -323,13 +330,12 @@ component wf_rx
component wf_consumed_vars
port (
uclk_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
slone_i : in std_logic;
nFIP_rst_i : in std_logic;
wb_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
......@@ -355,7 +361,6 @@ component wf_rx
nFIP_rst_i : in std_logic;
m_id_dec_i : in std_logic_vector (7 downto 0);
c_id_dec_i : in std_logic_vector (7 downto 0);
wb_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (9 downto 0);
......
wf_produced_vars.vhd
View file @ 9c7ea984
......@@ -77,34 +77,33 @@ entity wf_produced_vars is
nostat_i : in std_logic; --! if negated, nFIP status is sent
-- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset
nFIP_rst_i : in std_logic; --! internal reset
-- User Interface Wishbone Slave
wb_rst_i : in std_logic; --! wishbone reset
-- User Interface WISHBONE Slave
wb_clk_i : in std_logic; --! wishbone clock
wb_clk_i : in std_logic; --! WISHBONE clock
-- note: may be indipendant of uclk
wb_data_i : in std_logic_vector (7 downto 0); --! WISHBONE data bus
-- (buffered twice with wclk)
wb_adr_i : in std_logic_vector (9 downto 0); --! wishbone address to memory
wb_adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address to memory
-- (buffered once with wb_clk)
-- note: msb allways 0!
wb_stb_r_edge_p_i : in std_logic; --! wishbone strobe
wb_stb_r_edge_p_i : in std_logic; --! WISHBONE strobe
-- (buffered once with wb_clk)
-- note: indication that the
-- master is ready to transfer data
wb_we_p_i : in std_logic; --! wishbone write enable
wb_we_p_i : in std_logic; --! WISHBONE write enable
-- note: indicates a write cycle of master
wb_cyc_i : in std_logic; --! wishbone cycle
wb_cyc_i : in std_logic; --! WISHBONE cycle
-- note:indicates a valid cycle in progress
-- User Interface Non Wishbone
-- User Interface Non WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- (buffered twice with uclk)
......@@ -142,7 +141,7 @@ entity wf_produced_vars is
byte_o : out std_logic_vector (7 downto 0); --! output byte to be serialized and sent
-- nanoFIP output
wb_ack_prod_p_o : out std_logic --! wishbone acknowledge
wb_ack_prod_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe signal
);
end entity wf_produced_vars;
......@@ -182,15 +181,15 @@ architecture rtl of wf_produced_vars is
-- first 2 bits: identification of memory block
--remaining 7: address of a byte inside the blck
-- port A corresponds to: nanoFIP that reads from the Produced ram & B to: wishbone that writes
-- port A corresponds to: nanoFIP that reads from the Produced ram & B to: WISHBONE that writes
port map (clk_A_i => uclk_i, -- 40 MHz clck
addr_A_i => s_mem_addr_A, -- address of byte to be read from memory
data_A_o => s_mem_byte, -- output byte read
clk_B_i => wb_clk_i, -- wishbone clck
clk_B_i => wb_clk_i, -- WISHBONE clck
addr_B_i => wb_adr_i (8 downto 0), -- address of byte to be written
data_B_i => wb_data_i(7 downto 0),-- byte to be written
write_en_B_i => s_wb_ack_prod_p -- wishbone write enable ********************
write_en_B_i => s_wb_ack_prod_p -- WISHBONE write enable ********************
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -206,10 +205,10 @@ architecture rtl of wf_produced_vars is
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_prod_p_o: Generation of the wb_ack_prod_p_o signal
--! (acknowledgement from wishbone slave of the write cycle, as a response to the master's storbe).
--! (acknowledgement from WISHBONE slave of the write cycle, as a response to the master's storbe).
--! wb_ack_prod_p_o is asserted two wb_clk cycles after the assertion of the input strobe signal
--! (reminder: stb_i is buffered once in the input stage), if the wishbone input address
--! corresponds to the Produced memory block and the wishbone write enable is asserted.
--! (reminder: stb_i is buffered once in the input stage), if the WISHBONE input address
--! corresponds to the Produced memory block and the WISHBONE write enable is asserted.
Generate_wb_ack_prod_p_o: s_wb_ack_prod_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 7) = "010") and
......@@ -296,7 +295,7 @@ architecture rtl of wf_produced_vars is
s_length <= std_logic_vector (resize((unsigned(data_length_i)-2),byte_o'length));
--signal used for the rp_dat.Data.LENGTH byte
-- it represents the # bytes of "pure data"
-- it represents the # bytes of user-data
-- (P3_LGTH) plus 1 byte of rp_dat.Data.MPS
-- plus 1 byte of rp_dat.Data.nanoFIP_status,
-- if applicable
......@@ -354,7 +353,7 @@ architecture rtl of wf_produced_vars is
-- In memory mode:
if slone_i = '0' then
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_add; --retreival of info for mem base address
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr; --retreival of info for mem base address
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (rp_dat.Control) and second (PDU type) bytes to be sent
......
wf_rx.vhd
View file @ 9c7ea984
This diff is collapsed.
wf_tx.vhd
View file @ 9c7ea984
......@@ -442,9 +442,12 @@ begin
end case;
end process;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
Input_Byte_Sampling: process(uclk_i)
......
wf_tx_rx.vhd
View file @ 9c7ea984
......@@ -135,78 +135,77 @@ begin
uwf_tx: wf_tx
tx: wf_tx
generic map(C_CLKFCDLENTGTH => C_CLKFCDLENTGTH)
PORT MAP(
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
start_produce_p_i => start_produce_p_i,
request_byte_p_o => request_byte_p_o,
byte_ready_p_i => byte_ready_p_i,
byte_i => byte_i,
last_byte_p_i => last_byte_p_i,
-- clk_fixed_sample_manch_bit_p_i => s_clk_fixed_carrier_p,
tx_clk_p_buff_i => s_clk_fixed_carrier_p_d,
tx_data_o => tx_data_o,
tx_enable_o => tx_enable_o
byte_ready_p_i => byte_ready_p_i,
byte_i => byte_i,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => s_clk_fixed_carrier_p_d,
tx_data_o => tx_data_o,
request_byte_p_o => request_byte_p_o,
tx_enable_o => tx_enable_o
);
uwf_rx: wf_rx
rx: wf_rx
PORT MAP(
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
reset_rx_unit_p_i => reset_rx_unit_p_i,
byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o,
last_byte_p_o => last_byte_p_o,
fss_decoded_p_o => fss_decoded_p_o,
crc_ok_p_o => crc_ok_p_o,
rx_data_f_edge_i => s_data_in_f_edge,
rx_data_r_edge_i => s_data_in_r_edge,
rx_data_filtered_i => s_d_filtered,
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
reset_rx_unit_p_i => reset_rx_unit_p_i,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_edge_window,
adjac_bits_window_i => edge_180_window,
rx_data_f_edge_i => s_data_in_f_edge,
rx_data_r_edge_i => s_data_in_r_edge,
rx_data_filtered_i => s_d_filtered,
sample_manch_bit_p_i => s_sample_manch_bit_p,
byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o,
last_byte_p_o => last_byte_p_o,
fss_decoded_p_o => fss_decoded_p_o,
crc_ok_p_o => crc_ok_p_o,
wait_d_first_f_edge_o=> s_first_fe,
code_violation_p_o => code_violation_p_o,
crc_wrong_p_o => crc_wrong_p_o,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_edge_window,
adjac_bits_window_i => edge_180_window
code_violation_p_o => code_violation_p_o,
crc_wrong_p_o => crc_wrong_p_o
);
uwf_rx_osc :wf_rx_tx_osc
rx_tx_osc :wf_rx_tx_osc
generic map(C_COUNTER_LENGTH => 11,
C_QUARTZ_PERIOD => 24.8,
C_CLKFCDLENTGTH => C_CLKFCDLENTGTH)
C_QUARTZ_PERIOD => 24.8,
C_CLKFCDLENTGTH => C_CLKFCDLENTGTH)
port map(
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
d_edge_i => s_data_in_edge,
rx_data_f_edge_i => s_data_in_f_edge,
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
d_edge_i => s_data_in_edge,
rx_data_f_edge_i => s_data_in_f_edge,
wait_d_first_f_edge_i => s_first_fe,
rate_i => rate_i,
tx_clk_p_buff_o => s_clk_fixed_carrier_p_d,
tx_clk_o => d_clk_o,
rx_manch_clk_p_o => s_clk_carrier_p,
rx_bit_clk_p_o => s_clk_bit_180_p,
rx_signif_edge_window_o => s_edge_window,
rx_adjac_bits_window_o => edge_180_window
rate_i => rate_i,
tx_clk_p_buff_o => s_clk_fixed_carrier_p_d,
tx_clk_o => d_clk_o,
rx_manch_clk_p_o => s_clk_carrier_p,
rx_bit_clk_p_o => s_clk_bit_180_p,
rx_signif_edge_window_o => s_edge_window,
rx_adjac_bits_window_o => edge_180_window
);
Udeglitcher : wf_rx_deglitcher
deglitcher : wf_rx_deglitcher
generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
rx_data_i => s_data_in_d3(2),
rx_data_filtered_o => s_d_filtered,
sample_bit_p_i => s_clk_bit_180_p,
sample_manch_bit_p_i => s_clk_carrier_p,
Port map( uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
rx_data_i => s_data_in_d3(2),
sample_bit_p_i => s_clk_bit_180_p,
sample_manch_bit_p_i => s_clk_carrier_p,
rx_data_filtered_o => s_d_filtered,
sample_manch_bit_p_o => s_sample_manch_bit_p,
sample_bit_p_o => s_sample_bit_p
sample_bit_p_o => s_sample_bit_p
);
......
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