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nanoFIP - Gateware
Commit a702526a authored by egousiou's avatar egousiou
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changes for slone mode 

(consumed vars: PDU_TYPE and Length bytes received, 
produced vars: VAR3_ACC enabled only if ctrl, PDU_TYPE, Length and CRC bytes are correct;
sampling of dat_i takes place on the 1st clk tick after VAR3_ACC deasserted)

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@73 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 4303602e
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DualClkRAM.vhd
View file @ a702526a
...@@ -71,14 +71,14 @@ entity DualClkRAM is ...@@ -71,14 +71,14 @@ entity DualClkRAM is
port( port(
-- INPUTS -- INPUTS
-- Inpouts concerning port A -- Inpouts concerning port A
DINA : in std_logic_vector(7 downto 0); --! data in A DINA : in std_logic_vector (7 downto 0); --! data in A
ADDRA : in std_logic_vector(8 downto 0); --! address A ADDRA : in std_logic_vector (8 downto 0); --! address A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations CLKA : in std_logic; --! clock A for synchronous read/ write operations
-- may be indipendant of clock B -- may be indipendant of clock B
-- Inpouts concerning port B -- Inpouts concerning port B
DINB : in std_logic_vector(7 downto 0); --! data in B DINB : in std_logic_vector (7 downto 0); --! data in B
ADDRB : in std_logic_vector(8 downto 0); --! address B ADDRB : in std_logic_vector (8 downto 0); --! address B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations CLKB : in std_logic; --! clock B for synchronous read/ write operations
-- may be indipendant of clock A -- may be indipendant of clock A
...@@ -87,10 +87,10 @@ entity DualClkRAM is ...@@ -87,10 +87,10 @@ entity DualClkRAM is
-- OUTPUTS -- OUTPUTS
-- Output concerning port A -- Output concerning port A
DOUTA : out std_logic_vector(7 downto 0); --! data out A DOUTA : out std_logic_vector (7 downto 0); --! data out A
-- Output concerning port B -- Output concerning port B
DOUTB : out std_logic_vector(7 downto 0) --! data out B DOUTB : out std_logic_vector (7 downto 0) --! data out B
); );
end DualClkRAM; end DualClkRAM;
......
nanofip.vhd
View file @ a702526a
...@@ -187,36 +187,35 @@ architecture struc of nanofip is ...@@ -187,36 +187,35 @@ architecture struc of nanofip is
end component; end component;
signal s_data_length_from_control : std_logic_vector(7 downto 0); signal s_data_length_from_control : std_logic_vector (7 downto 0);
signal s_byte_to_tx : std_logic_vector(7 downto 0); signal s_byte_to_tx : std_logic_vector (7 downto 0);
signal s_rst : std_logic; signal s_rst : std_logic;
signal s_start_send_p : std_logic; signal s_start_send_p : std_logic;
signal s_request_byte_from_tx_p : std_logic; signal s_request_byte_from_tx_p : std_logic;
signal s_byte_to_tx_ready_p : std_logic; signal s_byte_to_tx_ready_p : std_logic;
signal s_last_byte_to_tx_p, s_last_byte_from_rx_p : std_logic; signal s_last_byte_to_tx_p, s_last_byte_from_rx_p : std_logic;
signal s_byte_from_rx_ready_p : std_logic; signal s_byte_from_rx_ready_p : std_logic;
signal s_byte_from_rx : std_logic_vector(7 downto 0); signal s_byte_from_rx : std_logic_vector (7 downto 0);
signal s_cons_byte_we_from_control : std_logic; signal s_cons_byte_we_from_control : std_logic;
signal s_var_from_control : t_var; signal s_var_from_control : t_var;
signal s_add_offset_from_control : std_logic_vector(7 downto 0); signal s_add_offset_from_control : std_logic_vector (7 downto 0);
signal s_crc_ok_from_rx : std_logic; signal s_crc_ok_from_rx : std_logic;
signal fss_decoded_p_from_rx : std_logic; signal fss_decoded_p_from_rx : std_logic;
signal s_stat : std_logic_vector(7 downto 0); signal s_stat : std_logic_vector (7 downto 0);
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic; signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_reset_status_bytes, s_sending_mps: std_logic; signal s_reset_status_bytes, s_sending_mps: std_logic;
signal s_code_violation_p : std_logic; signal s_code_violation_p : std_logic;
signal s_crc_bad_p : std_logic; signal s_crc_bad_p : std_logic;
signal s_var1_rdy : std_logic; signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic;
signal s_var2_rdy : std_logic; signal s_mps : std_logic_vector (7 downto 0);
signal s_var3_rdy : std_logic; signal s_wb_data_i_d1, s_wb_data_i_d2 : std_logic_vector (7 downto 0);
signal s_mps : std_logic_vector(7 downto 0); signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector (7 downto 0);
signal s_wb_data_d1, s_wb_data_d2, s_data_o : std_logic_vector(15 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector(7 downto 0);
--signal s_stb_d, s_we_d, s_cyc_d : std_logic;
signal s_reset_nFIP_and_FD, s_reset_rston : std_logic; signal s_reset_nFIP_and_FD, s_reset_rston : std_logic;
signal s_adr_d1, s_adr_d2 : std_logic_vector (9 downto 0); signal s_adr_d1, s_adr_d2 : std_logic_vector (9 downto 0);
signal s_slone_data_i_d1, s_slone_data_i_d2 : std_logic_vector (15 downto 0);
signal s_stb_r_edge, s_stb_d1, s_stb_d2, s_stb_d3 : std_logic; signal s_stb_r_edge, s_stb_d1, s_stb_d2, s_stb_d3 : std_logic;
signal s_we_d1, s_we_d2, s_cyc_d1, s_cyc_d2 : std_logic; signal s_we_d1, s_we_d2, s_cyc_d1, s_cyc_d2, s_reset_rx_unit_p : std_logic;
signal s_ctrl_byte_received, s_pdu_byte_received, s_length_byte_received, s_wb_dati : std_logic_vector (7 downto 0);
begin begin
--================================================================================================= --=================================================================================================
...@@ -224,7 +223,7 @@ begin ...@@ -224,7 +223,7 @@ begin
--================================================================================================= --=================================================================================================
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
ureset_logic : reset_logic reset_unit : wf_reset_unit
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
rstin_i => rstin_i, rstin_i => rstin_i,
...@@ -236,40 +235,53 @@ begin ...@@ -236,40 +235,53 @@ begin
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
uwf_engine_control : wf_engine_control engine_control : wf_engine_control
generic map( C_QUARTZ_PERIOD => 25.0) generic map( C_QUARTZ_PERIOD => 25.0)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => s_rst, nFIP_rst_i => s_rst,
start_produce_p_o => s_start_send_p , tx_request_byte_p_i => s_request_byte_from_tx_p,
request_byte_p_i => s_request_byte_from_tx_p, rx_fss_decoded_p_i => fss_decoded_p_from_rx,
byte_ready_p_o => s_byte_to_tx_ready_p, rx_byte_ready_p_i => s_byte_from_rx_ready_p,
last_byte_p_o => s_last_byte_to_tx_p, rx_byte_i => s_byte_from_rx,
fss_decoded_p_i => fss_decoded_p_from_rx, rx_CRC_FES_ok_p_i => s_crc_ok_from_rx,
byte_ready_p_i => s_byte_from_rx_ready_p, tx_sending_mps_i => s_sending_mps,
byte_i => s_byte_from_rx, rx_Ctrl_byte_i => s_ctrl_byte_received,
frame_ok_p_i => s_crc_ok_from_rx, rx_PDU_byte_i => s_pdu_byte_received,
rate_i => rate_i, rx_Length_byte_i => s_length_byte_received,
subs_i => subs_i, rate_i => rate_i,
p3_lgth_i => p3_lgth_i, subs_i => subs_i,
slone_i => slone_i, p3_lgth_i => p3_lgth_i,
nostat_i => nostat_i, slone_i => slone_i,
var1_rdy_o => s_var1_rdy, nostat_i => nostat_i,
var2_rdy_o => s_var2_rdy, var1_rdy_o => s_var1_rdy,
var3_rdy_o => s_var3_rdy, var2_rdy_o => s_var2_rdy,
var_o => s_var_from_control, var3_rdy_o => s_var3_rdy,
add_offset_o => s_add_offset_from_control, var_o => s_var_from_control,
data_length_o => s_data_length_from_control, tx_start_produce_p_o => s_start_send_p ,
consume_byte_p_o => s_cons_byte_we_from_control tx_byte_ready_p_o => s_byte_to_tx_ready_p,
tx_last_byte_p_o => s_last_byte_to_tx_p,
tx_rx_byte_index_o => s_add_offset_from_control,
tx_data_length_o => s_data_length_from_control,
rx_byte_ready_p_o => s_cons_byte_we_from_control,
reset_rx_unit_p_o => s_reset_rx_unit_p,
reset_status_bytes_o => s_reset_status_bytes
); );
var1_rdy_o <= s_var1_rdy;
var2_rdy_o <= s_var2_rdy;
var3_rdy_o <= s_var3_rdy;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
uwf_tx_rx : wf_tx_rx
tx_rx : wf_tx_rx
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => s_rst, nFIP_rst_i => s_rst,
reset_rx_unit_p_i => s_reset_rx_unit_p,
start_produce_p_i => s_start_send_p, start_produce_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p, request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p, byte_ready_p_i => s_byte_to_tx_ready_p,
...@@ -290,7 +302,7 @@ begin ...@@ -290,7 +302,7 @@ begin
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
uwf_consumed_vars : wf_consumed_vars consumed_vars : wf_consumed_vars
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
...@@ -299,7 +311,7 @@ begin ...@@ -299,7 +311,7 @@ begin
subs_i => subs_i, subs_i => subs_i,
byte_ready_p_i => s_cons_byte_we_from_control, byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control, var_i => s_var_from_control,
index_offset_i => s_add_offset_from_control, byte_index_i => s_add_offset_from_control,
byte_i => s_byte_from_rx, byte_i => s_byte_from_rx,
wb_rst_i => rst_i, wb_rst_i => rst_i,
wb_clk_i => wclk_i, wb_clk_i => wclk_i,
...@@ -309,11 +321,15 @@ begin ...@@ -309,11 +321,15 @@ begin
wb_ack_cons_p_o => s_ack_consumed, wb_ack_cons_p_o => s_ack_consumed,
data_o => dat_o, data_o => dat_o,
reset_nFIP_and_FD_o => s_reset_nFIP_and_FD, reset_nFIP_and_FD_o => s_reset_nFIP_and_FD,
reset_RSTON_o => s_reset_rston reset_RSTON_o => s_reset_rston,
rx_Ctrl_byte_o => s_ctrl_byte_received,
rx_PDU_byte_o => s_PDU_byte_received,
rx_Length_byte_o => s_length_byte_received
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
uwf_produced_vars : wf_produced_vars
produced_vars : wf_produced_vars
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
...@@ -321,25 +337,29 @@ begin ...@@ -321,25 +337,29 @@ begin
c_id_dec_i => s_c_id_dec_o, c_id_dec_i => s_c_id_dec_o,
slone_i => slone_i, slone_i => slone_i,
nostat_i => nostat_i, nostat_i => nostat_i,
sending_mps_o => s_sending_mps, nFIP_rst_i => s_rst,
nFIP_status_byte_i => s_stat, wb_rst_i => rst_i,
mps_byte_i => s_mps,
var_i => s_var_from_control,
index_offset_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
byte_o => s_byte_to_tx,
wb_rst_i => rst_i,
data_i => s_wb_data_d2,
wb_clk_i => wclk_i, wb_clk_i => wclk_i,
wb_adr_i => s_adr_d2, wb_adr_i => s_adr_d2,
wb_stb_r_edge_p_i => s_stb_r_edge, wb_stb_r_edge_p_i => s_stb_r_edge,
wb_cyc_i => s_cyc_d2, wb_cyc_i => s_cyc_d2,
wb_ack_prod_p_o => s_ack_produced, wb_we_p_i => s_we_d2,
wb_we_p_i => s_we_d2 nFIP_status_byte_i => s_stat,
mps_status_byte_i => s_mps,
var_i => s_var_from_control,
byte_index_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
wb_data_i => s_wb_data_i_d2,
slone_data_i => s_slone_data_i_d2,
var3_rdy_i => s_var3_rdy,
sending_mps_o => s_sending_mps,
byte_o => s_byte_to_tx,
wb_ack_prod_p_o => s_ack_produced
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
ustatus_gen : status_gen status_bytes_gen : wf_status_bytes_gen
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => s_rst, nFIP_rst_i => s_rst,
...@@ -351,17 +371,17 @@ begin ...@@ -351,17 +371,17 @@ begin
var_i => s_var_from_control, var_i => s_var_from_control,
var1_rdy_i => s_var1_rdy, var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy, var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy, var3_rdy_i => s_var3_rdy,
var1_access_a_i => var1_acc_i, var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i, var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i, var3_access_a_i => var3_acc_i,
reset_status_bytes_i => s_reset_status_bytes, reset_status_bytes_i => s_reset_status_bytes,
status_byte_o => s_stat, nFIP_status_byte_o => s_stat,
mps_byte_o => s_mps mps_status_byte_o => s_mps
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
Uwf_dec_m_ids : wf_dec_m_ids model_constr_decoder : wf_model_constr_decoder
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => s_rst, nFIP_rst_i => s_rst,
...@@ -375,12 +395,13 @@ begin ...@@ -375,12 +395,13 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
WISHBONE_input_signals_buffering: process(wclk_i) WISHBONE_input_signals_buffering: process(wclk_i)
begin begin
if rising_edge(wclk_i) then if rising_edge(wclk_i) then
if rst_i = '1' then -- reset not buffered to comply with WISHBONE rule 3.15 if rst_i = '1' then -- reset not buffered to comply with WISHBONE rule 3.15
s_wb_data_d1 <= (others => '0'); s_wb_data_i_d1 <= (others => '0');
s_wb_data_d2 <= (others => '0'); s_wb_data_i_d2 <= (others => '0');
s_adr_d1 <= (others => '0'); s_adr_d1 <= (others => '0');
s_adr_d2 <= (others => '0'); s_adr_d2 <= (others => '0');
s_stb_d1 <= '0'; s_stb_d1 <= '0';
...@@ -392,8 +413,8 @@ begin ...@@ -392,8 +413,8 @@ begin
s_we_d2 <= '0'; s_we_d2 <= '0';
else else
s_wb_data_d2 <= s_wb_data_d1; s_wb_data_i_d2 <= s_wb_data_i_d1;
s_wb_data_d1 <= dat_i; s_wb_data_i_d1 <= dat_i(7 downto 0);
s_adr_d2 <= s_adr_d1; s_adr_d2 <= s_adr_d1;
s_adr_d1 <= adr_i; s_adr_d1 <= adr_i;
...@@ -417,15 +438,28 @@ end process; ...@@ -417,15 +438,28 @@ end process;
ack_o <= (s_ack_produced or s_ack_consumed); --and stb_i; ack_o <= (s_ack_produced or s_ack_consumed); --and stb_i;
s_ack_o <= s_ack_produced or s_ack_consumed; s_ack_o <= s_ack_produced or s_ack_consumed;
s_reset_status_bytes <= s_sending_mps and s_byte_to_tx_ready_p; -- at the end of the transmission
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
var1_rdy_o <= s_var1_rdy; --! Variable 1 ready
var2_rdy_o <= s_var2_rdy; --! Variable 2 ready
var3_rdy_o <= s_var3_rdy; --! Variable 3 ready
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
Slone_dat_i_buffering: process(uclk_i)
begin
if rising_edge(uclk_i) then
if s_rst = '1' then -- reset not buffered to comply with WISHBONE rule 3.15
s_slone_data_i_d2 <= (others => '0');
s_slone_data_i_d1 <= (others => '0');
else
s_slone_data_i_d2 <= s_slone_data_i_d1;
s_slone_data_i_d1 <= dat_i;
end if;
end if;
end process;
end architecture struc; end architecture struc;
--============================================================================ --============================================================================
--============================================================================ --============================================================================
......
dpblockram_clka_rd_clkb_wr_syn.vhd → wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ a702526a
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @file dpblockram_clka_rd_clkb_wr_syn.vhd --! @file wf_DualClkRAM_clka_rd_clkb_wr.vhd
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Standard library -- Standard library
...@@ -11,7 +11,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions ...@@ -11,7 +11,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- dpblockram_clka_rd_clkb_wr_syn -- -- wf_DualClkRAM_clka_rd_clkb_wr --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -58,59 +58,59 @@ use IEEE.NUMERIC_STD.all; -- conversion functions ...@@ -58,59 +58,59 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for dpblockram_clka_rd_clkb_wr_syn --! Entity declaration for wf_DualClkRAM_clka_rd_clkb_wr
--================================================================================================= --=================================================================================================
entity dpblockram_clka_rd_clkb_wr is entity wf_DualClkRAM_clka_rd_clkb_wr is
generic (c_data_length : integer := 8; -- 8: length of data word (1 byte) generic (c_data_length : integer := 8; -- 8: length of data word (1 byte)
c_addr_length : integer := 9); -- 2^9: memory depth (512 bytes) c_addr_length : integer := 9); -- 2^9: memory depth (512 bytes)
port ( port (
clk_A_i : in std_logic; clk_A_i : in std_logic;
addr_A_i : in std_logic_vector(c_addr_length - 1 downto 0); addr_A_i : in std_logic_vector (c_addr_length - 1 downto 0);
clk_B_i : in std_logic; clk_B_i : in std_logic;
addr_B_i : in std_logic_vector(c_addr_length - 1 downto 0); addr_B_i : in std_logic_vector (c_addr_length - 1 downto 0);
data_B_i : in std_logic_vector(c_data_length - 1 downto 0); data_B_i : in std_logic_vector (c_data_length - 1 downto 0);
write_en_B_i : in std_logic; write_en_B_i : in std_logic;
data_A_o : out std_logic_vector(c_data_length -1 downto 0) data_A_o : out std_logic_vector (c_data_length -1 downto 0)
); );
end dpblockram_clka_rd_clkb_wr; end wf_DualClkRAM_clka_rd_clkb_wr;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture syn of dpblockram_clka_rd_clkb_wr is architecture syn of wf_DualClkRAM_clka_rd_clkb_wr is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: component DualClkRam declaration --!@brief: component DualClkRam declaration
component DualClkRam is component DualClkRam is
port( port(
DINA : in std_logic_vector(7 downto 0); DINA : in std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector(8 downto 0); ADDRA : in std_logic_vector (8 downto 0);
RWA : in std_logic; RWA : in std_logic;
CLKA : in std_logic; CLKA : in std_logic;
DINB : in std_logic_vector(7 downto 0); DINB : in std_logic_vector (7 downto 0);
ADDRB : in std_logic_vector(8 downto 0); ADDRB : in std_logic_vector (8 downto 0);
RWB : in std_logic; RWB : in std_logic;
CLKB : in std_logic; CLKB : in std_logic;
RESETn : in std_logic; RESETn : in std_logic;
DOUTA : out std_logic_vector(7 downto 0); DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector(7 downto 0) DOUTB : out std_logic_vector (7 downto 0)
); );
end component DualClkRam; end component DualClkRam;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
type t_data_o_A_array is array (natural range <>) of std_logic_vector(7 downto 0); type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal data_o_A_array : t_data_o_A_array(0 to 2); -- keeps the DOUTA of each one of the memories signal data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal zero, one, s_rwB : std_logic; signal zero, one, s_rwB : std_logic;
signal s_zeros : std_logic_vector(7 downto 0); signal s_zeros : std_logic_vector (7 downto 0);
--================================================================================================= --=================================================================================================
...@@ -126,7 +126,7 @@ s_rwB <= not write_en_B_i; ...@@ -126,7 +126,7 @@ s_rwB <= not write_en_B_i;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: memory triplication --!@brief: memory triplication
--! The component DualClkRam is generated three times. --! The component DualClkRam is generated three times.
--! Port A is used for reading, port B for writing. --! Port A is used for reading only, port B for writing only.
--! The input DINB is written in the same position in the 3 memories. --! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array data_o_A_array. --! The output DOUTA from each memory is kept in the array data_o_A_array.
......
wf_consumed_vars.vhd
View file @ a702526a
...@@ -73,7 +73,7 @@ port ( ...@@ -73,7 +73,7 @@ port (
slone_i : in std_logic; --! stand-alone mode (active high) slone_i : in std_logic; --! stand-alone mode (active high)
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding. subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- User Interface Wishbone Slave -- User Interface Wishbone Slave
...@@ -87,7 +87,7 @@ port ( ...@@ -87,7 +87,7 @@ port (
-- (buffered once with wb_clk) -- (buffered once with wb_clk)
-- note: msb allways 0! -- note: msb allways 0!
wb_stb_r_edge_p_i : in std_logic; --! pulse on the rising edge of stb_i wb_stb_r_edge_p_i : in std_logic; --! pulse on the rising edge of stb_i
-- the pulse appears 2 wclk ticks after -- the pulse appears 2 wclk ticks after
-- a rising edge on the stb_i -- a rising edge on the stb_i
-- note: indication that master -- note: indication that master
...@@ -98,21 +98,27 @@ port ( ...@@ -98,21 +98,27 @@ port (
-- Signals for the wf_engine_control -- Signals for the wf_engine_control
byte_ready_p_i : in std_logic; byte_ready_p_i : in std_logic;
index_offset_i : in std_logic_vector(7 downto 0); byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var; var_i : in t_var;
-- Signals for the receiver wf_rx -- Signals for the receiver wf_rx
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector (7 downto 0);
-- OUTPUTS -- OUTPUTS
-- User Interface WISHBONE slave -- OUTPUTS to the User Interface WISHBONE slave
data_o : out std_logic_vector (15 downto 0); --! data_o : out std_logic_vector (15 downto 0); --!
wb_ack_cons_p_o : out std_logic; --! Acknowledge wb_ack_cons_p_o : out std_logic; --! Acknowledge
-- OUTPUTS to the wf_engine_control
rx_Ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_PDU_byte_o : out std_logic_vector (7 downto 0);
rx_Length_byte_o : out std_logic_vector (7 downto 0);
-- OUTPUTS to the wf_reset_logic -- OUTPUTS to the wf_reset_logic
reset_nFIP_and_FD_o : out std_logic; reset_nFIP_and_FD_o : out std_logic;
reset_RSTON_o : out std_logic reset_RSTON_o : out std_logic
); );
end entity wf_consumed_vars; end entity wf_consumed_vars;
...@@ -123,10 +129,10 @@ end entity wf_consumed_vars; ...@@ -123,10 +129,10 @@ end entity wf_consumed_vars;
--================================================================================================= --=================================================================================================
architecture rtl of wf_consumed_vars is architecture rtl of wf_consumed_vars is
signal s_addr: std_logic_vector(8 downto 0); signal s_addr: std_logic_vector (8 downto 0);
signal s_mem_data_out : std_logic_vector(7 downto 0); signal s_mem_data_out : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector(1 downto 0); signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal s_base_addr : unsigned(8 downto 0); signal s_base_addr, s_last_addr : unsigned(8 downto 0);
signal s_write_byte_to_mem_p : std_logic; signal s_write_byte_to_mem_p : std_logic;
signal s_rp_dat_control_byte_ok : std_logic := '0'; -- for simulation esthetics signal s_rp_dat_control_byte_ok : std_logic := '0'; -- for simulation esthetics
...@@ -139,7 +145,7 @@ begin ...@@ -139,7 +145,7 @@ begin
-- !@brief synchronous process consumtion_dpram: Instanciation of a "Consumed RAM" -- !@brief synchronous process consumtion_dpram: Instanciation of a "Consumed RAM"
--! (for both consumed and consumed broadcast variables) --! (for both consumed and consumed broadcast variables)
consumtion_dpram: dpblockram_clka_rd_clkb_wr consumtion_dpram: wf_DualClkRAM_clka_rd_clkb_wr
generic map(c_data_length => 8, -- 8 bits: length of data word generic map(c_data_length => 8, -- 8 bits: length of data word
c_addr_length => 9) -- 2^9: depth of consumed RAM c_addr_length => 9) -- 2^9: depth of consumed RAM
...@@ -177,12 +183,12 @@ Generate_wb_ack_cons_p_o: wb_ack_cons_p_o <= '1' when ((wb_stb_r_edge_p_i = '1') ...@@ -177,12 +183,12 @@ Generate_wb_ack_cons_p_o: wb_ack_cons_p_o <= '1' when ((wb_stb_r_edge_p_i = '1')
--! s_rp_dat_control_byte_ok stays asserted until a new consumed variable arrives and its --! s_rp_dat_control_byte_ok stays asserted until a new consumed variable arrives and its
--! rp_dat.Control byte is to be checked. The signal is used by the process Bytes_Consumption. --! rp_dat.Control byte is to be checked. The signal is used by the process Bytes_Consumption.
Check_rp_dat_control_byte: process (byte_ready_p_i,index_offset_i,byte_i) Check_rp_dat_control_byte: process (byte_ready_p_i,byte_index_i,byte_i)
begin begin
if ((byte_ready_p_i='1') and (index_offset_i = c_CTRL_BYTE_INDEX)) then if ((byte_ready_p_i='1') and (byte_index_i = c_CTRL_BYTE_INDEX)) then
-- latche created on purpose
if byte_i = c_RP_DAT_CTRL_BYTE then if byte_i = c_RP_DAT_CTRL_BYTE then
s_rp_dat_control_byte_ok <= '1'; s_rp_dat_control_byte_ok <= '1';
else else
...@@ -190,6 +196,28 @@ begin ...@@ -190,6 +196,28 @@ begin
end if; end if;
end if; end if;
end process;
---------------------------------------------------------------------------------------------------
--!@brief combinatorial process Latch_Ctrl_PDU_Length_bytes_received: Latching the rp_dat.Control,
--! PDU_TYPE and Length bytes of an incoming rp_dat frame. The bytes are sent to the control unit
--! that verifies if they are correct and accordingly enables or not the signals var1_rdy, var2_rdy
Latch_Ctrl_PDU_Length_bytes_received: process (byte_ready_p_i,byte_index_i,byte_i)
begin -- latches created on purpose
if ((byte_ready_p_i='1') and (byte_index_i = c_CTRL_BYTE_INDEX)) then
rx_Ctrl_byte_o <= byte_i;
elsif byte_index_i = c_PDU_BYTE_INDEX and byte_ready_p_i ='1'then
rx_PDU_byte_o <= byte_i;
elsif byte_index_i = c_LENGTH_BYTE_INDEX and byte_ready_p_i ='1' then
rx_Length_byte_o <= byte_i;
end if;
end process; end process;
...@@ -209,16 +237,18 @@ end process; ...@@ -209,16 +237,18 @@ end process;
--! Note: in stand-alone mode nanoFIP does not handdle the var2 broadcast variable. --! Note: in stand-alone mode nanoFIP does not handdle the var2 broadcast variable.
Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slone_i, byte_i, Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, byte_index_i, slone_i, byte_i,
subs_i, byte_ready_p_i, s_base_addr) subs_i, byte_ready_p_i, s_base_addr)
begin begin
if s_rp_dat_control_byte_ok = '1' then -- only if the rp_dat.control byte is correct the if s_rp_dat_control_byte_ok = '1' then -- only if the rp_dat.control byte is correct the
-- process continues with the bytes' consumption -- process continues with the bytes' consumption
s_addr <= std_logic_vector(unsigned(index_offset_i)+s_base_addr - 2);-- address in memory s_addr <= std_logic_vector (unsigned(byte_index_i)+s_base_addr - 1);-- address in memory
-- of the byte to be -- of the byte to be
-- written -- written (-1 bc Ctrl byte
-- should not be written)
case var_i is case var_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -229,15 +259,20 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo ...@@ -229,15 +259,20 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo
reset_nFIP_and_FD_o <= '0'; reset_nFIP_and_FD_o <= '0';
s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_add; -- base addr info s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_add; -- base addr info
-- from wf_package -- from wf_package
s_last_addr <= s_base_addr + to_unsigned(127, s_last_addr'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode -- in memory mode
if slone_i = '0' then if slone_i = '0' then
s_slone_write_byte_p <= (others => '0'); s_slone_write_byte_p <= (others => '0');
s_write_byte_to_mem_p <= byte_ready_p_i; -- managment of the write enable signal if (unsigned(s_addr) >= s_base_addr) and (unsigned(s_addr) <= s_last_addr) then
-- of the Consumed memory s_write_byte_to_mem_p <= byte_ready_p_i; -- managment of the write enable signal
-- of the Consumed memory
else
s_write_byte_to_mem_p <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- in stand-alone mode -- in stand-alone mode
...@@ -245,12 +280,14 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo ...@@ -245,12 +280,14 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo
s_write_byte_to_mem_p <= '0'; s_write_byte_to_mem_p <= '0';
if index_offset_i = c_1st_BYTE_INDEX then -- 1st byte to be transferred if byte_index_i = c_1st_DAT_BYTE_INDEX then -- 1st byte to be transferred
s_slone_write_byte_p(0) <= byte_ready_p_i; s_slone_write_byte_p <= '0'& byte_ready_p_i;
end if;
elsif byte_index_i = c_2nd_DAT_BYTE_INDEX then -- 2nd byte to be transferred
s_slone_write_byte_p <= byte_ready_p_i & '0';
if index_offset_i = c_2nd_BYTE_INDEX then -- 2nd byte to be transferred else
s_slone_write_byte_p(1) <= byte_ready_p_i; s_slone_write_byte_p <= (others=>'0');
end if; end if;
end if; end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -262,6 +299,7 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo ...@@ -262,6 +299,7 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo
reset_RSTON_o <= '0'; reset_RSTON_o <= '0';
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_add; -- base addr info s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_add; -- base addr info
-- from wf_package -- from wf_package
s_last_addr <= s_base_addr + to_unsigned(127, s_last_addr'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode -- in memory mode
...@@ -269,8 +307,13 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo ...@@ -269,8 +307,13 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo
s_slone_write_byte_p <= (others => '0'); s_slone_write_byte_p <= (others => '0');
s_write_byte_to_mem_p <= byte_ready_p_i; -- managment of the write enable signal if (unsigned(s_addr) >= s_base_addr) and (unsigned(s_addr) <= s_last_addr) then
-- of the Consumed memory(same as in var_1) s_write_byte_to_mem_p <= byte_ready_p_i; -- managment of the write enable signal
-- of the Consumed memory(same as in var_1)
else
s_write_byte_to_mem_p <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- in stand-alone mode -- in stand-alone mode
...@@ -288,17 +331,17 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo ...@@ -288,17 +331,17 @@ Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slo
s_base_addr <= c_VARS_ARRAY(c_RESET_VAR_INDEX).base_add; -- base addr info s_base_addr <= c_VARS_ARRAY(c_RESET_VAR_INDEX).base_add; -- base addr info
--from wf_package --from wf_package
if ((byte_ready_p_i = '1')and(index_offset_i = c_1st_BYTE_INDEX)) then -- 1st byte if ((byte_ready_p_i = '1')and(byte_index_i = c_1st_DAT_BYTE_INDEX)) then -- 1st byte
if byte_i = subs_i then if byte_i = subs_i then
reset_nFIP_and_FD_o <= '1'; -- reset_nFIP_and_FD_o stays asserted until reset_nFIP_and_FD_o <= '1'; -- reset_nFIP_and_FD_o stays asserted until
end if; -- the end of this rp_dat frame end if; -- the end of this rp_dat frame
elsif ((byte_ready_p_i='1')and(index_offset_i=c_2nd_BYTE_INDEX)) then -- 2nd byte elsif ((byte_ready_p_i='1')and(byte_index_i=c_2nd_DAT_BYTE_INDEX)) then -- 2nd byte
if byte_i = subs_i then if byte_i = subs_i then
reset_RSTON_o <= '1'; -- reset_RSTON_o stays asserted until reset_RSTON_o <= '1'; -- reset_RSTON_o stays asserted until
end if; -- the end of this rp_dat frame end if; -- the end of this rp_dat frame
end if; end if;
...@@ -348,13 +391,15 @@ begin ...@@ -348,13 +391,15 @@ begin
if slone_i = '1' then -- 2 data bytes have to be transferred if slone_i = '1' then -- 2 data bytes have to be transferred
if s_slone_write_byte_p(0) = '1' then -- the 1st byte is written in the lsb of the bus if s_slone_write_byte_p(0) = '1' then -- the 1st byte is written in the lsb of the bus
data_o(7 downto 0) <= byte_i; -- the data stays there until a new byte arrives if byte_ready_p_i ='1' then
data_o(7 downto 0) <= byte_i; -- the data stays there until a new byte arrives
end if; end if;
end if; -- latch created in purpose, to store the value of dat_o
if s_slone_write_byte_p(1) = '1' then -- the 2nd byte is written in the msb of the bus if s_slone_write_byte_p(1) = '1' then -- the 2nd byte is written in the msb of the bus
data_o(15 downto 8) <= byte_i; -- the data stays there until a new byte arrives if byte_ready_p_i ='1' then
data_o(15 downto 8) <= byte_i; -- the data stays there until a new byte arrives
end if;
end if; end if;
......
wf_crc.vhd
View file @ a702526a
...@@ -75,7 +75,7 @@ port ( ...@@ -75,7 +75,7 @@ port (
-- OUTPUTS -- OUTPUTS
crc_ok_p : out std_logic; --! signaling of a correct received crc syndrome crc_ok_p : out std_logic; --! signaling of a correct received crc syndrome
crc_o : out std_logic_vector(c_GENERATOR_POLY_length-1 downto 0)--!calculated crc crc_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated crc
-- 2 bytes -- 2 bytes
); );
...@@ -92,11 +92,11 @@ architecture rtl of wf_crc is ...@@ -92,11 +92,11 @@ architecture rtl of wf_crc is
constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0) := constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0) :=
"0001110111001111"; "0001110111001111";
--! crc check mask --! crc check mask
constant c_VERIFICATION_MASK:std_logic_vector(c_GENERATOR_POLY_length-1 downto 0) := constant c_VERIFICATION_MASK:std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
"0001110001101011"; "0001110001101011";
signal s_crc_bit_ready_p : std_logic; signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector(c_GENERATOR_POLY_length - 1 downto 0); signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0);
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
...@@ -152,8 +152,11 @@ crc_o <= not s_q; ...@@ -152,8 +152,11 @@ crc_o <= not s_q;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: For the verification of a received crc --!@brief Combinatorial process Syndrome_Verification: On the reception, the crc is being
--! syndrome, the outputs of the 16 flip-flops are compared to the predefined mask --! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_VERIFICATION_MASK. When the crc calculated from the received data maches the
--! c_VERIFICATION_MASK, it means a correct crc word has been received and the signal crc_ok_p
--! gives a pulse.
Syndrome_Verification: process(s_q, s_crc_bit_ready_p) Syndrome_Verification: process(s_q, s_crc_bit_ready_p)
......
wf_engine_control.vhd
View file @ a702526a
...@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all; ...@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all;
--! wf_engine \n --! wf_engine \n
--! tx_engine \n --! tx_engine \n
--! clk_gen \n --! clk_gen \n
--! reset_logic \n --! wf_reset_unit \n
--! consumed_ram \n --! consumed_ram \n
-- --
-- --
...@@ -56,6 +56,10 @@ use work.WF_PACKAGE.all; ...@@ -56,6 +56,10 @@ use work.WF_PACKAGE.all;
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! 07/2009 v0.01 EB First version \n --! 07/2009 v0.01 EB First version \n
--! 08/2010 v0.02 EG E0 added as broadcast \n --! 08/2010 v0.02 EG E0 added as broadcast \n
--! PDU,length,ctrl bytes of rp_dat checked bf var1_rdy/ var_2_rdy assertion
--! if id_dat>8 bytes or rp_dat>134 (bf reception of a FES) go to idle
--! state consume_wait_FSS, for the correct use of the silence time(time not
--! counting when an rp_dat frame has started)
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -72,47 +76,67 @@ entity wf_engine_control is ...@@ -72,47 +76,67 @@ entity wf_engine_control is
generic( C_QUARTZ_PERIOD : real := 24.8); generic( C_QUARTZ_PERIOD : real := 24.8);
port ( port (
uclk_i : in std_logic; --! 40MHz clock -- INPUTS
nFIP_rst_i : in std_logic; --! internal reset -- User Interface general signals
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! no NanoFIP status transmission
rate_i : in std_logic_vector (1 downto 0); --! Worldfip bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset
-- Signal from the wf_tx unit
tx_request_byte_p_i : in std_logic; --!
-- Signals from the wf_rx unit
rx_fss_decoded_p_i : in std_logic; --! correct FSS detected by wf_rx
rx_byte_ready_p_i : in std_logic; --! new byte from the receiver on rx_byte_i
rx_byte_i : in std_logic_vector (7 downto 0); -- Decoded byte
rx_CRC_FES_ok_p_i : in std_logic;
-- Signal from the wf_produced_vars
tx_sending_mps_i : in std_logic;
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
-- Transmiter interface
request_byte_p_i : in std_logic;
-- Receiver interface -- OUTPUTS
fss_decoded_p_i : in std_logic; -- the receiver wf_rx has detected the start of a frame -- User interface, non-WISHBONE nanoFIP outputs
byte_ready_p_i : in std_logic; -- ouputs a new byte on byte_i var1_rdy_o : out std_logic; --! signals new data received and can safely be read
byte_i : in std_logic_vector(7 downto 0); -- Decoded byte var2_rdy_o : out std_logic; --! signals new data received and can safely be read
frame_ok_p_i : in std_logic; var3_rdy_o : out std_logic; --! signals that data can safely be written in the memory
rate_i : in std_logic_vector(1 downto 0); -- Worldfip bit rate -- Outputs to the wf_tx unit
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding. tx_last_byte_p_o : out std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length tx_start_produce_p_o : out std_logic;
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! No NanoFIP status transmission
-- Output to wf_rx
reset_rx_unit_p_o : out std_logic; --! if an FES has not arrived after 8 bytes of an id_dat,
--! or after 134 bytes of an rp_dat, the state machine
--! of the wf_rx unit returns to idle state
var1_rdy_o : out std_logic; --! Variable 1 ready. signals new data is received and can safely be read (Consumed -- Output to wf_concumed_vars and wf_produced_vars
--! variable 05xyh). In stand-alone mode one may sample the data on the var_o : out t_var;
--! first clock edge VAR1_RDY is high. tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
-- Output to wf_produced_vars
tx_data_length_o : out std_logic_vector (7 downto 0);
var2_rdy_o : out std_logic; --! Variable 2 ready. Signals new data is received and can safely be read (Consumed -- Output to wf_tx
--! broadcast variable 04xyh). In stand-alone mode one may sample the tx_byte_ready_p_o : out std_logic;
--! data on the first clock edge VAR1_RDY is high.
var3_rdy_o : out std_logic; --! Variable 3 ready. Signals that the variable can safely be written (Produced variable -- output to wf_consumed_vars
--! 06xyh). In stand-alone mode, data is sampled on the first clock after rx_byte_ready_p_o : out std_logic;
--! VAR_RDY is deasserted.
byte_ready_p_o : out std_logic;
last_byte_p_o : out std_logic;
start_produce_p_o : out std_logic;
var_o : out t_var;
add_offset_o : out std_logic_vector(7 downto 0);
data_length_o : out std_logic_vector(7 downto 0);
consume_byte_p_o : out std_logic
);
-- output to the wf_reset_unit
reset_status_bytes_o : out std_logic
);
end entity wf_engine_control; end entity wf_engine_control;
...@@ -123,25 +147,25 @@ end entity wf_engine_control; ...@@ -123,25 +147,25 @@ end entity wf_engine_control;
architecture rtl of wf_engine_control is architecture rtl of wf_engine_control is
type control_st_t is (idle, id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte, consume, type control_st_t is (idle, id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte, consume, consume_wait_FSS,
id_dat_frame_ok, produce_wait_respon_time, cont_w_cons_watchdog, produce); id_dat_frame_ok, produce_wait_respon_time, cont_w_cons_watchdog, produce);
signal control_st, nx_control_st : control_st_t; signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var, s_var_aux_concurr : t_var; signal s_var_aux, s_var, s_var_aux_concurr : t_var;
signal s_load_var, s_load_temp_var, s_byte_ready_p_d, s_last_byte_p_d : std_logic; signal s_load_var, s_load_temp_var, s_tx_byte_ready_p_d1 : std_logic;
signal s_counter_reset, s_reset_id_dat : std_logic; signal s_reset_time_c, s_reset_id_dat, s_tx_byte_ready_p_d2 : std_logic;
signal s_var1_received, s_var2_received : std_logic; signal s_var1_received, s_var2_received, s_tx_last_byte_p_d : std_logic;
signal s_start_produce_p, s_start_produce_p_d1 : std_logic; signal s_tx_start_produce_p, s_tx_start_produce_p_d1 : std_logic;
signal s_respon_silen_c_is_zero, s_broadcast_var : std_logic; signal s_time_c_is_zero, s_broadcast_var : std_logic;
signal s_inc_bytes_c, s_reset_bytes_c, s_last_byte_p : std_logic; signal s_tx_rx_inc_bytes_c, s_reset_tx_rx_bytes_c, s_tx_last_byte_p :std_logic;
signal s_data_length_match, s_byte_ready_p : std_logic; signal s_tx_data_length_match, s_tx_byte_ready_p, s_cons_frame_ok_p :std_logic;
signal s_p3_length_decoded, s_data_length : unsigned(7 downto 0); signal s_rx_ctrl_byte_ok, s_rx_PDU_byte_ok, s_rx_length_byte_ok : std_logic;
signal s_bytes_c : unsigned(7 downto 0); signal s_p3_length_decoded, s_tx_data_length, s_tx_rx_bytes_c : unsigned(7 downto 0);
signal s_respon_silen_c, s_counter_top: signed(16 downto 0); signal s_time_c, s_time_counter_top: signed(14 downto 0);
signal s_response_time, s_silence_time : signed(16 downto 0); signal s_response_time, s_silence_time : signed(14 downto 0);
signal s_produce_or_consume : std_logic_vector(1 downto 0); signal s_produce_or_consume : std_logic_vector (1 downto 0);
--================================================================================================= --=================================================================================================
...@@ -175,86 +199,133 @@ begin ...@@ -175,86 +199,133 @@ begin
--!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM --!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
Central_Control_FSM_Comb_State_Transitions:process (control_st, fss_decoded_p_i, s_last_byte_p, Central_Control_FSM_Comb_State_Transitions:process (control_st, rx_fss_decoded_p_i, s_tx_last_byte_p,
s_var_aux_concurr, byte_ready_p_i,byte_i, subs_i, s_var_aux_concurr, rx_byte_ready_p_i,rx_byte_i, subs_i,
s_respon_silen_c_is_zero,s_produce_or_consume, s_time_c_is_zero,s_produce_or_consume, slone_i,
frame_ok_p_i, s_broadcast_var) rx_CRC_FES_ok_p_i, s_broadcast_var, s_tx_rx_bytes_c)
begin begin
nx_control_st <= idle; nx_control_st <= idle;
case control_st is case control_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when idle => when idle =>
if fss_decoded_p_i = '1' then -- notification from the receiver that a correct FSS field has been received
if rx_fss_decoded_p_i = '1' then -- notification from the receiver that a correct FSS field has been received
nx_control_st <= id_dat_control_byte; nx_control_st <= id_dat_control_byte;
else else
nx_control_st <= idle; nx_control_st <= idle;
end if; end if;
when id_dat_control_byte => -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (byte_ready_p_i = '1') and (byte_i = c_ID_DAT_CTRL_BYTE) then when id_dat_control_byte =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; nx_control_st <= id_dat_var_byte;
elsif (byte_ready_p_i = '1') then
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle; nx_control_st <= idle;
else else
nx_control_st <= id_dat_control_byte; nx_control_st <= id_dat_control_byte;
end if; end if;
when id_dat_var_byte => -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (byte_ready_p_i = '1') and (s_var_aux_concurr /= var_whatever) then when id_dat_var_byte =>
if (rx_byte_ready_p_i = '1') and (s_var_aux_concurr /= var_whatever) then
nx_control_st <= id_dat_subs_byte; nx_control_st <= id_dat_subs_byte;
elsif (byte_ready_p_i = '1') and (s_var_aux_concurr = var_whatever) then
elsif (rx_byte_ready_p_i = '1') and (s_var_aux_concurr = var_whatever) then
nx_control_st <= idle; nx_control_st <= idle;
else else
nx_control_st <= id_dat_var_byte; nx_control_st <= id_dat_var_byte;
end if; end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_subs_byte => when id_dat_subs_byte =>
if (byte_ready_p_i = '1') and (byte_i = subs_i) then
if (rx_byte_ready_p_i = '1') and (rx_byte_i = subs_i) then
nx_control_st <= id_dat_frame_ok; nx_control_st <= id_dat_frame_ok;
elsif (byte_ready_p_i = '1') and (s_broadcast_var = '1') then
elsif (rx_byte_ready_p_i = '1') and (s_broadcast_var = '1') then
nx_control_st <= id_dat_frame_ok; nx_control_st <= id_dat_frame_ok;
elsif (byte_ready_p_i = '1') then
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle; nx_control_st <= idle;
else else
nx_control_st <= id_dat_subs_byte; nx_control_st <= id_dat_subs_byte;
end if; end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_frame_ok => when id_dat_frame_ok =>
if (frame_ok_p_i = '1') and (s_produce_or_consume = "10") then
if (rx_CRC_FES_ok_p_i = '1') and (s_produce_or_consume = "10") then
nx_control_st <= produce_wait_respon_time; nx_control_st <= produce_wait_respon_time;
elsif (frame_ok_p_i = '1') and (s_produce_or_consume = "01") then
nx_control_st <= consume; elsif (rx_CRC_FES_ok_p_i = '1') and (s_produce_or_consume = "01") then
elsif (frame_ok_p_i = '1') then nx_control_st <= consume_wait_FSS;
elsif (rx_CRC_FES_ok_p_i = '1') and (s_tx_rx_bytes_c > 2) then
nx_control_st <= idle; nx_control_st <= idle;
elsif fss_decoded_p_i = '1' then
nx_control_st <= id_dat_control_byte;
else else
nx_control_st <= id_dat_frame_ok; nx_control_st <= id_dat_frame_ok;
end if; end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce_wait_respon_time => when produce_wait_respon_time =>
if s_respon_silen_c_is_zero = '1' then
if s_time_c_is_zero = '1' then
nx_control_st <= produce; nx_control_st <= produce;
else else
nx_control_st <= produce_wait_respon_time; nx_control_st <= produce_wait_respon_time;
end if; end if;
when consume =>
if frame_ok_p_i = '1' or s_respon_silen_c_is_zero = '1' then -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume_wait_FSS =>
if rx_fss_decoded_p_i = '1' then
nx_control_st <= consume;
elsif s_time_c_is_zero = '1' then
nx_control_st <= idle; nx_control_st <= idle;
else
nx_control_st <= consume_wait_FSS;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume =>
if (rx_CRC_FES_ok_p_i = '1') or -- if the rp_dat frame finishes as
(s_tx_rx_bytes_c > 130 and slone_i = '0') or -- expected with a FES, or if no rp_dat
(s_tx_rx_bytes_c > 4 and slone_i = '1') then -- arrives after the silence_time, or
-- if no FES has arrived after the max
-- number of bytes expected, the engine
nx_control_st <= idle; -- goes back to idle state
else else
nx_control_st <= consume; nx_control_st <= consume;
end if; end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce => when produce =>
if s_last_byte_p = '1' then
if s_tx_last_byte_p = '1' then
nx_control_st <= idle; nx_control_st <= idle;
else else
nx_control_st <= produce; nx_control_st <= produce;
end if; end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others => when others =>
nx_control_st <= idle; nx_control_st <= idle;
end case; end case;
...@@ -263,172 +334,199 @@ begin ...@@ -263,172 +334,199 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Central_Control_FSM_Comb_Output_Signals: --!@brief synchronous process Central_Control_FSM_Comb_Output_Signals:
Central_Control_FSM_Comb_Output_Signals: process (control_st, frame_ok_p_i, s_bytes_c, Central_Control_FSM_Comb_Output_Signals: process (control_st, rx_CRC_FES_ok_p_i, s_tx_rx_bytes_c,
s_produce_or_consume, s_start_produce_p_d1, s_produce_or_consume, s_tx_start_produce_p_d1,
request_byte_p_i, s_respon_silen_c_is_zero, tx_request_byte_p_i, s_time_c_is_zero,
byte_ready_p_i,s_response_time, s_silence_time, rx_byte_ready_p_i,s_response_time, s_silence_time,
s_data_length_match) s_tx_data_length_match, s_tx_byte_ready_p_d2,
tx_sending_mps_i)
begin begin
case control_st is case control_st is
when idle => when idle =>
s_load_temp_var <= '0'; reset_rx_unit_p_o <= rx_byte_ready_p_i;
s_counter_reset <= '1'; s_load_temp_var <= '0';
s_inc_bytes_c <= '0'; s_reset_time_c <= '1';
s_reset_bytes_c <= '1'; s_time_counter_top <= s_silence_time;
s_load_var <= '0'; s_tx_rx_inc_bytes_c <= '0';
s_counter_top <= s_silence_time; s_reset_tx_rx_bytes_c<= '1';
consume_byte_p_o <= '0'; s_load_var <= '0';
s_start_produce_p <= '0'; rx_byte_ready_p_o <= '0';
s_last_byte_p <= '0'; s_tx_start_produce_p <= '0';
s_reset_id_dat <= '0'; s_tx_last_byte_p <= '0';
s_byte_ready_p <= '0'; s_reset_id_dat <= '0';
add_offset_o <= (others => '0'); s_tx_byte_ready_p <= '0';
reset_status_bytes_o <= '0';
tx_rx_byte_index_o <= (others => '0');
when id_dat_control_byte => when id_dat_control_byte =>
s_load_temp_var <= '0'; reset_rx_unit_p_o <= '0';
s_counter_reset <= '1'; s_load_temp_var <= '0';
s_inc_bytes_c <= '0'; s_reset_time_c <= '1';
s_reset_bytes_c <= '1'; s_tx_rx_inc_bytes_c <= '0';
s_load_var <= '0'; s_reset_tx_rx_bytes_c<= '1';
s_counter_top <= s_silence_time; s_load_var <= '0';
consume_byte_p_o <= '0'; s_time_counter_top <= s_silence_time;
s_start_produce_p <= '0'; rx_byte_ready_p_o <= '0';
s_last_byte_p <= '0'; s_tx_start_produce_p <= '0';
s_reset_id_dat <= '0'; s_tx_last_byte_p <= '0';
s_byte_ready_p <= '0'; s_reset_id_dat <= '0';
add_offset_o <= (others => '0'); s_tx_byte_ready_p <= '0';
reset_status_bytes_o <= '0';
tx_rx_byte_index_o <= (others => '0');
when id_dat_var_byte => when id_dat_var_byte =>
s_load_temp_var <= byte_ready_p_i; reset_rx_unit_p_o <= '0';
s_load_temp_var <= rx_byte_ready_p_i;
s_counter_reset <= '1';
s_inc_bytes_c <= '0'; s_reset_time_c <= '1';
s_reset_bytes_c <= '1'; s_tx_rx_inc_bytes_c <= '0';
s_load_var <= '0'; s_reset_tx_rx_bytes_c<= '1';
s_counter_top <= s_silence_time; s_load_var <= '0';
consume_byte_p_o <= '0'; s_time_counter_top <= s_silence_time;
s_start_produce_p <= '0'; rx_byte_ready_p_o <= '0';
s_last_byte_p <= '0'; s_tx_start_produce_p <= '0';
s_reset_id_dat <= '0'; s_tx_last_byte_p <= '0';
s_byte_ready_p <= '0'; s_reset_id_dat <= '0';
add_offset_o <= (others => '0'); s_tx_byte_ready_p <= '0';
reset_status_bytes_o <= '0';
tx_rx_byte_index_o <= (others => '0');
when id_dat_subs_byte => when id_dat_subs_byte =>
s_load_temp_var <= '0'; reset_rx_unit_p_o <= '0';
s_counter_reset <= '1'; s_load_temp_var <= '0';
s_inc_bytes_c <= '0'; s_reset_time_c <= '1';
s_reset_bytes_c <= '1'; s_tx_rx_inc_bytes_c <= '0';
s_load_var <= '0'; s_reset_tx_rx_bytes_c<= '1';
s_counter_top <= s_silence_time; s_load_var <= '0';
consume_byte_p_o <= '0'; s_time_counter_top <= s_silence_time;
s_start_produce_p <= '0'; rx_byte_ready_p_o <= '0';
s_last_byte_p <= '0'; s_tx_start_produce_p <= '0';
s_reset_id_dat <= '0'; s_tx_last_byte_p <= '0';
s_byte_ready_p <= '0'; s_reset_id_dat <= '0';
add_offset_o <= (others => '0'); s_tx_byte_ready_p <= '0';
reset_status_bytes_o <= '0';
tx_rx_byte_index_o <= (others => '0');
when id_dat_frame_ok => when id_dat_frame_ok =>
s_load_var <= '0'; reset_rx_unit_p_o <= '0';
s_load_var <= '0';
if s_produce_or_consume = "10" then
s_counter_top <= s_response_time; if s_produce_or_consume = "10" then
else s_time_counter_top <= s_response_time;
s_counter_top <= s_silence_time; else
end if; s_time_counter_top <= s_silence_time;
end if;
s_counter_reset <= '1';
s_inc_bytes_c <= '0'; s_reset_time_c <= '1';
s_reset_bytes_c <= '1'; s_tx_rx_inc_bytes_c <= rx_byte_ready_p_i;
consume_byte_p_o <= '0'; s_reset_tx_rx_bytes_c<= rx_CRC_FES_ok_p_i;
s_start_produce_p <= '0'; rx_byte_ready_p_o <= '0';
s_last_byte_p <= '0'; s_tx_start_produce_p <= '0';
s_reset_id_dat <= '0'; s_tx_last_byte_p <= '0';
s_byte_ready_p <= '0'; s_reset_id_dat <= '0';
s_load_temp_var <= '0'; s_tx_byte_ready_p <= '0';
add_offset_o <= (others => '0'); s_load_temp_var <= '0';
reset_status_bytes_o <= '0';
tx_rx_byte_index_o <= (others => '0');
when produce_wait_respon_time => when produce_wait_respon_time =>
s_start_produce_p <= s_respon_silen_c_is_zero; reset_rx_unit_p_o <= '0';
s_counter_reset <= '0'; s_tx_start_produce_p <= s_time_c_is_zero;
s_time_counter_top <= s_silence_time;
s_inc_bytes_c <= '0'; s_reset_time_c <= '0';
s_reset_bytes_c <= '1'; s_tx_rx_inc_bytes_c <= '0';
s_load_var <= '1'; s_reset_tx_rx_bytes_c<= '1';
s_counter_top <= s_silence_time; s_load_var <= '1';
consume_byte_p_o <= '0'; rx_byte_ready_p_o <= '0';
s_load_temp_var <= '0'; s_load_temp_var <= '0';
s_last_byte_p <= '0'; s_tx_last_byte_p <= '0';
s_reset_id_dat <= '0'; s_reset_id_dat <= '0';
s_byte_ready_p <= '0'; s_tx_byte_ready_p <= '0';
add_offset_o <= (others => '0'); reset_status_bytes_o <= '0';
tx_rx_byte_index_o <= (others => '0');
when consume_wait_FSS =>
s_reset_time_c <= '0';
reset_rx_unit_p_o <= '0';
rx_byte_ready_p_o <= '0';
s_reset_id_dat <= s_time_c_is_zero;
tx_rx_byte_index_o <= (others => '0');
s_tx_rx_inc_bytes_c <= '0';
s_reset_tx_rx_bytes_c<= '0';
s_load_var <= '0';
s_time_counter_top <= s_silence_time;
s_tx_start_produce_p <= '0';
s_tx_last_byte_p <= '0';
s_load_temp_var <= '0';
s_tx_byte_ready_p <= '0';
reset_status_bytes_o <= '0';
when consume => when consume =>
--if unsigned(s_bytes_c) > 1 then -- 1st byte: control; not to be consumed--should be >0??? s_reset_time_c <= '1';
consume_byte_p_o <= byte_ready_p_i; reset_rx_unit_p_o <= '0';
--else rx_byte_ready_p_o <= rx_byte_ready_p_i;
-- consume_byte_p_o <= '0'; s_reset_id_dat <= rx_CRC_FES_ok_p_i or s_time_c_is_zero;
--end if; tx_rx_byte_index_o <= std_logic_vector (resize(s_tx_rx_bytes_c,tx_rx_byte_index_o'length));
s_tx_rx_inc_bytes_c <= rx_byte_ready_p_i;
s_reset_id_dat <= frame_ok_p_i or s_respon_silen_c_is_zero; s_reset_tx_rx_bytes_c<= '0';
add_offset_o <= std_logic_vector(resize(s_bytes_c,add_offset_o'length)); s_load_var <= '1';
s_inc_bytes_c <= byte_ready_p_i; s_time_counter_top <= s_silence_time;
s_tx_start_produce_p <= '0';
s_reset_bytes_c <= '0'; s_tx_last_byte_p <= '0';
s_counter_reset <= '0'; s_load_temp_var <= '0';
s_load_var <= '1'; s_tx_byte_ready_p <= '0';
s_counter_top <= s_silence_time; reset_status_bytes_o <= '0';
s_start_produce_p <= '0';
s_last_byte_p <= '0';
s_load_temp_var <= '0';
s_byte_ready_p <= '0';
when produce => when produce =>
s_last_byte_p <= s_data_length_match and request_byte_p_i; reset_rx_unit_p_o <= '0';
s_byte_ready_p <= request_byte_p_i or s_start_produce_p_d1; s_tx_last_byte_p <= s_tx_data_length_match and tx_request_byte_p_i;
s_inc_bytes_c <= request_byte_p_i; s_tx_byte_ready_p <= tx_request_byte_p_i or s_tx_start_produce_p_d1;
s_reset_id_dat <= s_data_length_match and request_byte_p_i; s_tx_rx_inc_bytes_c <= tx_request_byte_p_i;
add_offset_o <= std_logic_vector(resize(s_bytes_c, add_offset_o'length)); s_reset_id_dat <= s_tx_data_length_match and tx_request_byte_p_i;
s_counter_reset <= '0'; tx_rx_byte_index_o <= std_logic_vector (resize(s_tx_rx_bytes_c, tx_rx_byte_index_o'length));
reset_status_bytes_o <= s_tx_byte_ready_p_d2 and tx_sending_mps_i;
s_reset_bytes_c <= '0'; s_reset_time_c <= '0';
s_start_produce_p <= '0'; s_reset_tx_rx_bytes_c<= '0';
s_load_var <= '0'; s_tx_start_produce_p <= '0';
s_counter_top <= s_silence_time; s_load_var <= '0';
consume_byte_p_o <= '0'; s_time_counter_top <= s_silence_time;
s_load_temp_var <= '0'; rx_byte_ready_p_o <= '0';
s_load_temp_var <= '0';
when others => when others =>
end case; end case;
end process; end process;
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
--! The following two processes: id_dat_var_concurrent and id_dat_var_specific_moments manage the --! The following two processes: id_dat_var_concurrent and id_dat_var_specific_moments manage the
--! signals s_var_aux_concurr, s_var_aux and s_var. All of them are used to keep the value of the --! signals s_var_aux_concurr, s_var_aux and s_var. All of them are used to keep the value of the
--! ID_DAT.Identifier.Variable byte of the incoming ID_DAT frame, but change their value on --! ID_DAT.Identifier.Variable byte of the incoming ID_DAT frame, but change their value on
--! different moments: --! different moments:
--! s_var_aux_concurr: is constantly following the incoming byte byte_i --! s_var_aux_concurr: is constantly following the incoming byte rx_byte_i
--! s_var_aux: locks to the value of s_var_aux_concurr when the ID_DAT.Identifier.Variable byte --! s_var_aux: locks to the value of s_var_aux_concurr when the ID_DAT.Identifier.Variable byte
--! is received (s_load_temp_var = 1) --! is received (s_load_temp_var = 1)
--! s_var: locks to the value of s_var_aux at the end of the id_dat frame (s_load_var = 1) if the --! s_var: locks to the value of s_var_aux at the end of the id_dat frame (s_load_var = 1) if the
--! specified station address matches the SUBS configuration. --! specified station address matches the SUBS configuration.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
id_dat_var_concurrent: process(byte_i) id_dat_var_concurrent: process(rx_byte_i)
begin begin
s_var_aux_concurr <= var_whatever; s_var_aux_concurr <= var_whatever;
for I in c_VARS_ARRAY'range loop for I in c_VARS_ARRAY'range loop
if byte_i = c_VARS_ARRAY(I).hexvalue then if rx_byte_i = c_VARS_ARRAY(I).hexvalue then
s_var_aux_concurr <= c_VARS_ARRAY(I).var; s_var_aux_concurr <= c_VARS_ARRAY(I).var;
exit; exit;
end if; end if;
...@@ -501,10 +599,10 @@ begin ...@@ -501,10 +599,10 @@ begin
--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation --! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation
data_length_calcul_produce: process ( s_var, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i ) data_length_calcul_produce: process ( s_var, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i )
variable v_nostat : std_logic_vector(1 downto 0); variable v_nostat : std_logic_vector (1 downto 0);
begin begin
s_data_length <= (others => '0'); s_tx_data_length <= (others => '0');
s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i))); s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
case s_var is case s_var is
...@@ -513,13 +611,13 @@ begin ...@@ -513,13 +611,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package) -- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
when presence_var => when presence_var =>
s_data_length<=to_unsigned(c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).array_length,s_data_length'length); s_tx_data_length <= c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package) -- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
when identif_var => when identif_var =>
s_data_length<=to_unsigned(c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).array_length,s_data_length'length); s_tx_data_length <= c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
...@@ -543,19 +641,19 @@ begin ...@@ -543,19 +641,19 @@ begin
if slone_i = '1' then if slone_i = '1' then
if nostat_i = '1' then if nostat_i = '1' then
s_data_length <= "00000011"; -- 4 bytes (counting starts from 0) s_tx_data_length <= "00000011"; -- 4 bytes (counting starts from 0)
else else
s_data_length <= "00000100"; -- 5 bytes (counting starts from 0) s_tx_data_length <= "00000100"; -- 5 bytes (counting starts from 0)
end if; end if;
else else
if nostat_i = '0' then if nostat_i = '0' then
s_data_length <= s_p3_length_decoded + 4; -- (bytes counting starts from 0) s_tx_data_length <= s_p3_length_decoded + 4; -- (bytes counting starts from 0)
else else
s_data_length <= s_p3_length_decoded + 3; -- (bytes counting starts from 0) s_tx_data_length <= s_p3_length_decoded + 3; -- (bytes counting starts from 0)
end if; end if;
end if; end if;
...@@ -571,7 +669,7 @@ begin ...@@ -571,7 +669,7 @@ begin
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- output signals that have been also used in the process -- output signals that have been also used in the process
data_length_o <= std_logic_vector(s_data_length); tx_data_length_o <= std_logic_vector (s_tx_data_length);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -582,17 +680,20 @@ begin ...@@ -582,17 +680,20 @@ begin
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then if nFIP_rst_i = '1' then
s_bytes_c <= to_unsigned(0, s_bytes_c'length); s_tx_rx_bytes_c <= (others => '0');
elsif s_reset_bytes_c = '1' then
s_bytes_c <= to_unsigned(0, s_bytes_c'length); elsif s_reset_tx_rx_bytes_c = '1' then
elsif s_inc_bytes_c = '1' then s_tx_rx_bytes_c <= (others => '0');
s_bytes_c <= s_bytes_c + 1;
elsif s_tx_rx_inc_bytes_c = '1' then
s_tx_rx_bytes_c <= s_tx_rx_bytes_c + 1;
end if; end if;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when s_data_length bytes have been counted, the signal s_data_length_match is activated -- when s_tx_data_length bytes have been counted, the signal s_tx_data_length_match is activated
s_data_length_match <= '1' when s_bytes_c = s_data_length else '0'; s_tx_data_length_match <= '1' when s_tx_rx_bytes_c = s_tx_data_length else '0';
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- retrieval of response and silence times information (in equivalent number of uclk ticks) from -- retrieval of response and silence times information (in equivalent number of uclk ticks) from
...@@ -605,23 +706,78 @@ begin ...@@ -605,23 +706,78 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Response_and_Silence_Time_Counter: Managing the counter that counts --!@brief Synchronous process Response_and_Silence_Time_Counter: Managing the counter that counts
--! either response or silence times in uclk ticks. The same counter is used in both cases. --! either response or silence times in uclk ticks. The same counter is used in both cases.
--! The signal s_counter_top initializes the counter to either the response or the silence time. --! The signal s_time_counter_top initializes the counter to either the response or the silence time.
Response_and_Silence_Time_Counter: process(uclk_i) Response_and_Silence_Time_Counter: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then if nFIP_rst_i = '1' then
s_respon_silen_c <= to_signed(-1, s_respon_silen_c'length); s_time_c <= to_signed(-1, s_time_c'length);
elsif s_counter_reset = '1' then
s_respon_silen_c <= s_counter_top; elsif s_reset_time_c = '1' then
s_time_c <= s_time_counter_top;
else else
s_respon_silen_c <= s_respon_silen_c -1; s_time_c <= s_time_c -1;
end if; end if;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when the response or silence time is reached, the signal s_respon_silen_c_is_zero is activated -- when the response or silence time is reached, the signal s_time_c_is_zero is activated
s_respon_silen_c_is_zero <= '1' when s_respon_silen_c = 0 else '0'; s_time_c_is_zero <= '1' when s_time_c = 0 else '0';
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process rx_Ctrl_PDU_Length_bytes_Verification: Checking the correctness of
--! the Ctrl, PDU and Length bytes of an rp_dat. At the end of the rp_dat frame, the signal
--! s_cons_frame_ok_p indicates if those bytes, along with the CRC and the FES were correct and enables
--! the signals var1_rdy or var2_rdy (VAR_RDY_Generation process)
process(s_var, rx_CRC_FES_ok_p_i, s_tx_rx_bytes_c, rx_PDU_byte_i, rx_Ctrl_byte_i, rx_Length_byte_i)
begin
if s_var = var_1 or s_var = var_2 then
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_Ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_rx_ctrl_byte_ok <= '1'; -- RP_DAt_CTRL byte
else
s_rx_ctrl_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_PDU_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_rx_PDU_byte_ok <= '1'; -- PDU_TYPE byte
else
s_rx_PDU_byte_ok <= '0' ;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_CRC_FES_ok_p_i = '1' then -- checking the rp_dat.Data.Length
-- byte, when the end of frame
-- arrives correctly
if s_tx_rx_bytes_c = (unsigned(rx_Length_byte_i) + 5) then -- s_tx_rx_bytes_c starts counting
s_rx_length_byte_ok <= '1'; -- from 0 and apart from"pure"data
-- bytes, also counts ctrl, PDU,
-- Length, 2 crc and FES bytes
else
s_rx_length_byte_ok <= '0';
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
else
s_rx_ctrl_byte_ok <= '0';
s_rx_PDU_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
s_cons_frame_ok_p <= rx_CRC_FES_ok_p_i and s_rx_length_byte_ok and s_rx_ctrl_byte_ok and s_rx_PDU_byte_ok;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -629,17 +785,17 @@ begin ...@@ -629,17 +785,17 @@ begin
--! VAR2_RDY and VAR3_RDY. --! VAR2_RDY and VAR3_RDY.
--! VAR1_RDY (for consumed vars): signals that the user can safely read from the consumed variable --! VAR1_RDY (for consumed vars): signals that the user can safely read from the consumed variable
--! memory. The signal is asserted only after a consumed var has been received and there is data --! memory or retreive data from the dat_o bus. The signal is asserted only after a consumed var
--! in the memory to read. --! that has been received correctly.
--! VAR2_RDY (for broadcast consumed vars): signals that the user can safely read from the consumed --! VAR2_RDY (for broadcast consumed vars): signals that the user can safely read from the consumed
--! broadcast variable memory. The signal is asserted only after a consumed var has been received --! broadcast variable memory. The signal is asserted only after a consumed var has been received
--! and there is data in the memory to read. --! and there is data in the memory to read. In slone mode, the var2_rdy remains deasserted.
--! VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable --! VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable
--! memory. it is deasserted right after the end of the reception of an id_dat that requests a --! memory. it is deasserted right after the end of the reception of an id_dat that requests a
--! produced var and stays deasserted until the end of the transmission of the corresponding rp_dat --! produced var and stays deasserted until the end of the transmission of the corresponding
--! from nanoFIP (in detail, it stays deasserted until the end of the transmission of the --! rp_dat from nanoFIP (in detail, it stays deasserted until the end of the transmission of the
--! rp_dat.data field and is enabled during the rp_dat.fcs and rp_dat.fes transmission. --! rp_dat.data field and is enabled during the rp_dat.fcs and rp_dat.fes transmission.
--! Note: the three memories (consumed, consumed broadcast, produced) are independant; therefore, --! Note: the three memories (consumed, consumed broadcast, produced) are independant; therefore,
...@@ -660,29 +816,35 @@ begin ...@@ -660,29 +816,35 @@ begin
else else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if s_var = var_1 then if s_var = var_1 then
var2_rdy_o <= s_var2_received; var2_rdy_o <= s_var2_received;
var3_rdy_o <= '1'; var3_rdy_o <= '1';
s_var1_received <='0'; s_var1_received <='0';
var1_rdy_o <= '0'; var1_rdy_o <='0';
if frame_ok_p_i = '1' then if s_cons_frame_ok_p = '1' then
s_var1_received <= '1'; -- only if the crc of the received data is correct, s_var1_received <= '1'; -- only if the received rp_dat frame is correct,
end if; -- the nanoFIP signals the user to retreive data end if; -- the nanoFIP signals the user to retreive data
-- note: the signal s_var1_received stays asserted -- note: the signal s_var1_received stays asserted
-- even after the end of the frame_ok_p_i pulse -- even after the end of the rx_CRC_FES_ok_p_i pulse
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif s_var = var_2 then elsif s_var = var_2 then
var1_rdy_o <= s_var1_received;
var3_rdy_o <= '1';
var2_rdy_o <= '0'; var1_rdy_o <= s_var1_received;
var3_rdy_o <= '1';
if frame_ok_p_i = '1' then var2_rdy_o <= '0';
s_var2_received <= '1'; -- only if the crc of the received data is correct,
end if; -- the nanoFIP signals the user to retreive data if slone_i = '0' then -- slone mode does not support broadcast variables
-- note: the signal s_var1_received stays asserted
-- even after the end of the frame_ok_p_i pulse if s_cons_frame_ok_p = '1' then
s_var2_received <= '1'; -- only if the received rp_dat frame is correct,
end if; -- the nanoFIP signals the user to retreive data
-- note: the signal s_var1_received stays asserted
-- even after the end of the rx_CRC_FES_ok_p_i pulse
else
s_var2_received <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif s_var = var_3 then elsif s_var = var_3 then
...@@ -703,27 +865,30 @@ begin ...@@ -703,27 +865,30 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: essential buffering of output signals last_byte_p_o, byte_ready_p_o, start_produce_p_o --!@brief: essential buffering of output signals tx_last_byte_p_o, tx_byte_ready_p_o, tx_start_produce_p_o
process(uclk_i) process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then if nFIP_rst_i = '1' then
last_byte_p_o <= '0'; tx_last_byte_p_o <= '0';
byte_ready_p_o <= '0'; s_tx_last_byte_p_d <= '0';
s_start_produce_p_d1 <= '0'; s_tx_byte_ready_p_d1 <= '0';
else s_tx_byte_ready_p_d2 <= '0';
s_last_byte_p_d <= s_last_byte_p; s_tx_start_produce_p_d1 <= '0';
last_byte_p_o <= s_last_byte_p_d;
s_byte_ready_p_d <= s_byte_ready_p; else
byte_ready_p_o <= s_byte_ready_p_d; s_tx_last_byte_p_d <= s_tx_last_byte_p;
s_start_produce_p_d1 <= s_start_produce_p; tx_last_byte_p_o <= s_tx_last_byte_p_d;
s_tx_byte_ready_p_d1 <= s_tx_byte_ready_p;
s_tx_byte_ready_p_d2 <= s_tx_byte_ready_p_d1;
s_tx_start_produce_p_d1 <= s_tx_start_produce_p;
end if; end if;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
start_produce_p_o <= s_start_produce_p_d1; tx_byte_ready_p_o <= s_tx_byte_ready_p_d2;
tx_start_produce_p_o <= s_tx_start_produce_p_d1;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
wf_dec_m_ids.vhd → wf_model_constr_decoder.vhd
View file @ a702526a
--=========================================================================== --===========================================================================
--! @file wf_dec_m_ids.vhd --! @file wf_model_constr_decoder.vhd
--=========================================================================== --===========================================================================
--! standard library --! standard library
...@@ -14,13 +14,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -14,13 +14,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_dec_m_ids -- -- wf_model_constr_decoder --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_dec_m_ids -- unit name wf_model_constr_decoder
-- --
-- --
--! @brief Decoding of the inputs S_ID and M_ID and construction of the nanoFIP output S_ID --! @brief Decoding of the inputs S_ID and M_ID and construction of the nanoFIP output S_ID
...@@ -61,9 +61,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -61,9 +61,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_dec_m_ids --! Entity declaration for wf_model_constr_decoder
--================================================================================================= --=================================================================================================
entity wf_dec_m_ids is entity wf_model_constr_decoder is
port ( port (
-- INPUTS -- INPUTS
...@@ -80,14 +80,14 @@ entity wf_dec_m_ids is ...@@ -80,14 +80,14 @@ entity wf_dec_m_ids is
-- OUTPUTS -- OUTPUTS
-- WorldFIP settings nanoFIP output -- WorldFIP settings nanoFIP output
s_id_o : out std_logic_vector(1 downto 0); --! Identification selection s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- Output to wf_produced_vars -- Output to wf_produced_vars
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
); );
end entity wf_dec_m_ids; end entity wf_model_constr_decoder;
...@@ -95,13 +95,13 @@ end entity wf_dec_m_ids; ...@@ -95,13 +95,13 @@ end entity wf_dec_m_ids;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_dec_m_ids is architecture rtl of wf_model_constr_decoder is
signal s_load_val : std_logic; signal s_load_val : std_logic;
signal s_c, s_c_n : unsigned(8 downto 0); signal s_c, s_c_n : unsigned(8 downto 0);
signal s_m_even, s_m_odd : std_logic_vector(3 downto 0); signal s_m_even, s_m_odd : std_logic_vector (3 downto 0);
signal s_c_even, s_c_odd : std_logic_vector(3 downto 0); signal s_c_even, s_c_odd : std_logic_vector (3 downto 0);
--================================================================================================= --=================================================================================================
...@@ -148,7 +148,7 @@ begin ...@@ -148,7 +148,7 @@ begin
end if; end if;
end process; end process;
s_id_o <= std_logic_vector(s_c((s_c'left - 1) downto (s_c'left - 2))); -- 2 msb of s_c s_id_o <= std_logic_vector (s_c((s_c'left - 1) downto (s_c'left - 2))); -- 2 msb of s_c
end architecture rtl; end architecture rtl;
......
wf_package.vhd
View file @ a702526a
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> egousiou: base_add unsigned(8 downto 0) instead of std_logic_vector(9 downto 0), --! -> egousiou: base_add unsigned(8 downto 0) instead of std_logic_vector (9 downto 0),
--! to simplify calculations --! to simplify calculations
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -25,22 +25,27 @@ package wf_package is ...@@ -25,22 +25,27 @@ package wf_package is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the manchester coding -- constants regarding the manchester coding
constant VP : std_logic_vector(1 downto 0) := "11"; constant VP : std_logic_vector (1 downto 0) := "11";
constant VN : std_logic_vector(1 downto 0) := "00"; constant VN : std_logic_vector (1 downto 0) := "00";
constant ONE : std_logic_vector(1 downto 0) := "10"; constant ONE : std_logic_vector (1 downto 0) := "10";
constant ZERO : std_logic_vector(1 downto 0) := "01"; constant ZERO : std_logic_vector (1 downto 0) := "01";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the ID_DAT and RP_DAT frame structure -- constants regarding the ID_DAT and RP_DAT frame structure
constant PREAMBLE : std_logic_vector(15 downto 0) := ONE&ZERO&ONE&ZERO&ONE&ZERO&ONE&ZERO; constant PREAMBLE : std_logic_vector (15 downto 0) := ONE&ZERO&ONE&ZERO&ONE&ZERO&ONE&ZERO;
constant FRAME_START : std_logic_vector(15 downto 0) := ONE&VP&VN&ONE&ZERO&VN&VP&ZERO; constant FRAME_START : std_logic_vector (15 downto 0) := ONE&VP&VN&ONE&ZERO&VN&VP&ZERO;
constant FRAME_END : std_logic_vector(15 downto 0) := ONE&VP&VN&VP&VN&ONE&ZERO&ONE; constant FRAME_END : std_logic_vector (15 downto 0) := ONE&VP&VN&VP&VN&ONE&ZERO&ONE;
constant FSS : std_logic_vector(31 downto 0) := PREAMBLE&FRAME_START; constant FSS : std_logic_vector (31 downto 0) := PREAMBLE&FRAME_START;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants concerning the control byte of an ID_DAT and RP_DAT frames -- constants concerning the control byte of an ID_DAT and RP_DAT frames and the PDU_TYPE byte of
constant c_ID_DAT_CTRL_BYTE : std_logic_vector(7 downto 0) := "00000011"; -- a condumed or produced variable
constant c_RP_DAT_CTRL_BYTE : std_logic_vector(7 downto 0) := "00000010"; constant c_ID_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000011";
constant c_RP_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000010";
constant c_PROD_CONS_PDU_TYPE_BYTE : std_logic_vector (7 downto 0) := "01000000";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the nanoFIP status bits --constants concerning the nanoFIP status bits
...@@ -51,12 +56,38 @@ package wf_package is ...@@ -51,12 +56,38 @@ package wf_package is
constant c_T_TXER_INDEX : integer := 6; constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7; constant c_T_WDER_INDEX : integer := 7;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the MPS status bits --constants concerning the MPS status bits
constant c_REFRESHMENT_INDEX : integer := 0; constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2; constant c_SIGNIFICANCE_INDEX : integer := 2;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the position of certain bytes in the frame structure
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LENGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DAT_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DAT_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_CONSTR_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000110"; -- 6
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(0 to 7) :=
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000000" -- reserved
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table with the timeout and silence times for each bit rate -- construction of a table with the timeout and silence times for each bit rate
-- the table contains the number of uclk tick corresponding to the respone/ silence times -- the table contains the number of uclk tick corresponding to the respone/ silence times
...@@ -89,46 +120,27 @@ package wf_package is ...@@ -89,46 +120,27 @@ package wf_package is
silence => integer(5160000.0/C_QUARTZ_PERIOD)) silence => integer(5160000.0/C_QUARTZ_PERIOD))
); );
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(0 to 7) :=
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000000" -- reserved
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table with that gathers all the main information for all the variables
type t_var is (presence_var, identif_var, var_1, var_2, var_3, reset_var, var_whatever); type t_var is (presence_var, identif_var, var_1, var_2, var_3, reset_var, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0); type t_byte_array is array (natural range <>) of std_logic_vector (7 downto 0);
type t_var_response is (produce, consume, reset); type t_var_response is (produce, consume, reset);
type t_var_record is record type t_var_record is record
response : t_var_response; response : t_var_response;
hexvalue : std_logic_vector(7 downto 0); hexvalue : std_logic_vector (7 downto 0);
var : t_var; var : t_var;
base_add : unsigned(8 downto 0); base_add : unsigned(8 downto 0);
array_length : integer; --! -1 represents a variable length array_length : unsigned(7 downto 0);
byte_array : t_byte_array(0 to 15); byte_array : t_byte_array(0 to 15);
end record; end record;
type t_var_array is array (natural range <>) of t_var_record; type t_var_array is array (natural range <>) of t_var_record;
constant c_LENGTH_BYTE_INDEX : integer := 2;
constant c_PDU_BYTE_INDEX : integer := 1;
constant c_CONSTR_BYTE_INDEX : integer := 7;
constant c_MODEL_BYTE_INDEX : integer := 8;
constant c_PRESENCE_VAR_INDEX : integer := 0; constant c_PRESENCE_VAR_INDEX : integer := 0;
constant c_IDENTIF_VAR_INDEX : integer := 1; constant c_IDENTIF_VAR_INDEX : integer := 1;
constant c_VAR_3_INDEX : integer := 2; constant c_VAR_3_INDEX : integer := 2;
...@@ -136,11 +148,6 @@ package wf_package is ...@@ -136,11 +148,6 @@ package wf_package is
constant c_VAR_2_INDEX : integer := 4; constant c_VAR_2_INDEX : integer := 4;
constant c_RESET_VAR_INDEX : integer := 5; constant c_RESET_VAR_INDEX : integer := 5;
constant c_2nd_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000010";
constant c_1st_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000001";
constant c_CTRL_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000000";
constant c_VARS_ARRAY : t_var_array(0 to 5) := constant c_VARS_ARRAY : t_var_array(0 to 5) :=
...@@ -148,8 +155,8 @@ package wf_package is ...@@ -148,8 +155,8 @@ package wf_package is
hexvalue => x"14", hexvalue => x"14",
response => produce, response => produce,
base_add => "---------", base_add => "---------",
array_length => 7, -- 8 bytes in total including the Control byte array_length => "00000111", -- 8 bytes in total including the Control byte
-- (counting starts from 0) -- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05", byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
3 => x"80", 4 => x"03", 5 => x"00", 6 => x"f0", 3 => x"80", 4 => x"03", 5 => x"00", 6 => x"f0",
7 => x"00", others => x"ff")), 7 => x"00", others => x"ff")),
...@@ -158,12 +165,12 @@ package wf_package is ...@@ -158,12 +165,12 @@ package wf_package is
c_IDENTIF_VAR_INDEX => (var => identif_var, c_IDENTIF_VAR_INDEX => (var => identif_var,
hexvalue => x"10", hexvalue => x"10",
response => produce, response => produce,
array_length => 10, -- 11 bytes in total including the Control byte array_length => "00001010", -- 11 bytes in total including the Control byte
-- (counting starts from 0) -- (counting starts from 0)
base_add => "---------", base_add => "---------",
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08", byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00", 5 => x"00", 6 => x"f0", 3 => x"01", 4 => x"00", 5 => x"00", 6 => x"ff",
7 => x"00", 8 => x"00", 9 => X"00", 10 => X"00", 7 => x"ff", 8 => x"00", 9 => x"00", 10 => x"00",
others => x"ff")), others => x"ff")),
...@@ -171,9 +178,9 @@ package wf_package is ...@@ -171,9 +178,9 @@ package wf_package is
hexvalue => x"06", hexvalue => x"06",
response => produce, response => produce,
base_add => "100000000", base_add => "100000000",
array_length => 1, -- only the Control and PDU type bytes are array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0) -- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"40", byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")), others => x"ff")),
...@@ -181,9 +188,9 @@ package wf_package is ...@@ -181,9 +188,9 @@ package wf_package is
hexvalue => x"05", hexvalue => x"05",
response => consume, response => consume,
base_add => "000000000", base_add => "000000000",
array_length => 1, -- only the Control and PDU type bytes are array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0) -- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"40", byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")), others => x"ff")),
...@@ -191,27 +198,32 @@ package wf_package is ...@@ -191,27 +198,32 @@ package wf_package is
hexvalue => x"04", hexvalue => x"04",
response => consume, response => consume,
base_add => "010000000", base_add => "010000000",
array_length => 1, -- only the Control and PDU type bytes are array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0) -- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"40", byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")), others => x"ff")),
c_RESET_VAR_INDEX => (var => reset_var, c_RESET_VAR_INDEX => (var => reset_var,
hexvalue => x"e0", hexvalue => x"e0",
response => reset, response => reset,
base_add => "010000000", base_add => "010000000",
array_length => 0, -- only the Control byte is predefined array_length => "00000001", -- only the Control byte is predefined
-- (counting starts from 0) -- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, others => x"ff"))); byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")));
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component wf_rx -- Components definitions: --
---------------------------------------------------------------------------------------------------
component wf_rx
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nFIP_rst_i : in std_logic; nFIP_rst_i : in std_logic;
reset_rx_unit_p_i : in std_logic;
signif_edge_window_i : in std_logic; signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic; adjac_bits_window_i : in std_logic;
rx_data_r_edge_i : in std_logic; rx_data_r_edge_i : in std_logic;
...@@ -221,7 +233,7 @@ package wf_package is ...@@ -221,7 +233,7 @@ package wf_package is
sample_bit_p_i : in std_logic; sample_bit_p_i : in std_logic;
byte_ready_p_o : out std_logic; byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0); byte_o : out std_logic_vector (7 downto 0);
crc_wrong_p_o : out std_logic; crc_wrong_p_o : out std_logic;
crc_ok_p_o : out std_logic; crc_ok_p_o : out std_logic;
last_byte_p_o : out std_logic; last_byte_p_o : out std_logic;
...@@ -242,8 +254,8 @@ package wf_package is ...@@ -242,8 +254,8 @@ package wf_package is
start_produce_p_i : in std_logic; start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic; byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic; last_byte_p_i : in std_logic;
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector(C_CLKFCDLENTGTH -1 downto 0); tx_clk_p_buff_i : in std_logic_vector (C_CLKFCDLENTGTH -1 downto 0);
request_byte_p_o : out std_logic; request_byte_p_o : out std_logic;
tx_data_o : out std_logic; tx_data_o : out std_logic;
...@@ -253,7 +265,7 @@ package wf_package is ...@@ -253,7 +265,7 @@ package wf_package is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component wf_rx_osc component wf_rx_tx_osc
generic (C_COUNTER_LENGTH : integer := 11; generic (C_COUNTER_LENGTH : integer := 11;
C_QUARTZ_PERIOD : real := 24.8; C_QUARTZ_PERIOD : real := 24.8;
C_CLKFCDLENTGTH : natural := 4 C_CLKFCDLENTGTH : natural := 4
...@@ -272,10 +284,10 @@ package wf_package is ...@@ -272,10 +284,10 @@ package wf_package is
rx_signif_edge_window_o : out std_logic; rx_signif_edge_window_o : out std_logic;
rx_adjac_bits_window_o : out std_logic; rx_adjac_bits_window_o : out std_logic;
tx_clk_o : out std_logic; tx_clk_o : out std_logic;
tx_clk_p_buff_o : out std_logic_vector(C_CLKFCDLENTGTH -1 downto 0) tx_clk_p_buff_o : out std_logic_vector (C_CLKFCDLENTGTH -1 downto 0)
); );
end component wf_rx_osc; end component wf_rx_tx_osc;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -283,14 +295,15 @@ package wf_package is ...@@ -283,14 +295,15 @@ package wf_package is
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
rate_i : in std_logic_vector(1 downto 0); rate_i : in std_logic_vector (1 downto 0);
nFIP_rst_i : in std_logic; nFIP_rst_i : in std_logic;
reset_rx_unit_p_i : in std_logic;
start_produce_p_i : in std_logic; start_produce_p_i : in std_logic;
request_byte_p_o : out std_logic; request_byte_p_o : out std_logic;
byte_ready_p_i : in std_logic; byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic; last_byte_p_i : in std_logic;
d_a_i : in std_logic; d_a_i : in std_logic;
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector (7 downto 0);
tx_enable_o : out std_logic; tx_enable_o : out std_logic;
d_clk_o : out std_logic; d_clk_o : out std_logic;
...@@ -301,7 +314,7 @@ package wf_package is ...@@ -301,7 +314,7 @@ package wf_package is
code_violation_p_o : out std_logic; code_violation_p_o : out std_logic;
crc_wrong_p_o : out std_logic; crc_wrong_p_o : out std_logic;
crc_ok_p_o : out std_logic; crc_ok_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0) byte_o : out std_logic_vector (7 downto 0)
); );
end component wf_tx_rx; end component wf_tx_rx;
...@@ -316,16 +329,19 @@ package wf_package is ...@@ -316,16 +329,19 @@ package wf_package is
wb_rst_i : in std_logic; wb_rst_i : in std_logic;
wb_clk_i : in std_logic; wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0); wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic; wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
byte_ready_p_i : in std_logic; byte_ready_p_i : in std_logic;
index_offset_i : in std_logic_vector(7 downto 0); byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var; var_i : in t_var;
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector (7 downto 0);
data_o : out std_logic_vector (15 downto 0); data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic; wb_ack_cons_p_o : out std_logic;
reset_nFIP_and_FD_o : out std_logic; reset_nFIP_and_FD_o : out std_logic;
reset_RSTON_o : out std_logic reset_RSTON_o : out std_logic;
rx_Ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_PDU_byte_o : out std_logic_vector (7 downto 0);
rx_Length_byte_o : out std_logic_vector (7 downto 0)
); );
end component wf_consumed_vars; end component wf_consumed_vars;
...@@ -333,27 +349,30 @@ package wf_package is ...@@ -333,27 +349,30 @@ package wf_package is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component wf_produced_vars is component wf_produced_vars is
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
slone_i : in std_logic; slone_i : in std_logic;
nostat_i : in std_logic; nostat_i : in std_logic;
m_id_dec_i : in std_logic_vector (7 downto 0); nFIP_rst_i : in std_logic;
c_id_dec_i : in std_logic_vector (7 downto 0); m_id_dec_i : in std_logic_vector (7 downto 0);
wb_rst_i : in std_logic; c_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic; wb_rst_i : in std_logic;
data_i : in std_logic_vector (15 downto 0); wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0); wb_data_i : in std_logic_vector (7 downto 0);
wb_stb_r_edge_p_i : in std_logic; wb_adr_i : in std_logic_vector (9 downto 0);
wb_we_p_i : in std_logic; wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic; wb_we_p_i : in std_logic;
nFIP_status_byte_i : in std_logic_vector(7 downto 0); wb_cyc_i : in std_logic;
mps_byte_i : in std_logic_vector(7 downto 0); slone_data_i : in std_logic_vector (15 downto 0);
var_i : in t_var; nFIP_status_byte_i : in std_logic_vector (7 downto 0);
data_length_i : in std_logic_vector(7 downto 0); mps_status_byte_i : in std_logic_vector (7 downto 0);
index_offset_i : in std_logic_vector(7 downto 0); var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
sending_mps_o : out std_logic; byte_index_i : in std_logic_vector (7 downto 0);
byte_o : out std_logic_vector(7 downto 0); var3_rdy_i : in std_logic;
wb_ack_prod_p_o : out std_logic
sending_mps_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
wb_ack_prod_p_o : out std_logic
); );
end component wf_produced_vars; end component wf_produced_vars;
...@@ -363,36 +382,42 @@ package wf_package is ...@@ -363,36 +382,42 @@ package wf_package is
generic( C_QUARTZ_PERIOD : real := 24.8); generic( C_QUARTZ_PERIOD : real := 24.8);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nFIP_rst_i : in std_logic; nFIP_rst_i : in std_logic;
rate_i : in std_logic_vector(1 downto 0); rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0); subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0); p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic; slone_i : in std_logic;
nostat_i : in std_logic; nostat_i : in std_logic;
request_byte_p_i : in std_logic; tx_request_byte_p_i : in std_logic;
fss_decoded_p_i : in std_logic; rx_fss_decoded_p_i : in std_logic;
byte_ready_p_i : in std_logic; rx_byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector(7 downto 0); rx_byte_i : in std_logic_vector (7 downto 0);
frame_ok_p_i : in std_logic; rx_CRC_FES_ok_p_i : in std_logic;
tx_sending_mps_i : in std_logic;
start_produce_p_o : out std_logic; rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
byte_ready_p_o : out std_logic; rx_PDU_byte_i : in std_logic_vector (7 downto 0);
last_byte_p_o : out std_logic; rx_Length_byte_i : in std_logic_vector (7 downto 0);
var1_rdy_o: out std_logic;
var2_rdy_o: out std_logic; var1_rdy_o: out std_logic;
var3_rdy_o: out std_logic; var2_rdy_o: out std_logic;
var_o : out t_var; var3_rdy_o: out std_logic;
consume_byte_p_o : out std_logic; tx_byte_ready_p_o : out std_logic;
add_offset_o : out std_logic_vector(7 downto 0); tx_last_byte_p_o : out std_logic;
data_length_o : out std_logic_vector(7 downto 0) tx_start_produce_p_o : out std_logic;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
tx_data_length_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
reset_status_bytes_o : out std_logic;
reset_rx_unit_p_o : out std_logic;
var_o : out t_var
); );
end component wf_engine_control; end component wf_engine_control;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component reset_logic component wf_reset_unit
generic(c_rstin_c_length : integer := 4); generic(c_rstin_c_length : integer := 4);
port ( port (
...@@ -405,26 +430,26 @@ package wf_package is ...@@ -405,26 +430,26 @@ package wf_package is
nFIP_rst_o : out std_logic; nFIP_rst_o : out std_logic;
fd_rstn_o : out std_logic fd_rstn_o : out std_logic
); );
end component reset_logic; end component wf_reset_unit;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component dpblockram_clka_rd_clkb_wr component wf_DualClkRAM_clka_rd_clkb_wr
generic (c_data_length : integer := 8; generic (c_data_length : integer := 8;
c_addr_length : integer := 9); c_addr_length : integer := 9);
port ( port (
clk_A_i : in std_logic; clk_A_i : in std_logic;
addr_A_i : in std_logic_vector(c_addr_length - 1 downto 0); addr_A_i : in std_logic_vector (c_addr_length - 1 downto 0);
clk_B_i : in std_logic; clk_B_i : in std_logic;
addr_B_i : in std_logic_vector(c_addr_length - 1 downto 0); addr_B_i : in std_logic_vector (c_addr_length - 1 downto 0);
data_B_i : in std_logic_vector(c_data_length - 1 downto 0); data_B_i : in std_logic_vector (c_data_length - 1 downto 0);
write_en_B_i : in std_logic; write_en_B_i : in std_logic;
data_A_o : out std_logic_vector(c_data_length -1 downto 0) data_A_o : out std_logic_vector (c_data_length -1 downto 0)
); );
end component dpblockram_clka_rd_clkb_wr; end component wf_DualClkRAM_clka_rd_clkb_wr;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -438,13 +463,13 @@ package wf_package is ...@@ -438,13 +463,13 @@ package wf_package is
data_bit_ready_p_i : in std_logic; data_bit_ready_p_i : in std_logic;
crc_ok_p : out std_logic; crc_ok_p : out std_logic;
crc_o : out std_logic_vector(c_GENERATOR_POLY_length - 1 downto 0) crc_o : out std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0)
); );
end component wf_crc; end component wf_crc;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component deglitcher component wf_rx_deglitcher
generic (C_ACULENGTH : integer := 10); generic (C_ACULENGTH : integer := 10);
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
...@@ -457,11 +482,11 @@ package wf_package is ...@@ -457,11 +482,11 @@ package wf_package is
rx_data_filtered_o : out std_logic; rx_data_filtered_o : out std_logic;
sample_bit_p_o : out std_logic sample_bit_p_o : out std_logic
); );
end component deglitcher; end component wf_rx_deglitcher;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component status_gen component wf_status_bytes_gen
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
...@@ -480,10 +505,10 @@ package wf_package is ...@@ -480,10 +505,10 @@ package wf_package is
crc_wrong_p_i : in std_logic; crc_wrong_p_i : in std_logic;
reset_status_bytes_i : in std_logic; reset_status_bytes_i : in std_logic;
status_byte_o : out std_logic_vector(7 downto 0); nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_byte_o : out std_logic_vector(7 downto 0) mps_status_byte_o : out std_logic_vector (7 downto 0)
); );
end component status_gen; end component wf_status_bytes_gen;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -532,25 +557,27 @@ package wf_package is ...@@ -532,25 +557,27 @@ package wf_package is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component wf_dec_m_ids component wf_model_constr_decoder
port ( port (
uclk_i : in std_logic; uclk_i : in std_logic;
nFIP_rst_i : in std_logic; nFIP_rst_i : in std_logic;
m_id_i : in std_logic_vector (3 downto 0); m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0); c_id_i : in std_logic_vector (3 downto 0);
s_id_o : out std_logic_vector(1 downto 0);
m_id_dec_o : out std_logic_vector (7 downto 0); s_id_o : out std_logic_vector (1 downto 0);
m_id_dec_o : out std_logic_vector (7 downto 0);
c_id_dec_o : out std_logic_vector (7 downto 0) c_id_dec_o : out std_logic_vector (7 downto 0)
); );
end component wf_dec_m_ids; end component wf_model_constr_decoder;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
end wf_package;
end wf_package;
package body wf_package is package body wf_package is
end wf_package; end wf_package;
--=================================================================================================
-- package end
--=================================================================================================
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
wf_produced_vars.vhd
View file @ a702526a
...@@ -39,7 +39,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -39,7 +39,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! status_gen \n --! wf_status_bytes_gen \n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
...@@ -75,6 +75,9 @@ entity wf_produced_vars is ...@@ -75,6 +75,9 @@ entity wf_produced_vars is
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode slone_i : in std_logic; --! stand-alone mode
nostat_i : in std_logic; --! if negated, nFIP status is sent nostat_i : in std_logic; --! if negated, nFIP status is sent
-- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset
-- User Interface Wishbone Slave -- User Interface Wishbone Slave
wb_rst_i : in std_logic; --! wishbone reset wb_rst_i : in std_logic; --! wishbone reset
...@@ -82,20 +85,17 @@ entity wf_produced_vars is ...@@ -82,20 +85,17 @@ entity wf_produced_vars is
wb_clk_i : in std_logic; --! wishbone clock wb_clk_i : in std_logic; --! wishbone clock
-- note: may be indipendant of uclk -- note: may be indipendant of uclk
data_i : in std_logic_vector (15 downto 0); --! input data bus wb_data_i : in std_logic_vector (7 downto 0); --! WISHBONE data bus
-- (buffered once with wb_clk) -- (buffered twice with wclk)
-- in memory mode the 8 LSB are used
-- as part of the wishbone interface
-- in slone mode all the bits are used
wb_adr_i : in std_logic_vector (9 downto 0);--! wishbone address to memory wb_adr_i : in std_logic_vector (9 downto 0); --! wishbone address to memory
-- (buffered once with wb_clk) -- (buffered once with wb_clk)
-- note: msb allways 0! -- note: msb allways 0!
wb_stb_r_edge_p_i : in std_logic; --! wishbone strobe wb_stb_r_edge_p_i : in std_logic; --! wishbone strobe
-- (buffered once with wb_clk) -- (buffered once with wb_clk)
-- note: indication that the -- note: indication that the
-- master is ready to transfer data -- master is ready to transfer data
wb_we_p_i : in std_logic; --! wishbone write enable wb_we_p_i : in std_logic; --! wishbone write enable
-- note: indicates a write cycle of master -- note: indicates a write cycle of master
...@@ -103,10 +103,16 @@ entity wf_produced_vars is ...@@ -103,10 +103,16 @@ entity wf_produced_vars is
wb_cyc_i : in std_logic; --! wishbone cycle wb_cyc_i : in std_logic; --! wishbone cycle
-- note:indicates a valid cycle in progress -- note:indicates a valid cycle in progress
-- User Interface Non Wishbone
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- (buffered twice with uclk)
-- Signals from wf_engine_control -- Signals from wf_engine_control
var_i : in t_var; --! variable received from id_dat var_i : in t_var; --! variable received from id_dat
data_length_i: in std_logic_vector(7 downto 0); --! # bytes of Conrol&Data fields of rp_dat data_length_i: in std_logic_vector (7 downto 0); --! # bytes of Conrol&Data fields of rp_dat
-- includes 1 byte for the rp_dat.Control, -- includes 1 byte for the rp_dat.Control,
-- 1 byte for rp_dat.Data.PDU_type, -- 1 byte for rp_dat.Data.PDU_type,
-- 1 byte for rp_dat.Data.LENGTH -- 1 byte for rp_dat.Data.LENGTH
...@@ -115,24 +121,25 @@ entity wf_produced_vars is ...@@ -115,24 +121,25 @@ entity wf_produced_vars is
-- 1 byte for rp_dat.Data.nanoFIP_status -- 1 byte for rp_dat.Data.nanoFIP_status
index_offset_i : in std_logic_vector(7 downto 0); --! pointer to message bytes byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- including rp_dat.Control and rp_dat.Data -- including rp_dat.Control and rp_dat.Data
var3_rdy_i : in std_logic;
-- Signals from status_gen -- Signals from wf_status_bytes_gen
nFIP_status_byte_i : in std_logic_vector(7 downto 0); --! nanoFIP status byte nFIP_status_byte_i : in std_logic_vector (7 downto 0); --! nanoFIP status byte
mps_byte_i : in std_logic_vector(7 downto 0); --! MPS status byte mps_status_byte_i : in std_logic_vector (7 downto 0); --! MPS status byte
-- Signals from the wf_dec_m_ids unit -- Signals from the wf_model_constr_decoder unit
m_id_dec_i : in std_logic_vector (7 downto 0); --! model identification settings (decoded) m_id_dec_i : in std_logic_vector (7 downto 0); --! model identification settings (decoded)
c_id_dec_i : in std_logic_vector (7 downto 0); --! constructor id settings (decoded) c_id_dec_i : in std_logic_vector (7 downto 0); --! constructor id settings (decoded)
-- OUTPUTS -- OUTPUTS
-- Signal to status_gen -- Signal to wf_status_bytes_gen
sending_mps_o : out std_logic; --!indication: mps byte being sent sending_mps_o : out std_logic; --!indication: mps byte being sent
-- Signal to wf_tx -- Signal to wf_tx
byte_o : out std_logic_vector(7 downto 0); --! output byte to be serialized and sent byte_o : out std_logic_vector (7 downto 0); --! output byte to be serialized and sent
-- nanoFIP output -- nanoFIP output
wb_ack_prod_p_o : out std_logic --! wishbone acknowledge wb_ack_prod_p_o : out std_logic --! wishbone acknowledge
...@@ -148,13 +155,15 @@ architecture rtl of wf_produced_vars is ...@@ -148,13 +155,15 @@ architecture rtl of wf_produced_vars is
constant c_ZERO : integer := 0; constant c_ZERO : integer := 0;
signal s_length, s_mem_byte, s_io_byte : std_logic_vector(7 downto 0); signal s_wb_ack_prod_p, var3_rdy_int_d3 : std_logic;
signal s_mem_addr_A : std_logic_vector(8 downto 0); signal var3_rdy_int_d2, var3_rdy_int_d1 : std_logic;
signal s_index_offset_d1 : std_logic_vector(7 downto 0); signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
signal s_byte_index_aux : integer range 0 to 15; signal s_byte_index_aux : integer range 0 to 15;
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0); signal s_length, s_mem_byte, s_io_byte : std_logic_vector (7 downto 0);
signal s_wb_ack_prod_p : std_logic; signal s_byte_index : std_logic_vector (7 downto 0);
signal s_byte_index : integer; signal s_mem_addr_A : std_logic_vector (8 downto 0);
signal s_sample_data_i : std_logic_vector (15 downto 0);
signal zero : std_logic_vector (7 downto 0);
...@@ -166,7 +175,7 @@ architecture rtl of wf_produced_vars is ...@@ -166,7 +175,7 @@ architecture rtl of wf_produced_vars is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- !@brief synchronous process production_dpram: Instanciation of a "Produced ram" -- !@brief synchronous process production_dpram: Instanciation of a "Produced ram"
production_dpram: dpblockram_clka_rd_clkb_wr production_dpram: wf_DualClkRAM_clka_rd_clkb_wr
generic map (c_data_length => 8, -- 8 bits: length of data word generic map (c_data_length => 8, -- 8 bits: length of data word
c_addr_length => 9) -- 2^9: depth of produced ram c_addr_length => 9) -- 2^9: depth of produced ram
...@@ -178,21 +187,21 @@ architecture rtl of wf_produced_vars is ...@@ -178,21 +187,21 @@ architecture rtl of wf_produced_vars is
addr_A_i => s_mem_addr_A, -- address of byte to be read from memory addr_A_i => s_mem_addr_A, -- address of byte to be read from memory
data_A_o => s_mem_byte, -- output byte read data_A_o => s_mem_byte, -- output byte read
clk_B_i => wb_clk_i, -- wishbone clck clk_B_i => wb_clk_i, -- wishbone clck
addr_B_i => wb_adr_i(8 downto 0), -- address of byte to be written addr_B_i => wb_adr_i (8 downto 0), -- address of byte to be written
data_B_i => data_i(7 downto 0), -- byte to be written data_B_i => wb_data_i(7 downto 0),-- byte to be written
write_en_B_i => s_wb_ack_prod_p -- wishbone write enable ******************** write_en_B_i => s_wb_ack_prod_p -- wishbone write enable ********************
); );
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- address of the byte to be read from memory: base_address(from wf_package) + index_offset_i - 1 -- address of the byte to be read from memory: base_address(from wf_package) + byte_index_i - 1
-- (the -1 is because when index_offset_i is on the 4th byte (control, pdu and length have -- (the -1 is because when byte_index_i is on the 4th byte (control, pdu and length have
-- preceeded and a byte from the memoryis now requested), the 3rd byte from the memory has to -- preceeded and a byte from the memoryis now requested), the 3rd byte from the memory has to
-- be retreived (in cell 00000010) etc) -- be retreived (in cell 00000010) etc)
s_mem_addr_A <= std_logic_vector(s_base_addr + s_mem_addr_offset - 1); s_mem_addr_A <= std_logic_vector (s_base_addr + s_mem_addr_offset - 1);
s_mem_addr_offset <= (resize((unsigned(index_offset_i)), s_mem_addr_offset'length)); s_mem_addr_offset <= (resize((unsigned(byte_index_i)), s_mem_addr_offset'length));
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -202,7 +211,7 @@ architecture rtl of wf_produced_vars is ...@@ -202,7 +211,7 @@ architecture rtl of wf_produced_vars is
--! (reminder: stb_i is buffered once in the input stage), if the wishbone input address --! (reminder: stb_i is buffered once in the input stage), if the wishbone input address
--! corresponds to the Produced memory block and the wishbone write enable is asserted. --! corresponds to the Produced memory block and the wishbone write enable is asserted.
Generate_wb_ack_prod_p_o: s_wb_ack_prod_p <= '1' when ((wb_stb_r_edge_p_i = '1') and Generate_wb_ack_prod_p_o: s_wb_ack_prod_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 7) = "010") and (wb_adr_i(9 downto 7) = "010") and
(wb_we_p_i = '1') and (wb_we_p_i = '1') and
(wb_cyc_i = '1')) (wb_cyc_i = '1'))
...@@ -213,45 +222,79 @@ architecture rtl of wf_produced_vars is ...@@ -213,45 +222,79 @@ architecture rtl of wf_produced_vars is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief synchronous process Delay_index_offset_i: in the combinatorial process that follows --!@brief synchronous process Delay_index_offset_i: in the combinatorial process that follows
--! (Bytes_Generation), according to the value of the signal s_byte_index, a byte is retreived --! (Bytes_Generation), according to the value of the signal s_byte_index, a byte is retreived
--! either from the memory, or from the wf_package or from the status_gen or dec_m_ids units. --! either from the memory, or from the wf_package or from the wf_status_bytes_gen or dec_m_ids units.
--! Since the memory needs one clock cycle to output its data the signal s_byte_index has to be a --! Since the memory needs one clock cycle to output its data the signal s_byte_index has to be a
--! delayed version of the index_offset_i, which is actually the signal used as address for the mem --! delayed version of the byte_index_i, which is actually the signal used as address for the mem
Delay_index_offset_i: process(uclk_i) Delay_index_offset_i: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
s_index_offset_d1 <= index_offset_i; if nFIP_rst_i = '1' then
s_byte_index <= (others=> '0');
else
s_byte_index <= byte_index_i; -- index of byte to be sent
end if;
end if; end if;
end process; end process;
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Sample_Data_i: in stand-alone mode, nanoFIP should sample the data on
--! the first clock cycle after the deassettion of VAR3_RDY. Since slone_data_i is the doubly
--! buffered version of the input bus DAT_I, the signal VAR3_RDY has to be delayed too in order
--! to comply with the statement above.
Sample_Data_i: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
var3_rdy_int_d3 <= '0';
var3_rdy_int_d2 <= '0';
var3_rdy_int_d1 <= '0';
s_sample_data_i <= (others=>'0');
else
var3_rdy_int_d3 <= var3_rdy_int_d2;
var3_rdy_int_d2 <= var3_rdy_int_d1;
var3_rdy_int_d1 <= var3_rdy_i;
if var3_rdy_int_d3 = '1' then -- data latching
s_sample_data_i <= slone_data_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_io_byte <= s_sample_data_i(7 downto 0) when byte_index_i(0) = '1'
else s_sample_data_i(15 downto 8);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Bytes_Generation: Generation of bytes for the Control and Data --!@brief Combinatorial process Bytes_Generation: Generation of bytes for the Control and Data
--! fields of an rp_dat frame:\n If the variable requested in the id_dat is of "produced" type(id/ --! fields of an rp_dat frame:\n If the variable requested in the id_dat is of "produced" type(id/
--! presence/ var3) the process prepares accordingly, one by one, bytes of data to be sent. \n The --! presence/ var3) the process prepares accordingly, one by one, bytes of data to be sent. \n The
--! pointer "index_offset_i" indicates which byte of the frame is to be sent. Some of the bytes are --! pointer "byte_index_i" indicates which byte of the frame is to be sent. Some of the bytes are
--! defined in the wf_package, the rest come either from the memory (if slone=0) or from the the --! defined in the wf_package, the rest come either from the memory (if slone=0) or from the the
--! input bus data_i or from the wf_status_gen or wf_dec_m_ids units.\n --! input bus data_i or from the wf_status_gen or wf_model_constr_decoder units.\n
--! The output byte "byte_o" is sent to the transmitter(wf_tx)for serialization --! The output byte "byte_o" is sent to the transmitter(wf_tx)for serialization
Bytes_Generation: process (var_i, s_index_offset_d1, s_byte_index, data_length_i, c_id_dec_i, Bytes_Generation: process (var_i, s_byte_index, data_length_i, c_id_dec_i, m_id_dec_i,
m_id_dec_i,nFIP_status_byte_i, mps_byte_i, s_io_byte, s_mem_byte, nFIP_status_byte_i, mps_status_byte_i, s_io_byte, s_mem_byte,
slone_i, s_byte_index_aux, nostat_i) slone_i, s_byte_index_aux, nostat_i)
begin begin
s_byte_index <= to_integer(unsigned(s_index_offset_d1)); zero <= (others=>'0');
-- index of byte to be sent s_byte_index_aux <= (to_integer(unsigned(s_byte_index(3 downto 0))));
s_byte_index_aux <= (to_integer(unsigned(s_index_offset_d1(3 downto 0))));
-- index of byte to be sent(range restricted) -- index of byte to be sent(range restricted)
-- used to retreive bytes from the matrix -- used to retreive bytes from the matrix
-- c_VARS_ARRAY.byte_array, with a predefined -- c_VARS_ARRAY.byte_array, with a predefined
-- width of 15 bytes -- width of 15 bytes
s_length <= std_logic_vector(resize((unsigned(data_length_i)-2),byte_o'length)); s_length <= std_logic_vector (resize((unsigned(data_length_i)-2),byte_o'length));
--signal used for the rp_dat.Data.LENGTH byte --signal used for the rp_dat.Data.LENGTH byte
-- it represents the # bytes of "pure data" -- it represents the # bytes of "pure data"
-- (P3_LGTH) plus 1 byte of rp_dat.Data.MPS -- (P3_LGTH) plus 1 byte of rp_dat.Data.MPS
...@@ -280,7 +323,7 @@ architecture rtl of wf_produced_vars is ...@@ -280,7 +323,7 @@ architecture rtl of wf_produced_vars is
--case: identification variable --case: identification variable
-- The Constructor and Model bytes of the identification variable arrive from the decoding unit -- The Constructor and Model bytes of the identification variable arrive from the decoding unit
-- (wf_dec_m_ids), wereas all the rest are predefined in the c_VARS_ARRAY matrix -- (wf_model_constr_decoder), wereas all the rest are predefined in the c_VARS_ARRAY matrix
when identif_var => when identif_var =>
...@@ -317,7 +360,7 @@ architecture rtl of wf_produced_vars is ...@@ -317,7 +360,7 @@ architecture rtl of wf_produced_vars is
-- The first (rp_dat.Control) and second (PDU type) bytes to be sent -- The first (rp_dat.Control) and second (PDU type) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the wf_package -- are predefined in the c_VARS_ARRAY matrix of the wf_package
if s_byte_index <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less than or equal to if unsigned(s_byte_index) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less than or equal to
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux); byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux);
sending_mps_o <= '0'; sending_mps_o <= '0';
...@@ -332,14 +375,14 @@ architecture rtl of wf_produced_vars is ...@@ -332,14 +375,14 @@ architecture rtl of wf_produced_vars is
-- The one but last byte if the input nostat_i is negated is the nanoFIP status byte -- The one but last byte if the input nostat_i is negated is the nanoFIP status byte
-- (if nostat_i is not negated, the "else" condition takes place) -- (if nostat_i is not negated, the "else" condition takes place)
elsif s_byte_index = (unsigned(data_length_i)-1 ) and nostat_i = '0' then elsif unsigned(s_byte_index) = (unsigned(data_length_i)-1 ) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i; byte_o <= nFIP_status_byte_i;
sending_mps_o <= '0'; sending_mps_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The last byte is the MPS status -- The last byte is the MPS status
elsif s_byte_index = (unsigned(data_length_i))then elsif s_byte_index = (data_length_i)then
byte_o <= mps_byte_i; byte_o <= mps_status_byte_i;
sending_mps_o <= '1'; -- indication: MPS byte is being sent sending_mps_o <= '1'; -- indication: MPS byte is being sent
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -360,7 +403,7 @@ architecture rtl of wf_produced_vars is ...@@ -360,7 +403,7 @@ architecture rtl of wf_produced_vars is
-- The first byte to be sent is the rp_dat.Control, which is -- The first byte to be sent is the rp_dat.Control, which is
-- predefined in the c_VARS_ARRAY matrix of the wf_package -- predefined in the c_VARS_ARRAY matrix of the wf_package
if s_byte_index = 0 then if s_byte_index = zero then
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux); byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux);
sending_mps_o <= '0'; sending_mps_o <= '0';
...@@ -368,14 +411,14 @@ architecture rtl of wf_produced_vars is ...@@ -368,14 +411,14 @@ architecture rtl of wf_produced_vars is
-- The one but last byte if the input nostat_i is negated is the nanoFIP status byte -- The one but last byte if the input nostat_i is negated is the nanoFIP status byte
-- (if nostat_i is not negated, the "else" condition takes place) -- (if nostat_i is not negated, the "else" condition takes place)
elsif s_byte_index = (unsigned(data_length_i)-1 ) and nostat_i = '0' then elsif unsigned(s_byte_index) = (unsigned(data_length_i)-1 ) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i; byte_o <= nFIP_status_byte_i;
sending_mps_o <= '0'; sending_mps_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The last byte is the MPS status -- The last byte is the MPS status
elsif s_byte_index = (unsigned(data_length_i))then elsif s_byte_index = data_length_i then
byte_o <= mps_byte_i; byte_o <= mps_status_byte_i;
sending_mps_o <= '1'; -- indication: MPS byte is being sent sending_mps_o <= '1'; -- indication: MPS byte is being sent
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -397,14 +440,6 @@ architecture rtl of wf_produced_vars is ...@@ -397,14 +440,6 @@ architecture rtl of wf_produced_vars is
end case; end case;
end process; end process;
---------------------------------------------------------------------------------------------------
-- In stand-alone mode 2 bytes of "pure" data have to sent in total (other bytes to be sent: Control
-- mps and nFIP status bytes). The first data byte after the rp_dat.Control is retreived from the
-- input bus data_i(7:0) and the second from the data_i(15:8)
s_io_byte <= data_i(7 downto 0) when index_offset_i(0) = '1' else data_i(15 downto 8);
end architecture rtl; end architecture rtl;
--================================================================================================= --=================================================================================================
......
reset_logic.vhd → wf_reset_unit.vhd
View file @ a702526a
--================================================================================================= --=================================================================================================
--! @file reset_logic.vhd --! @file wf_reset_unit.vhd
--================================================================================================= --=================================================================================================
--! standard library --! standard library
...@@ -15,13 +15,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -15,13 +15,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_reset_logic -- -- wf_reset_unit --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name: reset_logic -- unit name: wf_reset_unit
-- --
--! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset --! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset
--! and user interface reset (RSTON) --! and user interface reset (RSTON)
...@@ -64,9 +64,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -64,9 +64,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for reset_logic --! Entity declaration for wf_reset_unit
--================================================================================================= --=================================================================================================
entity reset_logic is entity wf_reset_unit is
generic (c_rstin_c_length : integer := 4); --! rstin counter length generic (c_rstin_c_length : integer := 4); --! rstin counter length
port ( port (
...@@ -92,16 +92,16 @@ entity reset_logic is ...@@ -92,16 +92,16 @@ entity reset_logic is
-- nanoFIP output to FIELDRIVE -- nanoFIP output to FIELDRIVE
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
); );
end entity reset_logic; end entity wf_reset_unit;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of reset_logic is architecture rtl of wf_reset_unit is
signal s_rst : std_logic; signal s_rst : std_logic;
signal s_rstin_buff : std_logic_vector(2 downto 0); signal s_rstin_buff : std_logic_vector (2 downto 0);
signal s_rstin_c : unsigned(4 downto 0) := (others=>'0'); -- counter init for simulation purpuses signal s_rstin_c : unsigned(4 downto 0) := (others=>'0'); -- counter init for simulation purpuses
......
wf_rx.vhd
View file @ a702526a
...@@ -75,8 +75,11 @@ entity wf_rx is ...@@ -75,8 +75,11 @@ entity wf_rx is
-- User interface general signal -- User interface general signal
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- Signal from the wf_engine_control
reset_rx_unit_p_i : in std_logic;
-- signals from the wf_rx_tx_osc -- signals from the wf_rx_tx_osc
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
...@@ -95,10 +98,9 @@ entity wf_rx is ...@@ -95,10 +98,9 @@ entity wf_rx is
-- OUTPUTS -- OUTPUTS
-- needed by the wf_consumed and wf_engine_control -- needed by the wf_consumed and wf_engine_control
byte_ready_p_o : out std_logic; --! indication of a valid data byte byte_ready_p_o : out std_logic; --! indication of a valid data byte
byte_o : out std_logic_vector(7 downto 0) ; --! retreived data byte byte_o : out std_logic_vector (7 downto 0) ; --! retreived data byte
-- needed by the wf_engine_control -- needed by the wf_engine_control
crc_ok_p_o : out std_logic; crc_ok_p_o : out std_logic;
...@@ -106,7 +108,7 @@ entity wf_rx is ...@@ -106,7 +108,7 @@ entity wf_rx is
fss_decoded_p_o : out std_logic; fss_decoded_p_o : out std_logic;
last_byte_p_o : out std_logic; last_byte_p_o : out std_logic;
-- needed by the status_gen -- needed by the wf_status_bytes_gen
code_violation_p_o : out std_logic; --! indicator of a manchester 2 code violation code_violation_p_o : out std_logic; --! indicator of a manchester 2 code violation
-- needed by the wf_rx_tx_osc -- needed by the wf_rx_tx_osc
...@@ -139,14 +141,14 @@ architecture rtl of wf_rx is ...@@ -139,14 +141,14 @@ architecture rtl of wf_rx is
signal s_frame_start_wrong_bit, s_frame_start_last_bit : std_logic; signal s_frame_start_wrong_bit, s_frame_start_last_bit : std_logic;
signal s_frame_end_detected_p, s_frame_end_detection, s_frame_end_wrong_bit : std_logic; signal s_frame_end_detected_p, s_frame_end_detection, s_frame_end_wrong_bit : std_logic;
signal s_violation_check, s_code_violation_p : std_logic; signal s_check_violation, s_code_violation_p : std_logic;
signal s_calculate_crc, s_crc_ok_p, s_crc_ok, s_start_crc_p : std_logic; signal s_calculate_crc, s_crc_ok_p, s_crc_ok, s_start_crc_p : std_logic;
signal s_byte_ok, s_write_bit_to_byte, s_rx_data_filtered_d: std_logic; signal s_byte_ok, s_write_bit_to_byte, s_rx_data_filtered_d: std_logic;
signal s_byte : std_logic_vector(7 downto 0); signal s_byte : std_logic_vector (7 downto 0);
signal s_rx_data_filtered_buff : std_logic_vector(1 downto 0); signal s_rx_data_filtered_buff : std_logic_vector (1 downto 0);
...@@ -158,16 +160,15 @@ architecture rtl of wf_rx is ...@@ -158,16 +160,15 @@ architecture rtl of wf_rx is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief instantiation of the crc calculator unit --!@brief instantiation of the crc calculator unit
crc_verification : wf_crc crc_verification : wf_crc
generic map( generic map(c_GENERATOR_POLY_length => 16)
c_GENERATOR_POLY_length => 16)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i, nFIP_rst_i => nFIP_rst_i,
start_crc_p_i => s_start_crc_p, start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_write_bit_to_byte, data_bit_ready_p_i => s_write_bit_to_byte,
data_bit_i => rx_data_filtered_i, data_bit_i => rx_data_filtered_i,
crc_o => open, crc_o => open,
crc_ok_p => s_crc_ok_p crc_ok_p => s_crc_ok_p
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -204,7 +205,8 @@ architecture rtl of wf_rx is ...@@ -204,7 +205,8 @@ architecture rtl of wf_rx is
s_frame_start_wrong_bit, s_manch_f_edge, rx_st, s_frame_start_wrong_bit, s_manch_f_edge, rx_st,
s_frame_end_detected_p, s_frame_end_wrong_bit, s_frame_end_detected_p, s_frame_end_wrong_bit,
rx_data_f_edge_i, s_edge_outside_manch_window, rx_data_f_edge_i, s_edge_outside_manch_window,
s_code_violation_p,s_bit_r_edge, s_manch_r_edge ) s_code_violation_p,s_bit_r_edge, s_manch_r_edge,
reset_rx_unit_p_i )
begin begin
nx_rx_st <= idle; nx_rx_st <= idle;
...@@ -255,7 +257,7 @@ architecture rtl of wf_rx is ...@@ -255,7 +257,7 @@ architecture rtl of wf_rx is
end if; end if;
-- A small delay is expected between the rx_data_i and the rx_data_filtered_i (output of the -- A small delay is expected between the rx_data_i and the rx_data_filtered_i (output of the
-- deglitcher) which means that the last falling edge of the preamble of rx_data_i arrives -- wf_rx_deglitcher) which means that the last falling edge of the preamble of rx_data_i arrives
-- earlier than the one of the rx_data_filtered_i. the state switch_to _deglitched is used for -- earlier than the one of the rx_data_filtered_i. the state switch_to _deglitched is used for
-- this purpose. -- this purpose.
...@@ -284,7 +286,7 @@ architecture rtl of wf_rx is ...@@ -284,7 +286,7 @@ architecture rtl of wf_rx is
when data_field_byte => when data_field_byte =>
if s_frame_end_detected_p = '1' then if s_frame_end_detected_p = '1' or reset_rx_unit_p_i = '1' then
nx_rx_st <= idle; nx_rx_st <= idle;
-- Is there a code violation that does not correspond to the queue pattern? -- Is there a code violation that does not correspond to the queue pattern?
elsif s_frame_end_wrong_bit = '1' and s_code_violation_p = '1' then elsif s_frame_end_wrong_bit = '1' and s_code_violation_p = '1' then
...@@ -362,7 +364,7 @@ architecture rtl of wf_rx is ...@@ -362,7 +364,7 @@ architecture rtl of wf_rx is
s_start_pointer <= to_unsigned(0,s_start_pointer'length); s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0'; s_load_pointer <= '0';
s_decr_pointer <= '0'; s_decr_pointer <= '0';
s_frame_start_bit <='0'; s_frame_start_bit <= '0';
fss_decoded_p_o <= '0'; fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0'; s_write_bit_to_byte <= '0';
s_byte_ok <= '0'; s_byte_ok <= '0';
...@@ -413,7 +415,7 @@ architecture rtl of wf_rx is ...@@ -413,7 +415,7 @@ architecture rtl of wf_rx is
s_byte_ok <= s_pointer_is_zero and sample_manch_bit_p_i and s_byte_ok <= s_pointer_is_zero and sample_manch_bit_p_i and
(not s_frame_end_detected_p); (not s_frame_end_detected_p);
s_queue_bit <= FRAME_END(to_integer(resize(pointer,4))); s_queue_bit <= FRAME_END(to_integer(resize(pointer,4)));
code_violation_p_o <= s_code_violation_p; code_violation_p_o <= s_code_violation_p and s_frame_end_wrong_bit;
s_start_crc_p <= '0'; s_start_crc_p <= '0';
s_calculate_crc <= '1'; s_calculate_crc <= '1';
s_frame_start_bit <= '0'; s_frame_start_bit <= '0';
...@@ -448,7 +450,7 @@ architecture rtl of wf_rx is ...@@ -448,7 +450,7 @@ architecture rtl of wf_rx is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extra concurrent signal assignments -- extra concurrent signal assignments
s_code_violation_p <= (not (rx_data_filtered_i xor s_rx_data_filtered_d)) and s_violation_check; s_code_violation_p <= (not (rx_data_filtered_i xor s_rx_data_filtered_d)) and s_check_violation;
s_pointer_is_zero <= '1' when pointer = 0 else '0'; s_pointer_is_zero <= '1' when pointer = 0 else '0';
-- s_frame_start_last_bit <= s_pointer_is_zero and s_frame_start_correct_bit and sample_manch_bit_p_i; -- s_frame_start_last_bit <= s_pointer_is_zero and s_frame_start_correct_bit and sample_manch_bit_p_i;
...@@ -565,14 +567,14 @@ end process; ...@@ -565,14 +567,14 @@ end process;
-- 0 V- 1 -- 0 V- 1
-- rx_data_filtered_i: __|--|____|--|__ -- rx_data_filtered_i: __|--|____|--|__
-- s_rx_data_filtered_d: __|--|____|--|__ -- s_rx_data_filtered_d: __|--|____|--|__
-- s_violation_check: ^ ^ ^ -- s_check_violation: ^ ^ ^
Check_code_violations: process(uclk_i) Check_code_violations: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then if nFIP_rst_i = '1' then
byte_ready_p_o <='0'; byte_ready_p_o <='0';
s_violation_check <='0'; s_check_violation <='0';
s_sample_bit_p_d1 <='0'; s_sample_bit_p_d1 <='0';
s_sample_bit_p_d2 <='0'; s_sample_bit_p_d2 <='0';
s_rx_data_filtered_d <='0'; s_rx_data_filtered_d <='0';
...@@ -581,7 +583,7 @@ end process; ...@@ -581,7 +583,7 @@ end process;
if sample_manch_bit_p_i = '1' then if sample_manch_bit_p_i = '1' then
s_rx_data_filtered_d <= rx_data_filtered_i; s_rx_data_filtered_d <= rx_data_filtered_i;
end if; end if;
s_violation_check <= s_sample_bit_p_d2; s_check_violation <= s_sample_bit_p_d2;
s_sample_bit_p_d2 <= s_sample_bit_p_d1; s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i; s_sample_bit_p_d1 <= sample_bit_p_i;
byte_ready_p_o <= s_byte_ok and (not s_frame_end_detected_p); byte_ready_p_o <= s_byte_ok and (not s_frame_end_detected_p);
......
deglitcher.vhd → wf_rx_deglitcher.vhd
View file @ a702526a
--================================================================================================= --=================================================================================================
--! @file deglitcher.vhd --! @file wf_rx_deglitcher.vhd
--================================================================================================= --=================================================================================================
--! Standard library --! Standard library
...@@ -12,7 +12,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -12,7 +12,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- deglitcher -- -- wf_rx_deglitcher --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -37,7 +37,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -37,7 +37,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! wf_osc \n --! wf_osc \n
--! reset_logic \n --! wf_reset_unit \n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
...@@ -62,7 +62,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -62,7 +62,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! Entity declaration for wf_deglitcher --! Entity declaration for wf_deglitcher
--================================================================================================= --=================================================================================================
entity deglitcher is entity wf_rx_deglitcher is
generic (C_ACULENGTH : integer := 10); generic (C_ACULENGTH : integer := 10);
port( port(
...@@ -70,7 +70,7 @@ entity deglitcher is ...@@ -70,7 +70,7 @@ entity deglitcher is
-- User interface general signal -- User interface general signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- FIELDRIVE input signal -- FIELDRIVE input signal
...@@ -86,14 +86,14 @@ entity deglitcher is ...@@ -86,14 +86,14 @@ entity deglitcher is
rx_data_filtered_o : out std_logic; rx_data_filtered_o : out std_logic;
sample_manch_bit_p_o : out std_logic sample_manch_bit_p_o : out std_logic
); );
end deglitcher; end wf_rx_deglitcher;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture Behavioral of deglitcher is architecture Behavioral of wf_rx_deglitcher is
signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0); signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0);
signal s_rx_data_filtered: STD_LOGIC; signal s_rx_data_filtered: STD_LOGIC;
...@@ -115,7 +115,7 @@ process(uclk_i) ...@@ -115,7 +115,7 @@ process(uclk_i)
s_count_ones_c <= (others =>'0'); s_count_ones_c <= (others =>'0');
else else
if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit
s_count_ones_c <= (others =>'0'); -- counter initialized s_count_ones_c <= (others =>'0'); -- counter initialized
elsif rx_data_i = '1' then -- counting the number of ones elsif rx_data_i = '1' then -- counting the number of ones
......
wf_rx_osc.vhd → wf_rx_tx_osc.vhd
View file @ a702526a
--================================================================================================= --=================================================================================================
--! @file wf_rx_osc.vhd --! @file wf_rx_tx_osc.vhd
--================================================================================================= --=================================================================================================
--! Standard library --! Standard library
...@@ -12,13 +12,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -12,13 +12,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_rx_osc //change name to wf_rx_tx_osc -- -- wf_rx_tx_osc --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_rx_osc -- unit name wf_rx_tx_osc
-- --
--! @brief Generation the clock signals needed for the transmiter and receiver units. \n --! @brief Generation the clock signals needed for the transmiter and receiver units. \n
--! --!
...@@ -79,10 +79,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -79,10 +79,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_rx_osc --! Entity declaration for wf_rx_tx_osc
--================================================================================================= --=================================================================================================
entity wf_rx_osc is entity wf_rx_tx_osc is
generic (C_COUNTER_LENGTH : integer := 11; -- in the slowest bit rate (31.25kbps), the period is generic (C_COUNTER_LENGTH : integer := 11; -- in the slowest bit rate (31.25kbps), the period is
-- 32000ns and can be measured after 1280 uclk ticks. -- 32000ns and can be measured after 1280 uclk ticks.
-- Therefore a counter of 11 bits is the max needed -- Therefore a counter of 11 bits is the max needed
...@@ -96,7 +96,7 @@ entity wf_rx_osc is ...@@ -96,7 +96,7 @@ entity wf_rx_osc is
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! bit rate rate_i : in std_logic_vector (1 downto 0); --! bit rate
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- Signals from wf_tx_rx -- Signals from wf_tx_rx
...@@ -123,18 +123,18 @@ entity wf_rx_osc is ...@@ -123,18 +123,18 @@ entity wf_rx_osc is
-- bits is expected -- bits is expected
-- Output signals needed in the transmission -- Output signals needed in the transmission
tx_clk_p_buff_o : out std_logic_vector(C_CLKFCDLENTGTH -1 downto 0); tx_clk_p_buff_o : out std_logic_vector (C_CLKFCDLENTGTH -1 downto 0);
tx_clk_o : out std_logic tx_clk_o : out std_logic
); );
end entity wf_rx_osc; end entity wf_rx_tx_osc;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_rx_osc is architecture rtl of wf_rx_tx_osc is
-- calculations of the number of uclk ticks equivalent to the reception/ transmission period -- calculations of the number of uclk ticks equivalent to the reception/ transmission period
...@@ -156,7 +156,7 @@ architecture rtl of wf_rx_osc is ...@@ -156,7 +156,7 @@ architecture rtl of wf_rx_osc is
-- auxiliary signals declarations -- auxiliary signals declarations
signal s_counter_rx, s_counter_tx, s_period, s_jitter : unsigned (C_COUNTER_LENGTH-1 downto 0); signal s_counter_rx, s_counter_tx, s_period, s_jitter : unsigned (C_COUNTER_LENGTH-1 downto 0);
signal s_counter_full, s_one_forth_period, s_half_period :unsigned (C_COUNTER_LENGTH-1 downto 0); signal s_counter_full, s_one_forth_period, s_half_period :unsigned (C_COUNTER_LENGTH-1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector(C_CLKFCDLENTGTH -1 downto 0); signal s_tx_clk_p_buff : std_logic_vector (C_CLKFCDLENTGTH -1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic; signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_rx_bit_clk, s_rx_bit_clk_d1, s_rx_manch_clk, s_rx_manch_clk_d1 : std_logic; signal s_rx_bit_clk, s_rx_bit_clk_d1, s_rx_manch_clk, s_rx_manch_clk_d1 : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic; signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
......
status_gen.vhd → wf_status_bytes_gen.vhd
View file @ a702526a
--================================================================================================= --=================================================================================================
--! @file status_gen.vhd --! @file wf_status_bytes_gen.vhd
--================================================================================================= --=================================================================================================
--! standard library --! standard library
...@@ -14,17 +14,16 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,17 +14,16 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_status_byte_generator -- -- wf_status_bytes_generator --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name status_gen -- unit name wf_status_bytes_gen
-- --
-- --
--! @brief Generation of the NanoFIP status that may be sent with Produced variables. --! @brief Generation of the NanoFIP status, as well as the MPS status bytes.
--! See Table 8 of the Functional Specification..
-- --
-- --
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch) --! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
...@@ -54,18 +53,21 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -54,18 +53,21 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 EB First version \n --! 07/07/2009 v0.01 EB First version \n
--! 08/2010 v0.02 EG code violation & CRC errors considered
--! only during a concumed var reception
--!
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo Define I/O signals \n --! @todo bits 6 and 7 reset only when nanoFIP is reset...
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
-- Entity declaration for status_gen -- Entity declaration for wf_status_bytes_gen
--================================================================================================= --=================================================================================================
entity status_gen is entity wf_status_bytes_gen is
port ( port (
-- INPUTS -- INPUTS
...@@ -97,23 +99,23 @@ port ( ...@@ -97,23 +99,23 @@ port (
-- Signal from nanofip -- Signal from nanofip
reset_status_bytes_i : in std_logic; reset_status_bytes_i : in std_logic; --! both status bytes are reinitialized
--! right after having been delivered
-- OUTPUTS -- OUTPUTS
-- Output to wf_produced_vars -- Output to wf_produced_vars
status_byte_o : out std_logic_vector(7 downto 0); --! status byte nFIP_status_byte_o : out std_logic_vector (7 downto 0); --! status byte
mps_byte_o : out std_logic_vector(7 downto 0) --! mps byte mps_status_byte_o : out std_logic_vector (7 downto 0) --! mps byte
); );
end entity status_gen; end entity wf_status_bytes_gen;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of status_gen is architecture rtl of wf_status_bytes_gen is
signal s_refreshment : std_logic; signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1 : std_logic;
signal s_var1_access, s_var2_access, s_var3_access : std_logic_vector(1 downto 0); signal s_var1_access_d2, s_var2_access_d2, s_var3_access_d2, s_refreshment : std_logic;
--================================================================================================= --=================================================================================================
...@@ -129,16 +131,22 @@ begin ...@@ -129,16 +131,22 @@ begin
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nFIP_rst_i = '1' then if nFIP_rst_i = '1' then
s_var1_access <= (others => '0'); s_var1_access_d1 <= '0';
s_var2_access <= (others => '0'); s_var1_access_d2 <= '0';
s_var3_access <= (others => '0'); s_var2_access_d1 <= '0';
s_var2_access_d2 <= '0';
s_var3_access_d1 <= '0';
s_var3_access_d2 <= '0';
else else
s_var1_access(0) <= var1_access_a_i; s_var1_access_d1 <= var1_access_a_i;
s_var2_access(0) <= var2_access_a_i; s_var1_access_d2 <= s_var1_access_d1;
s_var3_access(0) <= var3_access_a_i;
s_var1_access(1) <= s_var1_access(0); s_var2_access_d1 <= var2_access_a_i;
s_var2_access(1) <= s_var2_access(0); s_var2_access_d2 <= s_var2_access_d1;
s_var3_access(1) <= s_var3_access(0);
s_var3_access_d1 <= var3_access_a_i;
s_var3_access_d2 <= s_var3_access_d1;
end if; end if;
end if; end if;
end process; end process;
...@@ -153,40 +161,40 @@ begin ...@@ -153,40 +161,40 @@ begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if ((nFIP_rst_i = '1') or (reset_status_bytes_i = '1')) then -- the byte is reinitialized if ((nFIP_rst_i = '1') or (reset_status_bytes_i = '1')) then -- the byte is reinitialized
status_byte_o <= (others => '0'); -- after having been delivered nFIP_status_byte_o <= (others => '0'); -- after having been delivered
else else
if ((var1_rdy_i = '0' and s_var1_access(1) = '1') or -- since the last time the status if ((var1_rdy_i = '0' and s_var1_access_d2 = '1') or -- since the last time the status
(var2_rdy_i = '0' and s_var2_access(1) = '1')) then -- byte was delivered, (var2_rdy_i = '0' and s_var2_access_d2 = '1')) then -- byte was delivered,
status_byte_o(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cosmd nFIP_status_byte_o(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cosmd
end if; -- variable when it was not ready end if; -- variable when it was not ready
if ((var3_rdy_i = '0') and (s_var3_access(1) = '1')) then -- since the last time the status if ((var3_rdy_i = '0') and (s_var3_access_d2 = '1')) then -- since the last time the status
status_byte_o(c_U_PACER_INDEX) <= '1'; -- byte was delivered, nFIP_status_byte_o(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
end if; -- the user logic accessed a prod end if; -- the user logic accessed a prod
-- variable when it was not ready -- variable when it was not ready
if ((var_i = var_1 or var_i = var_2) and (code_violation_p_i = '1')) then if ((var_i = var_1 or var_i = var_2) and (code_violation_p_i = '1')) then
status_byte_o(c_R_BNER_INDEX) <= '1'; -- since the last time the status nFIP_status_byte_o(c_R_BNER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered, -- byte was delivered,
end if; -- a consumed var arrived for end if; -- a consumed var arrived for
-- this station with a manch code -- this station with a manch code
-- violation (on the rp_dat.Data) -- violation (on the rp_dat.Data)
if ((var_i = var_1 or var_i = var_2)and(crc_wrong_p_i = '1')) then if ((var_i = var_1 or var_i = var_2)and(crc_wrong_p_i = '1')) then
status_byte_o(c_R_FCSER_INDEX) <= '1'; -- since the last time the status nFIP_status_byte_o(c_R_FCSER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered, -- byte was delivered,
end if; -- a consumed var with a wrong CRC end if; -- a consumed var with a wrong CRC
-- arrived for this station -- arrived for this station
if (fd_wdgn_i = '0') then -- since the last time the status if (fd_wdgn_i = '0') then -- since the last time the status
status_byte_o(c_T_TXER_INDEX) <= '1'; -- byte was delivered, nFIP_status_byte_o(c_T_TXER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for end if; -- there has been a signal for
-- a FIELDRIVE transmission error -- a FIELDRIVE transmission error
if (fd_txer_i = '1') then -- since the last time the status if (fd_txer_i = '1') then -- since the last time the status
status_byte_o(c_T_WDER_INDEX) <= '1'; -- byte was delivered, nFIP_status_byte_o(c_T_WDER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for a end if; -- there has been a signal for a
-- FIELDRIVE watchdog timer problem -- FIELDRIVE watchdog timer problem
end if; end if;
...@@ -197,17 +205,17 @@ end process; ...@@ -197,17 +205,17 @@ end process;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Refreshment_bit_Formation: Formation of the refreshment bit (used in --!@brief Synchronous process Refreshment_bit_Formation: Formation of the refreshment bit (used in
--! the mps status byte). It is set to 1 if the user has updated the produced variable (var3_access --! the mps status byte). It is set to 1 if the user has updated the produced variable (var3_access
--! has been asserted) since the last transmission of the variable. --! has been asserted since the last time a variable was produced).
refreshment_bit_formation: process(uclk_i) refreshment_bit_formation: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_rst_i = '1' or reset_status_bytes_i = '1' then if nFIP_rst_i = '1' or reset_status_bytes_i = '1' then -- the bit is reinitialized
s_refreshment <= '0'; s_refreshment <= '0'; -- after having been delivered
else else
if (var3_access_a_i = '1') then if (var3_access_a_i = '1') then -- indication that the memory has been accessed
s_refreshment <= '1'; s_refreshment <= '1';
end if; end if;
...@@ -223,14 +231,14 @@ end process; ...@@ -223,14 +231,14 @@ end process;
begin begin
if slone_i='1' then if slone_i='1' then
mps_byte_o <= (others => '0'); mps_status_byte_o <= (others => '0');
mps_byte_o (c_REFRESHMENT_INDEX) <= '1'; mps_status_byte_o (c_REFRESHMENT_INDEX) <= '1';
mps_byte_o (c_SIGNIFICANCE_INDEX) <= '1'; mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= '1';
else else
mps_byte_o <= (others => '0'); mps_status_byte_o <= (others => '0');
mps_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment; mps_status_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_byte_o (c_SIGNIFICANCE_INDEX) <= s_refreshment; mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= s_refreshment;
end if; end if;
end process; end process;
......
wf_tx.vhd
View file @ a702526a
...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! wf_engine \n --! wf_engine \n
--! tx_engine \n --! tx_engine \n
--! clk_gen \n --! clk_gen \n
--! reset_logic \n --! wf_reset_unit \n
--! consumed_ram \n --! consumed_ram \n
-- --
-- --
...@@ -55,7 +55,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -55,7 +55,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> v0.02 PAS Entity Ports added, start of architecture content --! -> v0.02 PAS Entity Ports added, start of architecture content
--! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit --! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit
--! briefly index_offset_i needed to arrive 1 clock tick earlier --! briefly byte_index_i needed to arrive 1 clock tick earlier
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -75,7 +75,7 @@ entity wf_tx is ...@@ -75,7 +75,7 @@ entity wf_tx is
-- user interface general signals -- user interface general signals
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- Signals from the wf_engine_control -- Signals from the wf_engine_control
...@@ -88,11 +88,11 @@ entity wf_tx is ...@@ -88,11 +88,11 @@ entity wf_tx is
-- crc bytes follow -- crc bytes follow
-- Signals from the wf_produced_vars -- Signals from the wf_produced_vars
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector (7 downto 0);
--! data byte to be delivered --! data byte to be delivered
-- Signal from the wf_rx_tx_osc -- Signal from the wf_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector(C_CLKFCDLENTGTH-1 downto 0); tx_clk_p_buff_i : in std_logic_vector (C_CLKFCDLENTGTH-1 downto 0);
--! clk for transmission synchronization --! clk for transmission synchronization
-- OUTPUTS -- OUTPUTS
...@@ -125,9 +125,9 @@ architecture rtl of wf_tx is ...@@ -125,9 +125,9 @@ architecture rtl of wf_tx is
signal s_bit_index_load, s_decr_index : std_logic; signal s_bit_index_load, s_decr_index : std_logic;
signal s_bit_index_is_zero : std_logic; signal s_bit_index_is_zero : std_logic;
signal s_bit_index, s_bit_index_top : unsigned(4 downto 0); signal s_bit_index, s_bit_index_top : unsigned(4 downto 0);
signal s_byte : std_logic_vector(7 downto 0); signal s_byte : std_logic_vector (7 downto 0);
signal s_manchester_crc : std_logic_vector(31 downto 0); signal s_manchester_crc : std_logic_vector (31 downto 0);
signal s_crc_byte_manch, s_byte_manch : std_logic_vector(15 downto 0); signal s_crc_byte_manch, s_byte_manch : std_logic_vector (15 downto 0);
--================================================================================================= --=================================================================================================
...@@ -156,10 +156,10 @@ begin ...@@ -156,10 +156,10 @@ begin
--! finally a combinatorial process to manage the output signals), which are the 3 processes that --! finally a combinatorial process to manage the output signals), which are the 3 processes that
--! follow. --! follow.
--! The signal tx_clk_p_buff_i is used for the synchronization of the transitions of the state --! The signal tx_clk_p_buff_i is used for the synchronization of the state transitions of the
--! machine as well as the actions on the output signals. --! machine as well as of the actions on the output signals.
-- The following draft drawing shows the transitions of the signal tx_clk_p_buff_i with respect to -- The following drawing shows the transitions of the signal tx_clk_p_buff_i with respect to
-- the signal tx_clk (line driver half bit clock). -- the signal tx_clk (line driver half bit clock).
-- tx_clk: __________|----------------|________________|----------------|_______________ -- tx_clk: __________|----------------|________________|----------------|_______________
...@@ -174,7 +174,7 @@ begin ...@@ -174,7 +174,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "idle state": signals initializations -- "idle state": signals initializations
-- jump to "send_fss" state after a pulse arrival from the signal start_produce_p_i (controlled by the -- jump to "send_fss" state after a pulse on the signal start_produce_p_i (controlled by the
-- wf_engine_control) -- wf_engine_control)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -189,9 +189,9 @@ begin ...@@ -189,9 +189,9 @@ begin
-- the tx_clk_p_buff(3) assertion. -- the tx_clk_p_buff(3) assertion.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_data_byte state": delivery of manchester encoded bits of data that arrive from the -- "send_data_byte" state: delivery of manchester encoded bits of data that arrive from the
-- wf_produced_vars unit (byte_i), with the coordination of the wf_engine_control (byte_ready_p_i) -- wf_produced_vars unit (byte_i), with the coordination of the wf_engine_control (byte_ready_p_i)
-- request of a new byte on tx_clk_p_buff (0) assertion -- request of a new byte on tx_clk_p_buff (0) assertion (with s_bit_index = 0)
-- bit delivery after tx_clk_p_buff (1) assertion -- bit delivery after tx_clk_p_buff (1) assertion
-- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1)) -- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1))
-- s_bit_index updated after tx_clk_p_buff (3) assertion (the s_bit_index here loops several times -- s_bit_index updated after tx_clk_p_buff (3) assertion (the s_bit_index here loops several times
...@@ -202,7 +202,7 @@ begin ...@@ -202,7 +202,7 @@ begin
-- start_produce_p_i signal; for the rest, there is a request of a new byte when the s_bit_index -- start_produce_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal -- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal
-- triggers the wf_control_engine to send a new address to the memory of the produced_vars unit (new -- triggers the wf_control_engine to send a new address to the memory of the produced_vars unit (new
-- address available on tx_clk_p_buff (1)), which in turn will give an output one uclk cycle later
-- (on tx_clk_p_buff (2)), exactly on the assertion of the byte_ready_p_i. Finally the first bit of -- (on tx_clk_p_buff (2)), exactly on the assertion of the byte_ready_p_i. Finally the first bit of
-- this new byte starts being delivered after tx_clk_p_buff (3) assertion. -- this new byte starts being delivered after tx_clk_p_buff (3) assertion.
......
wf_tx_rx.vhd
View file @ a702526a
...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! On reception it depacketises the data and only presents the actual data --! On reception it depacketises the data and only presents the actual data
--! contents. It also verifies the FCS (Frame Checksum, CRC).\n --! contents. It also verifies the FCS (Frame Checksum, CRC).\n
--! On transmission it packetises the data and adds the FCS. --! On transmission it packetises the data and adds the FCS.
--! The unit wf_rx_osc recovers the carrier clock during --! The unit wf_rx_tx_osc recovers the carrier clock during
--! --!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- --
...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! wf_engine \n --! wf_engine \n
--! tx_engine \n --! tx_engine \n
--! clk_gen \n --! clk_gen \n
--! reset_logic \n --! wf_reset_unit \n
--! consumed_ram \n --! consumed_ram \n
--! --!
--! --!
...@@ -69,25 +69,26 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -69,25 +69,26 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
entity wf_tx_rx is entity wf_tx_rx is
port ( port (
uclk_i : in std_logic; --! User Clock uclk_i : in std_logic; --! User Clock
nFIP_rst_i : in std_logic; nFIP_rst_i : in std_logic;
start_produce_p_i : in std_logic; reset_rx_unit_p_i : in std_logic;
request_byte_p_o : out std_logic; start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic; request_byte_p_o : out std_logic;
byte_i : in std_logic_vector(7 downto 0); byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic; byte_i : in std_logic_vector (7 downto 0);
tx_data_o : out std_logic; last_byte_p_i : in std_logic;
tx_enable_o : out std_logic; d_a_i : in std_logic;
d_clk_o : out std_logic; rate_i : in std_logic_vector (1 downto 0);
d_a_i : in std_logic; tx_data_o : out std_logic;
rate_i : in std_logic_vector(1 downto 0); tx_enable_o : out std_logic;
byte_ready_p_o : out std_logic; d_clk_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0); byte_ready_p_o : out std_logic;
last_byte_p_o : out std_logic; byte_o : out std_logic_vector (7 downto 0);
fss_decoded_p_o : out std_logic; last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic; code_violation_p_o : out std_logic;
crc_wrong_p_o : out std_logic; crc_wrong_p_o : out std_logic;
crc_ok_p_o : out std_logic crc_ok_p_o : out std_logic
); );
end entity wf_tx_rx; end entity wf_tx_rx;
...@@ -103,15 +104,15 @@ architecture rtl of wf_tx_rx is ...@@ -103,15 +104,15 @@ architecture rtl of wf_tx_rx is
constant C_CLKFCDLENTGTH : natural := 4; constant C_CLKFCDLENTGTH : natural := 4;
signal s_data_in_d3 : std_logic_vector(2 downto 0); signal s_data_in_d3 : std_logic_vector (2 downto 0);
signal s_data_in_r_edge, s_data_in_f_edge : std_logic; signal s_data_in_r_edge, s_data_in_f_edge : std_logic;
signal s_d_filtered : std_logic; signal s_d_filtered : std_logic;
signal s_first_fe : std_logic; signal s_first_fe : std_logic;
signal s_clk_carrier_p : std_logic; signal s_clk_carrier_p : std_logic;
signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p : std_logic; signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_edge_window, edge_180_window : std_logic; signal s_edge_window, edge_180_window : std_logic;
signal s_data_in_edge, s_code_violation : std_logic; signal s_data_in_edge : std_logic;
signal s_clk_fixed_carrier_p_d : std_logic_vector(C_CLKFCDLENTGTH - 1 downto 0); signal s_clk_fixed_carrier_p_d : std_logic_vector (C_CLKFCDLENTGTH - 1 downto 0);
begin begin
...@@ -155,6 +156,7 @@ begin ...@@ -155,6 +156,7 @@ begin
PORT MAP( PORT MAP(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i, nFIP_rst_i => nFIP_rst_i,
reset_rx_unit_p_i => reset_rx_unit_p_i,
byte_ready_p_o => byte_ready_p_o, byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o, byte_o => byte_o,
last_byte_p_o => last_byte_p_o, last_byte_p_o => last_byte_p_o,
...@@ -173,7 +175,7 @@ begin ...@@ -173,7 +175,7 @@ begin
); );
uwf_rx_osc :wf_rx_osc uwf_rx_osc :wf_rx_tx_osc
generic map(C_COUNTER_LENGTH => 11, generic map(C_COUNTER_LENGTH => 11,
C_QUARTZ_PERIOD => 24.8, C_QUARTZ_PERIOD => 24.8,
...@@ -195,7 +197,7 @@ begin ...@@ -195,7 +197,7 @@ begin
rx_adjac_bits_window_o => edge_180_window rx_adjac_bits_window_o => edge_180_window
); );
Udeglitcher : deglitcher Udeglitcher : wf_rx_deglitcher
generic map (C_ACULENGTH => 10) generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i, Port map( uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i, nFIP_rst_i => nFIP_rst_i,
......
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