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nanoFIP - Gateware
Commit aa169408 authored by Tristan Gingold's avatar Tristan Gingold
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Adjust code for igloo2: 

Add top nanofip.vhd file
Use a generic dualport ram
Fix VHDL staticness issues
parent e51c789c
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Showing with 38 additions and 61 deletions
Manifest.py
View file @ aa169408
files = "top/nanofip.vhd"
modules = {"local" : ["src"]}
src/dualram_512x8.vhd
View file @ aa169408
......@@ -46,8 +46,8 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Component specific library
library PROASIC3; -- ProASIC3 library
use PROASIC3.all;
--library PROASIC3; -- ProASIC3 library
--use PROASIC3.all;
--=================================================================================================
......@@ -115,7 +115,7 @@ architecture RAM4K9 of dualram_512x8 is
-- pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
generic (MEMORYFILE : string := "");
-- generic (MEMORYFILE : string := "");
port(
ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
......
src/wf_dualram_512x8_clka_rd_clkb_wr.vhd
View file @ aa169408
......@@ -50,10 +50,6 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_dualram_512x8_clka_rd_clkb_wr
......@@ -83,51 +79,19 @@ end wf_dualram_512x8_clka_rd_clkb_wr;
-- architecture declaration
--=================================================================================================
architecture syn of wf_dualram_512x8_clka_rd_clkb_wr is
signal s_one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
-- Port A used for reading only, port B for writing only.
-- for triplication: G_memory_triplication: for I in 0 to 2 generate
DualRam : dualram_512x8
port map(
DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => s_one,
CLKA => clk_porta_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
RESETn => s_one,
DOUTA => data_porta_o, -- for triplication: s_data_o_A_array(I)
DOUTB => open);
-- end generate;
---------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
-- (s_data_o_A_array(1) and s_data_o_A_array(2)) or
-- (s_data_o_A_array(2) and s_data_o_A_array(0));
process (clk_porta_i, clk_portb_i, write_en_portb_i)
type t_mem is array (2**9 downto 0) of std_logic_vector (7 downto 0);
variable mem : t_mem;
begin
if rising_edge(clk_porta_i) then
data_porta_o <= mem (to_integer(unsigned(addr_porta_i)));
end if;
if rising_edge(clk_portb_i) and write_en_portb_i = '1' then
mem (to_integer(unsigned(addr_portb_i))) := data_portb_i;
end if;
end process;
end syn;
--=================================================================================================
......
src/wf_engine_control.vhd
View file @ aa169408
......@@ -755,49 +755,49 @@ begin
case rx_byte_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue =>
when c_VAR_PRESENCE_CODE =>
s_var_aux <= var_presence;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue =>
when c_VAR_IDENTIF_CODE =>
s_var_aux <= var_identif;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue =>
when c_VAR_1_CODE =>
s_var_aux <= var_1;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue =>
when c_VAR_2_CODE =>
s_var_aux <= var_2;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue =>
when c_VAR_3_CODE =>
s_var_aux <= var_3;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue =>
when c_VAR_RST_CODE =>
s_var_aux <= var_rst;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_4_INDEX).hexvalue =>
when c_VAR_4_CODE =>
s_var_aux <= var_4;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_4_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_4_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_5_INDEX).hexvalue =>
when c_VAR_5_CODE =>
s_var_aux <= var_5;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_5_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_5_INDEX).broadcast;
......
src/wf_package.vhd
View file @ aa169408
......@@ -347,11 +347,19 @@ package wf_package is
constant c_VAR_4_INDEX : integer := 6;
constant c_VAR_5_INDEX : integer := 7;
constant c_VAR_PRESENCE_CODE : std_logic_vector (7 downto 0) := x"14";
constant c_VAR_IDENTIF_CODE : std_logic_vector (7 downto 0) := x"10";
constant c_VAR_3_CODE : std_logic_vector (7 downto 0) := x"06";
constant c_VAR_1_CODE : std_logic_vector (7 downto 0) := x"05";
constant c_VAR_2_CODE : std_logic_vector (7 downto 0) := x"91";
constant c_VAR_RST_CODE : std_logic_vector (7 downto 0) := x"e0";
constant c_VAR_4_CODE : std_logic_vector (7 downto 0) := x"aa";
constant c_VAR_5_CODE : std_logic_vector (7 downto 0) := x"ab";
constant c_VARS_ARRAY : t_var_array(0 to 7) :=
(c_VAR_PRESENCE_INDEX => (var => var_presence,
hexvalue => x"14",
hexvalue => c_VAR_PRESENCE_CODE,
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
......
top/nanofip.vhd
View file @ aa169408
......@@ -316,7 +316,10 @@ entity nanofip is port(
jc_tms_o : out std_logic; -- Drives the JTAG Test Mode Select of the target TAP
jc_tdi_o : out std_logic; -- Drives the JTAG Test Data In of the target TAP
jc_tck_o : out std_logic); -- Drives the JTAG Test Clock of the target TAP
jc_tck_o : out std_logic; -- Drives the JTAG Test Clock of the target TAP
led_rx_ok_o : out std_logic;
led_rx_err_o : out std_logic);
end entity nanofip;
......@@ -438,7 +441,8 @@ begin
rx_crc_wrong_p_o => s_rx_crc_wrong_p);
-------------------------------------------------------------
led_rx_ok_o <= s_rx_fss_crc_fes_ok_p;
led_rx_err_o <= s_rx_crc_wrong_p;
---------------------------------------------------------------------------------------------------
-- wf_production --
......
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