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nanoFIP - Gateware
Commit ad26318d authored by egousiou's avatar egousiou
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small units eliminated; 

corrections on nFIP status byte

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@170 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 4abbe8b9
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DualClkRAM.vhd
View file @ ad26318d
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! ProASIC3 library
library PROASIC3;
library PROASIC3; --! component specific library
--! ProASIC3 packages
use PROASIC3.all;
......@@ -31,7 +31,7 @@ use PROASIC3.all;
---------------------------------------------------------------------------------------------------
--
--
--! @brief Instantiation of a template RAM4K9 memory component with
--! @brief Instantiation of a template ProAsic3 RAM4K9 memory component with
--! o word width : 8 bits and
--! o depth : 512 bytes.
--
......@@ -183,6 +183,7 @@ architecture RAM4K9 of DualClkRAM is
-- architecture begin
--=================================================================================================
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
......@@ -200,7 +201,7 @@ begin
port map (
-- INPUTS
-- INPUTS concerning port A
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
DINA8 => GROUND,
DINA7 => DINA(7),
......@@ -235,7 +236,7 @@ begin
PIPEA => GROUND,
WMODEA => GROUND,
-- INPUTS concerning port B
-- inputs concerning port B
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
......@@ -269,11 +270,10 @@ begin
BLKB => GROUND,
PIPEB => GROUND,
WMODEB => GROUND,
-- reset
-- input reset
RESET => RESETn,
-- Oututs
-------------------------------
-- OUTPUTS
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => open,
......@@ -296,8 +296,8 @@ begin
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0)
);
DOUTB0 => DOUTB(0));
-------------------------------
end RAM4K9;
--=================================================================================================
......
nanofip.vhd
View file @ ad26318d
......@@ -156,7 +156,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_inputs_synchronizer \n
--! WF_reset_unit \n
--! WF_model_constr_dec \n
--! WF_tx_rx_osc \n
......@@ -323,7 +322,7 @@ architecture struc of nanofip is
signal s_rx_rst_p, s_nfip_status_r_tler : std_logic;
signal s_prod_byte_ready_p : std_logic;
signal s_var_from_control : t_var;
signal s_data_length_from_control : std_logic_vector (7 downto 0);
signal s_data_lgth_from_control : std_logic_vector (7 downto 0);
signal s_rx_byte, s_byte_to_tx, s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_cons_prod_byte_index_from_control : std_logic_vector (7 downto 0);
......@@ -381,7 +380,7 @@ begin
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
data_o => dat_o,
nfip_status_r_tler_o => s_nfip_status_r_tler,
nfip_status_r_tler_p_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p);
---------------------------------------------------------
......@@ -428,10 +427,10 @@ begin
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
var_i => s_var_from_control,
data_length_i => s_data_length_from_control,
data_lgth_i => s_data_lgth_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
byte_request_accept_p_i => s_prod_byte_ready_p,
nfip_status_r_tler_i => s_nfip_status_r_tler,
nfip_status_r_tler_p_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_crc_or_manch_wrong_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
......@@ -460,7 +459,6 @@ begin
tx_byte_request_accept_p_i => s_prod_byte_ready_p,
tx_last_byte_p_i => s_prod_last_byte_p,
tx_start_p_i => s_start_tx_p,
tx_rst_p_i => s_rst_tx_p,
---------------------------------------------------------
tx_byte_request_p_o => s_prod_request_byte_p,
tx_data_o => fd_txd_o,
......@@ -495,9 +493,8 @@ begin
tx_byte_request_accept_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_length_o => s_data_length_from_control,
rx_rst_p_o => s_rx_rst_p,
rst_tx_p_o => s_rst_tx_p);
prod_data_lgth_o => s_data_lgth_from_control,
rx_rst_p_o => s_rx_rst_p);
---------------------------------------------------------
var1_rdy_o <= s_var1_rdy;
......
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ ad26318d
......@@ -100,13 +100,10 @@ end WF_DualClkRAM_clka_rd_clkb_wr;
--=================================================================================================
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
---------------------------------------------------------------------------------------------------
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal zero, one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal s_one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
......@@ -114,24 +111,24 @@ signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
begin
zero <= '0';
one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
s_one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
--!@brief: memory triplication
--! The component DualClkRam is generated three times.
--! Port A is used for reading only, port B for writing only.
--! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array data_o_A_array.
--! The output DOUTA from each memory is kept in the array s_data_o_A_array.
G_memory_triplication: for I in 0 to 2 generate
G_memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam
port map ( DINA => s_zeros,
UDualClkRam : DualClkRam
port map (
DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => one,
RWA => s_one,
CLKA => clk_porta_i,
DINB => data_portb_i,
......@@ -139,19 +136,20 @@ UDualClkRam : DualClkRam
RWB => s_rwB,
CLKB => clk_portb_i,
RESETn => one,
RESETn => s_one,
DOUTA => s_data_o_A_array(I),
DOUTB => open);
DOUTA => data_o_A_array(I),
DOUTB => open) ;
end generate;
end generate;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial Majority_Voter
Majority_Voter: data_porta_o <= (data_o_A_array(0) and data_o_A_array(1)) or
(data_o_A_array(1) and data_o_A_array(2)) or
(data_o_A_array(2) and data_o_A_array(0));
Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
(s_data_o_A_array(1) and s_data_o_A_array(2)) or
(s_data_o_A_array(2) and s_data_o_A_array(0));
end syn;
--=================================================================================================
......
wf_bits_to_txd.vhd
View file @ ad26318d
......@@ -47,7 +47,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! WF_tx_osc \n
--! WF_tx_serializer \n
--
--
......@@ -96,7 +96,7 @@ entity WF_bits_to_txd is
txd_bit_index_i : in unsigned(4 downto 0); --! index of a bit inside a byte
-- Signals from the WF_tx_rx_osc unit
-- Signals from the WF_tx_osc unit
tx_clk_p_i : in std_logic; --!clk for transmission synchronization
......@@ -112,7 +112,8 @@ end entity WF_bits_to_txd;
--! architecture declaration
--=================================================================================================
architecture rtl of WF_bits_to_txd is
signal s_fss : std_logic_vector (31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -155,7 +156,7 @@ begin
end if;
end process;
s_fss<=c_FSS;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
......
wf_cons_bytes_processor.vhd
View file @ ad26318d
......@@ -27,8 +27,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit is consuming the data bytes that are arriving from the WF_rx_deserializer,
--! according to the following:
--! @brief The unit is consuming the RP_DAT data bytes that are arriving from the
--! WF_fd_receiver, according to the following:
--!
--! o If the consumed variable had been a var_1 or a var_2:
--!
......@@ -39,9 +39,15 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o If the operation is in stand-alone mode: the unit is transferring the 2 appli-
--! cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O
--!
--! o If the consumed variable had been a var_rst, the 2 application-data bytes are just
--! o If the consumed variable had been a var_rst, the 2 application-data bytes are
--! identified and sent to the WF_reset_unit.
--!
--! Note: The validity of the consumed bytes (stored in the memory or transfered to DATO
--! or transfered to the WF_reset_unit) is indicated by the "nanoFIP User Interface,
--! NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY or the nanoFIP internal signals
--! rst_nFIP_and_FD_p/ assert_RSTON_p, which are treated in the WF_cons_outcome unit and
--! are assessed after the end of the reception of a complete frame.
--!
--!
--! Reminder:
--!
......@@ -49,7 +55,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! ___________ ______ _______ ________ __________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__|
--!
--! |--------LGTH bytes--------|
--! |--------&LGTH bytes-------|
--! |---------write to Consumed memory----------|
--! |-----to DAT_O-----|
--! |---to Reset Unit--|
......@@ -70,7 +76,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_deserializer \n
--! WF_fd_receiver \n
--! WF_engine_control \n
--
--
......@@ -118,7 +124,7 @@ port (
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector (8 downto 0); --! WISHBONE address to memory
-- Signals from the WF_rx_deserializer unit
-- Signals from the WF_fd_receiver unit
byte_i : in std_logic_vector (7 downto 0); --! input byte
byte_ready_p_i : in std_logic; --! indication of a new input byte
......@@ -134,17 +140,12 @@ port (
-- nanoFIP User Interface, WISHBONE Slave output
data_o : out std_logic_vector (15 downto 0);--! data out bus
-- Signals to the WF_cons_frame_validator unit
-- Signals to the WF_cons_outcome unit
cons_ctrl_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT Control byte
cons_lgth_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT Length byte
cons_pdu_byte_o : out std_logic_vector (7 downto 0); --! received RP_DAT PDY_TYPE byte
-- Signals to the WF_cons_outcome unit
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); --! content of the 1st data byte of
--! a reset variable
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0) --! content of the 2nd data byte of
--! a reset variable
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); --! received var_rst, 1st data byte
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0) --! received var_rst, 2nd data byte
);
end entity WF_cons_bytes_processor;
......@@ -155,13 +156,14 @@ end entity WF_cons_bytes_processor;
--=================================================================================================
architecture rtl of WF_cons_bytes_processor is
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned (7 downto 0);
signal s_base_addr : unsigned (8 downto 0);
signal s_write_byte_to_mem_p : std_logic;
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned (7 downto 0);
signal s_base_addr : unsigned (8 downto 0);
signal s_write_byte_to_mem_p : std_logic;
--=================================================================================================
-- architecture begin
......@@ -174,48 +176,64 @@ begin
-- Consumed & Consumed Broadcast RAM --
-- Storage (by the unit) & retreival (by the user) of consumed bytes --
---------------------------------------------------------------------------------------------------
-- !@brief Instantiation of a Dual Port Consumed RAM
--! (for both the consumed and consumed broadcast variables)
--!@brief Instantiation of a Dual Port Consumed RAM (for both the consumed and consumed broadcast
--! variables).
--! Port A is connected to WISHBONE interface for the readings from the user and
--! Port B is used by nanoFIP for the writings into the memory.
Consumed_Bytes_To_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of consumed RAM
-- first 2 bits: identification of the memory block
-- remaining 7 bits: address of a byte inside the block
-- port A: WISHBONE that reads from the Consumed RAM; port B: nanoFIP that writes
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
port map (
clk_porta_i => wb_clk_i, -- WISHBONE clock
addr_porta_i => wb_adr_i(8 downto 0), -- address of byte to be read
-----------------------------------------------------------------------------
data_porta_o => s_mem_data_out, -- output byte read
-----------------------------------------------------------------------------
addr_porta_i => wb_adr_i, -- address of byte to be read
clk_portb_i => uclk_i, -- 40 MHz clock
addr_portb_i => s_addr(8 downto 0), -- address of byte to be written
addr_portb_i => s_addr, -- address of byte to be written
data_portb_i => byte_i, -- byte to be written
write_en_portb_i => s_write_byte_to_mem_p ); -- write enable
write_en_portb_i => s_write_byte_to_mem_p,-- write enable
--------------------------------------------
data_porta_o => s_mem_data_out); -- output byte read
--------------------------------------------
---------------------------------------------------------------------------------------------------
-- Consumed bytes to DAT_O --
-- Storage of consumed bytes to DATO --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the unit responsible for the transfering of 2 de-serialized data bytes
--! to DAT_O;
--!@brief Synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, according to the signal
--! s_slone_write_byte_p, the first or second byte of the "User Interface, NON WISHBONE" bus DAT_O
--! takes the byte byte_i.
Consumed_Bytes_To_DATO: WF_cons_bytes_to_dato
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
transfer_byte_p_i => s_slone_write_byte_p,
byte_i => byte_i,
------------------------------------------
slone_data_o => s_slone_data);
------------------------------------------
Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_slone_data <= (others => '0'); -- bus initialization
else
if s_slone_write_byte_p(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
s_slone_data(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
if s_slone_write_byte_p(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
s_slone_data(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- In stand-alone mode the 16 bits DAT_O fills up with the output of the WF_cons_bytes_to_dato
-- unit.In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory
-- In stand-alone mode the 16 bits DAT_O fills up with the s_slone_data.
-- In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory
data_o <= s_slone_data when slone_i = '1'
else "00000000" & s_mem_data_out;
......@@ -241,7 +259,7 @@ begin
--! The signals byte_index_i and Length (s_cons_lgth_byte) are used to distinguish the Control and
--! CRC bytes from the rest:
--! o the Control byte arrives when byte_index_i = 0
--! o the CRC bytes arrive $Length bytes after the Length byte
--! o the CRC bytes arrive &Length bytes after the Length byte
--! The byte_index_i signal is counting each byte after the FSS and before the FES.
--! The Length byte (s_cons_lgth_byte) is received from the WF_rx_deserializer when byte_index_i is
--! equal to 3 and indicates the amount of bytes in the frame after the Control, PDU_TYPE and itself and
......@@ -259,8 +277,8 @@ begin
-- (-1 bc the Ctrl
-- byte is not written)
Bytes_Processing: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i,two,byte_ready_p_i,s_cons_lgth_byte)
begin
......@@ -283,11 +301,12 @@ begin
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits
if byte_index_i > c_LENGTH_BYTE_INDEX then -- after the reception
if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception
-- of the Length byte
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then -- less or eq
s_write_byte_to_mem_p <= byte_ready_p_i; -- "Length" amount of
-- bytes are written
--(to avoid writing CRC!)
else
s_write_byte_to_mem_p <= '0';
end if;
......@@ -333,7 +352,7 @@ begin
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then
if byte_index_i > c_LENGTH_BYTE_INDEX then
if byte_index_i > c_LGTH_BYTE_INDEX then
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then
s_write_byte_to_mem_p <= byte_ready_p_i;
......@@ -410,12 +429,12 @@ end process;
---------------------------------------------------------------------------------------------------
-- Control, PDU_TYPE, Length bytes --
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Register_Ctrl_PDU_Length_bytes: Storage of the Control, PDU_TYPE
--! and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_cons_frame_validator
--! unit that validates them and accordingly signals the WF_outcome unit for the activation of the
--! VAR1_RDY(for a var_1), VAR2_RDY(for a var_2), assert_rston_p & rst_nfip_and_fd_p(for a var_rst).
--!@brief Synchronous process Register_Ctrl_PDU_LGTH_bytes: Storage of the Control, PDU_TYPE
--! and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_cons_outcome
--! unit that validates them and accordingly activates the VAR1_RDY(for a var_1),
--! VAR2_RDY(for a var_2), assert_rston_p & rst_nfip_and_fd_p(for a var_rst).
Register_Ctrl_PDU_Length_bytes: process (uclk_i)
Register_Ctrl_PDU_LGTH_bytes: process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -433,7 +452,7 @@ Register_Ctrl_PDU_Length_bytes: process (uclk_i)
elsif ((byte_index_i = c_PDU_BYTE_INDEX) and (byte_ready_p_i ='1')) then
cons_pdu_byte_o <= byte_i;
elsif ((byte_index_i = c_LENGTH_BYTE_INDEX) and (byte_ready_p_i ='1')) then
elsif ((byte_index_i = c_LGTH_BYTE_INDEX) and (byte_ready_p_i ='1')) then
s_cons_lgth_byte <= byte_i;
end if;
......@@ -446,7 +465,7 @@ Register_Ctrl_PDU_Length_bytes: process (uclk_i)
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
cons_lgth_byte_o <= s_cons_lgth_byte;
end architecture rtl;
......
wf_cons_bytes_to_dato.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_cons_bytes_to_dato.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_bytes_to_dato --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief In stand-alone mode, after the reception of a consumed (var_1) or a consumed
--! broadcast variable (var_2), the unit is responsible for transering the two
--! application-data bytes to the 2-bytes long bus DAT_O.
--! The bytes are put in the bus one by one as they arrive, as the signal
--! transfer_byte_p_i indicates.
--!
--! Note: The validity of these transfered bytes is indicated by the "nanoFIP
--! User Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY which arrive later, after
--! the end of the reception of the consumed frame.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 10/01/2011
--
--
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 10/1/2011 v0.02 EG unit renamed from WF_slone_cons_bytes_to_dato to
--! WF_cons_bytes_to_dato; cleaning-up + commenting
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_cons_bytes_to_dato
--=================================================================================================
entity WF_cons_bytes_to_dato is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_bytes_processor
byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte
transfer_byte_p_i : in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_O(7:0)
--! 10: byte_i transfered to DAT_O(15:8)
-- OUTPUTS
-- nanoFIP, User Interface NON WISHBONE output
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
);
end entity WF_cons_bytes_to_dato;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_bytes_to_dato is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, according to the signal
--! transfer_byte_p_i, the first or second byte of the "User Interface, NON WISHBONE" bus DAT_O
--! takes the byte byte_i.
Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization
else
if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
slone_data_o(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
slone_data_o(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_cons_frame_validator.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_cons_frame_validator.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_frame_validator --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Validation of a consumed RP_DAT frame with respect to the correctness of:
--! o the Control, PDU_TYPE and Length bytes;
--! the bytes are received from the the WF_cons_bytes_processor unit.
--! o the CRC, FSS, FES bytes and the Manchester encoding;
--! the rx_fss_crc_fes_manch_ok_p_i pulse from the WF_rx_deserializer unit groups
--! these checks.
--!
--! The output cons_frame_ok_p is used by the WF_cons_outcome unit, which handles
--! accordingly the signals VAR1_RDY/ VAR2_RDY (if it had been a var_1 or a var_2)
--! or the signals nFIP_and_FD_p/ assert_RSTON_p (if it had been a var_rst)
--!
--!
--! Reminder:
--!
--! Consumed RP_DAT frame structure :
--! ___________ ______ _______ ______ _________________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__|
--!
--! |---------------LGTH bytes---------------|
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 10/12/2010
--
--
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_cons_bytes_processor \n
--! WF_engine_control \n
--! WF_rx_deserializer \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/2010 v0.02 EG code cleaned-up+commented \n
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_cons_frame_validator
--=================================================================================================
entity WF_cons_frame_validator is
port (
-- INPUTS
-- Signals from the WF_cons_bytes_processor unit
cons_ctrl_byte_i : in std_logic_vector (7 downto 0); --! received RP_DAT Control byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0); --! received RP_DAT Length byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0); --!received RP_DAT PDU_TYPE byte
-- Signal from the WF_rx_deserializer unit
rx_fss_crc_fes_manch_ok_p_i: in std_logic; --! indication of a frame with correct FSS, FES, CRC
--! and manch. encoding
rx_crc_or_manch_wrong_p_i : in std_logic; --! indication .................
-- Signals from the WF_engine_control unit
rx_byte_index_i : in std_logic_vector (7 downto 0); --! index of byte being received
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- Signal to the WF_cons_outcome unit
cons_frame_ok_p_o : out std_logic; --! pulse at the end of the FES
--! indicating a valid received RP_DAT frame
-- Signal to the WF_status_bytes_gen unit
nfip_status_r_tler_o : out std_logic --! received PDU_TYPE or Length error
--! nanoFIP status byte bit 6
);
end entity WF_cons_frame_validator;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_frame_validator is
signal s_cons_ctrl_byte_ok, s_cons_pdu_byte_ok, s_cons_lgth_byte_ok : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Consumed_Frame_Validator: validation of an RP_DAT
--! frame with respect to the Ctrl, PDU_TYPE and Length bytes as well as to the CRC, FSS, FES and
--! to the Manchester encoding. The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
--! arrive at the beginning of a frame, have been registered and keep their values until the end
--! of it. The signal rx_fss_crc_fes_manch_ok_p_i, is a pulse at the end of the FES that combines
--! the checks of the FSS, CRC, FES and of the manch. encoding.
Consumed_Frame_Validator: process (var_i, cons_ctrl_byte_i, rx_byte_index_i, cons_pdu_byte_i,
rx_fss_crc_fes_manch_ok_p_i, cons_lgth_byte_i, rx_crc_or_manch_wrong_p_i)
begin
case var_i is
-------------------------------------------------------------------------------------------------
when var_1 | var_2 | var_rst => -- only for consumed RP_DAT frames
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if cons_ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_cons_ctrl_byte_ok <= '1'; -- RP_DAT.CTRL byte
else
s_cons_ctrl_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if cons_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_cons_pdu_byte_ok <= '1'; -- PDU_TYPE byte
else
s_cons_pdu_byte_ok <= '0' ;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_fss_crc_fes_manch_ok_p_i = '1' or rx_crc_or_manch_wrong_p_i = '1' then -- checking the
-- RP_DAT.Data.Length byte,
-- when the FES arrives
if unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5) then
s_cons_lgth_byte_ok <= '1'; -- rx_byte_index starts counting
-- from 0 and apart from the
-- user-data bytes, also counts the
else -- Control, PDU_TYPE, Length,
-- the 2 CRC and the FES bytes
s_cons_lgth_byte_ok <= '0';
end if;
else
s_cons_lgth_byte_ok <= '0';
end if;
-------------------------------------------------------------------------------------------------
when others =>
s_cons_ctrl_byte_ok <= '0';
s_cons_pdu_byte_ok <= '0';
s_cons_lgth_byte_ok <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
cons_frame_ok_p_o <= rx_fss_crc_fes_manch_ok_p_i and
s_cons_lgth_byte_ok and
s_cons_ctrl_byte_ok and
s_cons_pdu_byte_ok;
nfip_status_r_tler_o <= s_cons_lgth_byte_ok and
s_cons_ctrl_byte_ok and
s_cons_pdu_byte_ok;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_cons_outcome.vhd
View file @ ad26318d
......@@ -27,21 +27,39 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--
--! @brief According to the consumed variable that has been received (var_1, var_2, var_rst)
--! and the output of the WF_cons_frame_validator, the unit generates the signals:
--! @brief The unit starts by validating a consumed RP_DAT frame with respect to the
--! correctness of:
--! o the Control, PDU_TYPE and Length bytes;
--! the bytes are received from the the WF_consumption unit.
--! o the CRC, FSS, FES bytes and the Manchester encoding;
--! the rx_fss_crc_fes_manch_ok_p_i pulse from the WF_fd_receiver unit groups
--! these checks.
--!
--! o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY,
--! Then, according to the consumed variable that has been received (var_1, var_2,
--! var_rst) it generates the signals:
--! o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY.
--! o "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o, also used by
--! the WF_status_bytes_generator unit (nanoFIP status byte, bit 4).
--! o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit.
--
--!
--!
--! Reminder:
--!
--! Consumed RP_DAT frame structure :
--! ___________ ______ _______ ______ _________________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__|
--!
--! |-----------&LGTH bytes-----------|
--!
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 14/01/2011
--! @date 22/02/2011
--
--
--! @version v0.04
--! @version v0.05
--
--
--! @details \n
......@@ -49,8 +67,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_cons_frame_validator \n
--! WF_cons_bytes_processor \n
--! WF_fd_receiver \n
--! WF_consumption \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -65,6 +83,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting
--! -> 01/2010 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome
--! (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3)
--! -> 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator
--
---------------------------------------------------------------------------------------------------
--
......@@ -72,13 +91,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the variables var_1, var_2 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -99,24 +111,36 @@ entity WF_cons_outcome is
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --! pulse after a correct cons frame
-- Signal from the WF_fd_receiver unit
rx_fss_crc_fes_manch_ok_p_i : in std_logic; --! indication of a frame with correct FSS, FES, CRC
--! and manch. encoding; pulse upon FES detection
-- Signal from the WF_engine_control unit
var_i : in t_var; --! variable type that is being treated
rx_crc_or_manch_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC or manch.
-- pulse upon FES detection
-- Signals from the WF_cons_bytes_processor
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);--! 1st data-byte of a received var_rst
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);--! 2nd data-byte of a received var_rst
-- Signals from the WF_consumption unit
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Control byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT Length byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0);--! received RP_DAT PDU_TYPE byte
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 1st data-byte
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);--! received var_rst RP_DAT, 2nd data-byte
-- Signals from the WF_engine_control unit
rx_byte_index_i : in std_logic_vector (7 downto 0);--! index of byte being received
var_i : in t_var; --! variable type that is being treated
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic; --! signals new data is received and can safely be read
var2_rdy_o : out std_logic; --! signals new data is received and can safely be read
var1_rdy_o : out std_logic;--! signals new data is received and can safely be read
var2_rdy_o : out std_logic;--! signals new data is received and can safely be read
-- Signal to the WF_status_bytes_gen unit
nfip_status_r_tler_p_o : out std_logic;--! received PDU_TYPE or Length error
--! nanoFIP status byte bit 4
-- Signals to the WF_reset_unit
assert_rston_p_o : out std_logic; --! indicates that a var_rst with its 2nd data-byte
assert_rston_p_o : out std_logic;--! indicates that a var_rst with its 2nd data-byte
--! containing the station's address has been
--! correctly received
......@@ -132,14 +156,70 @@ end entity WF_cons_outcome;
--=================================================================================================
architecture rtl of WF_cons_outcome is
signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
signal s_var_type_match, s_cons_frame_ok_p : std_logic;
signal s_var1_received, s_var2_received : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Sequential process Frame_Validation: validation of a consumed RP_DAT frame, with
--! respect to the Ctrl, PDU_TYPE and Length bytes as well as to the CRC, FSS, FES and to the
--! Manchester encoding. The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
--! arrive at the beginning of a frame, have been registered and keep their values until the end
--! of it. The signal rx_fss_crc_fes_manch_ok_p_i, is a pulse at the end of the FES that combines
--! the checks of the FSS, CRC, FES and of the manch. encoding.
--! To check the correctness of the the RP_DAT.Data.Length byte, we compare it to the value of the
--! rx_byte_index, when the FES is detected (pulse rx_fss_crc_fes_manch_ok_p_i).
--! Note: In addition to the &Length bytes, the rx_byte_index also counts the Control, PDU_TYPE,
--! Length, the 2 CRC and the FES bytes (and counting starts from 0!).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! The same process is also used for the generation of the of the nanoFIP status byte, bit 4, that
--! indicates a received PDU_TYPE or Length byte error in a consumed RP_DAT frame.
--! Note: The end of a frame is marked by either the signal rx_fss_crc_fes_manch_ok_p_i or by the
--! rx_crc_or_manch_wrong_p_i.
Frame_Validation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_cons_frame_ok_p <= '0';
else
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) then -- only consumed RP_DATs
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (rx_fss_crc_fes_manch_ok_p_i = '1') and -- FSS CRC FES Manch. check
(cons_ctrl_byte_i = c_RP_DAT_CTRL_BYTE) and -- CTRL byte check
(cons_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE) and -- PDU_TYPE byte check
(unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then --LGTH byte check
s_cons_frame_ok_p <= '1';
else
s_cons_frame_ok_p <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if ((rx_fss_crc_fes_manch_ok_p_i = '1') or (rx_crc_or_manch_wrong_p_i = '1')) and -- end of frame
((cons_pdu_byte_i /= c_PROD_CONS_PDU_TYPE_BYTE) or -- PDU_TYPE byte check
(unsigned(rx_byte_index_i ) /= (unsigned(cons_lgth_byte_i) + 5))) then -- LGTH byte check
nfip_status_r_tler_p_o <= '1';
else
nfip_status_r_tler_p_o <= '0';
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process VAR_RDY_Generation:
......@@ -168,7 +248,7 @@ begin
--! VAR2_RDY (for broadcast consumed vars): stays always deasserted.
--! Note: A correct consumed RP_DAT frame is signaled by the cons_frame_ok_p_i, whereas a correct
--! Note: A correct consumed RP_DAT frame is signaled by the s_cons_frame_ok_p, whereas a correct
--! ID_DAT frame along with the variable it contained is signaled by the var_i.
--! For consumed variables, var_i gets its value (var_1, var_2, var_rst) after the reception of a
--! correct ID_DAT frame and of a correct FSS of the corresponding RP_DAT frame and it retains it
......@@ -194,7 +274,7 @@ begin
-- -- -- -- -- -- -- -- -- -- --
if cons_frame_ok_p_d1 = '1' then -- only if the received RP_DAT frame is correct,
if s_cons_frame_ok_p = '1' then -- only if the received RP_DAT frame is correct,
-- the nanoFIP signals the user to retreive data
s_var1_received <= '1'; -- note:the signal s_var1_received remains asser-
-- ted after the end of the cons_frame_ok_p pulse
......@@ -208,7 +288,7 @@ begin
var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is 0
var1_rdy_o <= s_var1_received; -- VAR1_RDY retains its value
if slone_i = '0' and cons_frame_ok_p_d1 = '1' then
if slone_i = '0' and s_cons_frame_ok_p = '1' then
-- only in memory mode and if the received RP_DAT
s_var2_received <= '1'; -- frame is correct, the nanoFIP signals the user
-- to retreive data.
......@@ -231,27 +311,11 @@ begin
end process;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Cons_frame_ok_p_delay : a 1-uclk delay is needed for the signal
--! cons_frame_ok_p_i, so that it gets synchronized with the var_i (the end of the pulse takes
--! place at the same moment that var_i changes from one variable to another).
Cons_frame_ok_p_delay: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
cons_frame_ok_p_d1 <= '0';
else
cons_frame_ok_p_d1 <= cons_frame_ok_p_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
--!@ brief: Generation of the signals s_rst_nfip_and_fd : signals that the 1st byte of a consumed
--!@ brief: Generation of the signals rst_nfip_and_fd : signals that the 1st byte of a consumed
--! reset var contains the station address
--! and s_assert_rston : signals that the 2nd byte of a consumed
--! and assert_rston : signals that the 2nd byte of a consumed
--! reset var contains the station address
Cons_Reset_Signals: process (uclk_i)
......@@ -284,11 +348,11 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_nfip_and_fd_p_o <= '1' when s_rst_nfip_and_fd = '1' and cons_frame_ok_p_d1= '1'
rst_nfip_and_fd_p_o <= '1' when s_rst_nfip_and_fd = '1' and s_cons_frame_ok_p = '1'
else '0';
assert_rston_p_o <= '1' when s_assert_rston = '1' and cons_frame_ok_p_d1= '1'
assert_rston_p_o <= '1' when s_assert_rston = '1' and s_cons_frame_ok_p = '1'
else '0';
......
wf_consumption.vhd
View file @ ad26318d
......@@ -30,52 +30,41 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @brief The unit groups the main actions that regard data consumption.
--! It instantiates the units:
--!
--! o WF_rx_deglitcher : for the filtering of the "nanoFIP FIELDRIVE"
--! input fd_rxd
--! o WF_cons_bytes_processor : for the handling of received RP_DAT data bytes as they
--! arrive from the WF_fd_receiver (registration to the RAM
--! or outputting to the DAT_O).
--!
--! o WF_rx_deserializer : for the formation of bytes of data
--!
--! o WF_cons_bytes_processor : for the handling of the data as they arrive
--! (registration to the RAM or outputting to the DAT_O)
--! o WF_cons_outcome : for the validation of the consumed frame at the end of
--! its arrival (in terms of FSS, Ctrl, PDU_TYPE, Lgth,
--! CRC bytes & manch. encoding) and the generation of the
--! "nanoFIP User Interface,NON-WISHBONE" outputs VAR1_RDY
--! and VAR2_RDY (for var_1, var_2) or of the internal
--! signals for the nanoFIP and FIELDRIVE resets (var_rst).
--!
--! o WF_cons_frame_validator : for the validation of the consumed frame, at the end of
--! of its arrival (in terms of FSS, Ctrl, PDU_TYPE, Lgth,
--! CRC bytes & manch. encoding)
--!
--! o WF_cons_outcome : for the generation of the "nanoFIP User Interface, NON-
--! WISHBONE" outputs VAR1_RDY and VAR2_RDY (for var_1, var_2)
--! or of the internal signals for the nanoFIP and FIELDRIVE
--! resets (for a var_rst)
--!
--! _________________________________
--! | |
--! | WF_cons_outcome |
--! |_________________________________|
--! ^
--! _________________________________
--! | |
--! | WF_cons_frame_validator |
--! |_________________________________|
--! ^
--! _________________________________
--! ___________________________________________________________
--! | WF_consumption |
--! | |
--! | WF_cons_bytes_processor |
--! | _____________________________________________ |
--! | | | |
--! | | WF_cons_outcome | |
--! | | | |
--! | |_____________________________________________| |
--! | |
--! |_________________________________|
--! ^
--! _________________________________
--! | _____________________________________________ |
--! | | | |
--! | | WF_cons_bytes_processor | |
--! | | | |
--! | |_____________________________________________| |
--! |___________________________________________________________|
--! /\
--! ___________________________________________________________
--! | |
--! | WF_rx_deserializer |
--! | |
--! |_________________________________|
--! ^
--! _________________________________
--! | |
--! | WF_rx_deglitcher |
--! |_________________________________|
--!
--! _______________________________________________________________
--! 0__________________________FIELDBUS____________________________O
--! | WF_fd_receiver |
--! |___________________________________________________________|
--! /\
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--!
--!
--! Important Notice : The WF_rx_deserializer is "blindly" responsible for the formation
......@@ -100,9 +89,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_prod_bytes_retriever \n
--! WF_status_bytes_gen \n
--! WF_tx_serializer \n
--! WF_reset_unit \n
--! WF_fd_receiver \n
--! WF_engine_control \n
--
--
......@@ -148,7 +136,7 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit unit
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic;
-- used by: all the units
......@@ -175,11 +163,11 @@ entity WF_consumption is
-- Signals from the WF_engine_control unit
var_i : in t_var;
-- used by: WF_cons_bytes_processor, WF_cons_frame_validator and WF_cons_outcome
-- used by: WF_cons_bytes_processor and WF_cons_outcome
byte_index_i : in std_logic_vector (7 downto 0);
-- used by: WF_cons_bytes_processor for the reception coordination
-- used by: WF_cons_frame_validator for the validation of the Length byte
-- used by: WF_cons_outcome for the validation of the Length byte
-----------------------------------------------------------------------------------------------
......@@ -193,7 +181,7 @@ entity WF_consumption is
data_o : out std_logic_vector (15 downto 0);
-- Signals to the WF_produce
nfip_status_r_tler_o : out std_logic;
nfip_status_r_tler_p_o : out std_logic;
-- Signals to the WF_reset_unit
assert_rston_p_o : out std_logic;
......@@ -209,7 +197,6 @@ end entity WF_consumption;
--=================================================================================================
architecture struc of WF_consumption is
signal s_cons_frame_ok_p : std_logic;
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
......@@ -250,35 +237,13 @@ begin
---------------------------------------------------------------------------------------------------
-- Frame Validation --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_cons_frame_validator unit, responsible for the validation of a
--! received RP_DAT frame with respect to the correctness of the Control, PDU_TYPE and Length
--! bytes of the Manchester encoding.
Consumption_Frame_Validator: WF_cons_frame_validator
port map (
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
rx_fss_crc_fes_manch_ok_p_i => rx_fss_crc_fes_manch_ok_p_i,
rx_crc_or_manch_wrong_p_i => rx_crc_or_manch_wrong_p_i,
var_i => var_i,
rx_byte_index_i => byte_index_i,
--------------------------------------------------------
nfip_status_r_tler_o => nfip_status_r_tler_o,
cons_frame_ok_p_o => s_cons_frame_ok_p);
--------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Outcome --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_cons_outcome unit that is generating :
--! the "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY & VAR2_RDY (for a var_1/2)
--! or the nanoFIP internal signals rst_nFIP_and_FD_p and assert_RSTON_p (for a var_rst).
--! the "nanoFIP User Interface, NON_WISHBONE" output signal R_TLER,
--! the "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY & VAR2_RDY (for a var_1/2) or
--! the nanoFIP internal signals rst_nFIP_and_FD_p and assert_RSTON_p (for a var_rst).
Consumption_Outcome : WF_cons_outcome
port map (
......@@ -286,19 +251,25 @@ begin
slone_i => slone_i,
subs_i => subs_i,
nfip_rst_i => nfip_rst_i,
cons_frame_ok_p_i => s_cons_frame_ok_p,
rx_fss_crc_fes_manch_ok_p_i => rx_fss_crc_fes_manch_ok_p_i,
rx_crc_or_manch_wrong_p_i => rx_crc_or_manch_wrong_p_i,
var_i => var_i,
rx_byte_index_i => byte_index_i,
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_i => s_cons_var_rst_byte_2,
--------------------------------------------------------
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
nfip_status_r_tler_p_o => nfip_status_r_tler_p_o,
assert_rston_p_o => assert_rston_p_o,
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o);
--------------------------------------------------------
end architecture struc;
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_crc.vhd
View file @ ad26318d
......@@ -35,10 +35,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--
--
--! @date 08/2010
--! @date 23/02/2011
--
--
--! @version v0.03
--! @version v0.04
--
--
--! @details \n
......@@ -60,6 +60,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
--! variable v_q_check_mask replaced with a signal,
--! code cleaned-up+commented \n
--! -> 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list!
--! xor replaced with if(Syndrome_Verification); processes rewritten;
--! delay on data_bit_ready_p_i removed.
--
---------------------------------------------------------------------------------------------------
--
......@@ -73,7 +76,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
port (
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
......@@ -89,7 +92,7 @@ port (
-- OUTPUTS
-- Signal to the WF_rx_deserializer unit
crc_ok_p : out std_logic; --! signals a correct received CRC syndrome
crc_ok_p_o : out std_logic; --! signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH-1 downto 0)--!calculated CRC
......@@ -103,8 +106,8 @@ end entity WF_crc;
--=================================================================================================
architecture rtl of WF_crc is
signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -116,27 +119,22 @@ begin
--! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
--! are interconnected as a linear feedback shift register.
Gen_16_bit_Register_and_Interconnections:
for I in 0 to c_CRC_GENER_POLY'left generate
Generate_16_bit_Register_and_Interconnections:
iteration_0: if I = 0 generate
s_q_nx(I) <= ((data_bit_i) xor s_q(s_q'left));
end generate;
s_q_nx(0) <= data_bit_i xor s_q(s_q'left);
next_iterations: if I > 0 generate
G: for I in 1 to c_CRC_GENER_POLY'left generate
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
end generate;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process CRC_calculation: the process "moves" the shift register described
--! above, for the calculation of the CRC.
CRC_calculation: process (uclk_i)
begin
CRC_calculation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
......@@ -145,21 +143,19 @@ begin
else
if start_crc_p_i = '1' then
s_q <= (others => '1'); -- register initialization
s_q <= (others => '1');-- register initialization
-- (initially preset, according to the Annex)
elsif data_bit_ready_p_i = '1' then -- new data bit to be considered for the CRC calculation
elsif data_bit_ready_p_i = '1' then -- new bit to be considered for the CRC calculation
s_q <= s_q_nx; -- data propagation
end if;
s_crc_bit_ready_p <= data_bit_ready_p_i;
end if;
end if;
end process;
end if;
end process;
-- -- -- -- --
crc_o <= not s_q;
-- -- -- -- --
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
......@@ -167,26 +163,23 @@ crc_o <= not s_q;
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_CRC_VERIFIC_MASK. When the CRC calculated from the received data matches the
--! c_CRC_VERIFIC_MASK, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p gives a 1 uclk-wide pulse.
--! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, s_crc_bit_ready_p)
Syndrome_Verification: process (s_q, data_bit_ready_p_i)
begin
begin
if s_q = not c_CRC_VERIFIC_MASK then
s_q_check_mask <= s_q xor c_CRC_VERIFIC_MASK;------------
if (unsigned(not s_q_check_mask)) = 0 then
crc_ok_p <= s_crc_bit_ready_p;
crc_ok_p_o <= data_bit_ready_p_i;
else
crc_ok_p <= '0';
crc_ok_p_o <= '0';
end if;
end process;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_decr_counter.vhd
View file @ ad26318d
......@@ -90,7 +90,8 @@ end entity WF_decr_counter;
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
......
wf_engine_control.vhd
View file @ ad26318d
......@@ -73,8 +73,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_production \n
--! WF_consumption \n
--! WF_fd_transmitter \n
--! WF_fd_receiver \n
--
--
--! \n<b>Modified by:</b> \n
......@@ -95,7 +95,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3),
--! assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and
--! rx_byte_ready_p_o removed cleaning-up+commenting
--! 02/2011 v0.05 EG session timeout counter added; time counter 18 digits instead of 15
--! 02/2011 v0.05 EG Independant timeout counter added; time counter 18 digits instead of 15
--
---------------------------------------------------------------------------------------------------
--
......@@ -129,17 +129,15 @@ entity WF_engine_control is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_production
-- Signal from the WF_fd_transmitter unit
-- Signal from the WF_tx_serializer unit
tx_byte_request_p_i : in std_logic; --! used for the counting of the
--! # produced bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_consumption
-- Signals from the WF_fd_receiver unit
-- Signals from the WF_rx_deserializer unit
rx_byte_i : in std_logic_vector(7 downto 0);--!deserialized ID_DAT/ RP_DAT byte
rx_byte_ready_p_i : in std_logic;--! indication of a new byte on rx_byte_i
......@@ -157,15 +155,14 @@ entity WF_engine_control is
-- OUTPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production
-- Signal to the WF_tx_serializer unit
tx_byte_request_accept_p_o : out std_logic;--! answer to tx_byte_request_p_i
tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte
tx_start_p_o : out std_logic;--! launches the transmitters's FSM
-- Signal to the WF_prod_bytes_retriever
prod_data_length_o : out std_logic_vector (7 downto 0);--! # bytes of the Conrol & Data
-- Signal to the WF_production unit
prod_data_lgth_o : out std_logic_vector (7 downto 0);--! # bytes of the Conrol & Data
--!fields of a prod RP_DAT frame
......@@ -177,7 +174,6 @@ entity WF_engine_control is
--!or after 134 bytes of a RP_DAT, the state machine
--!of the WF_rx_deserializer returns to idle state
rst_tx_p_o : out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production & WF_consumption
......@@ -217,11 +213,11 @@ architecture rtl of WF_engine_control is
signal s_load_time_counter, s_time_c_is_zero, s_session_timedout : std_logic;
signal s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_byte_p, s_tx_last_byte_p_d : std_logic;
signal s_prod_data_length_match, s_tx_start_prod_p, s_broadcast_var : std_logic;
signal s_prod_data_lgth_match, s_tx_start_prod_p, s_broadcast_var : std_logic;
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
signal s_time_counter_top, s_turnaround_time, s_silence_time : unsigned (17 downto 0);
signal s_tx_byte_index, s_rx_byte_index, s_prod_data_length : std_logic_vector (7 downto 0);
signal s_produce_or_consume : std_logic_vector (1 downto 0);
signal s_tx_byte_index, s_rx_byte_index, s_prod_data_lgth : std_logic_vector (7 downto 0);
signal s_prod_or_cons : std_logic_vector (1 downto 0);
......@@ -273,7 +269,7 @@ begin
--!@brief Combinatorial process Engine_Control_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero, s_produce_or_consume,subs_i,
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero, s_prod_or_cons,subs_i,
rx_crc_or_manch_wrong_p_i, s_session_timedout,
rx_fss_crc_fes_manch_ok_p_i, s_broadcast_var,
s_var_identified,rx_byte_ready_p_i,rx_byte_i,
......@@ -289,7 +285,7 @@ begin
when idle =>
if (rx_fss_received_p_i = '1') then -- correct FSS arrived
nx_control_st <= id_dat_control_byte;-- session timeout counter starts counting
nx_control_st <= id_dat_control_byte;
else
nx_control_st <= idle;
......@@ -357,10 +353,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_frame_ok =>
if (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_produce_or_consume = "10") then
if (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_prod_or_cons = "10") then
nx_control_st <= produce_wait_turnar_time; -- CRC & FES check ok! station has to produce
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_produce_or_consume = "01") then
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_prod_or_cons = "01") then
nx_control_st <= consume_wait_FSS; -- CRC & FES check ok! station has to consume
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_rx_bytes_c > 2) then
......@@ -622,9 +618,8 @@ begin
p3_lgth_i => p3_lgth_i,
var_i => s_var,
-------------------------------------------------------
prod_data_length_o => s_prod_data_length
prod_data_lgth_o => s_prod_data_lgth);
-------------------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the number of the bytes that are
......@@ -639,13 +634,12 @@ begin
incr_counter_i => s_inc_prod_bytes_counter,
-------------------------------------------------------
counter_o => s_prod_bytes_c,
counter_is_full_o => open
counter_is_full_o => open );
-------------------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- --
-- when s_prod_data_length bytes have been counted,the signal s_prod_data_length_match is activated
s_prod_data_length_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_length) else '0';
-- when s_prod_data_lgth bytes have been counted,the signal s_prod_data_lgth_match is activated
s_prod_data_lgth_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_lgth) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -668,9 +662,8 @@ begin
incr_counter_i => s_inc_rx_bytes_counter,
-------------------------------------------------------
counter_o => s_rx_bytes_c,
counter_is_full_o => open
counter_is_full_o => open);
-------------------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Combinatorial process Arguments_For_Both_Bytes_Counters: The process gives values to
......@@ -726,18 +719,14 @@ begin
---------------------------------------------------------------------------------------------------
-- General Timeout Counter --
-- Independant Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_decr_counter for the counting of turnaround and silence times.
--! The same counter is used in both cases. The signal s_time_counter_top initializes the counter
--! to either the turnaround or the silence time. If after the correct arrival of an ID_DAT frame
--! the identified variable is a produced one the counter loads to the turnaround time, whereas if
--! it had been a consumed variable it loads to the silence. The counting takes place during the
--! states "produce_wait_turnar_time" and "consume_wait_FSS" respectively.
--! @brief Instantiation of a WF_decr_counter relying only on the system clock as an additional
--! way to go back to Idle state, in case any other logic is being stuck.
General_Timeout_Counter: WF_decr_counter
Session_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
uclk_i => uclk_i,
......@@ -790,18 +779,18 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Combinatorial process Turnaround_and_Silence_Time_Counter_Arg: The process gives values
--! to the counter_top and counter_load_i inputs of the Turnaround_and_Silence_Time_Counter,
--! according to the state of the FSM and the type of received variable (s_produce_or_consume).
--! according to the state of the FSM and the type of received variable (s_prod_or_cons).
Turnaround_and_Silence_Time_Counter_Arg: process (s_prod_wait_turnar_time, s_turnaround_time,
s_id_dat_frame_ok, s_produce_or_consume,
s_id_dat_frame_ok, s_prod_or_cons,
s_cons_wait_FSS, s_silence_time)
begin
if s_id_dat_frame_ok = '1' and s_produce_or_consume = "10" then
if s_id_dat_frame_ok = '1' and s_prod_or_cons = "10" then
s_load_time_counter <= '1'; -- counter loads
s_time_counter_top <= s_turnaround_time;
elsif s_id_dat_frame_ok = '1' and s_produce_or_consume = "01" then
elsif s_id_dat_frame_ok = '1' and s_prod_or_cons = "01" then
s_load_time_counter <= '1'; -- counter loads
s_time_counter_top <= s_silence_time;
......@@ -843,16 +832,15 @@ begin
if nfip_rst_i = '1' then
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_produce_or_consume <= "00";
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
else
-------------------------------------------------------------------------------------------
if (s_idle_state = '1') or (s_id_dat_ctrl_byte = '1') then -- new frame initializations
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_produce_or_consume <= "00";
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
......@@ -862,43 +850,43 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue then
s_var_aux <= var_presence;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).prod_or_cons;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue then
s_var_aux <= var_identif;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue then
s_var_aux <= var_1;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue then
s_var_aux <= var_2;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue then
s_var_aux <= var_3;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue then
s_var_aux <= var_rst;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
else
s_var_aux <= var_whatever;
s_produce_or_consume <= "00";
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
end if;
......@@ -956,7 +944,7 @@ begin
s_tx_byte_request_accept_p <= s_producing and (tx_byte_request_p_i or s_tx_start_prod_p);
s_tx_last_byte_p <= s_producing and s_prod_data_length_match and tx_byte_request_p_i;
s_tx_last_byte_p <= s_producing and s_prod_data_lgth_match and tx_byte_request_p_i;
......@@ -967,7 +955,7 @@ begin
var_o <= s_var;
-- number of bytes of the Control & Data fields of a produced RP_DAT frame
prod_data_length_o <= s_prod_data_length;
prod_data_lgth_o <= s_prod_data_lgth;
-- response to WF_tx_serializer request for a byte
tx_byte_request_accept_p_o <= s_tx_byte_request_accept_p_d2;
......@@ -978,12 +966,11 @@ begin
-- If the WF_rx_deserializer continues receiving bytes when the engine_control is idle, it has to
-- be reset. This happens when the number of bytes that have arrived exceed the expected (ID_DAT >8
-- bytes and consumed RP_DAT > 130 bytes)
rx_rst_p_o <= (s_idle_state and rx_byte_ready_p_i) or s_session_timedout;
rx_rst_p_o <= s_idle_state and rx_byte_ready_p_i;
-- Production starts after the expiration of the turnaround time
tx_start_p_o <= s_tx_start_prod_p;
rst_tx_p_o <= s_session_timedout;
---------------------------------------------------------------------------------------------------
......
wf_fd_receiver.vhd
View file @ ad26318d
......@@ -59,11 +59,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! | |_______________________________________| |
--! | |
--! |___________________________________________________________|
--! /\
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--!
--!
--! \/
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......
wf_fd_transmitter.vhd
View file @ ad26318d
......@@ -59,8 +59,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! | |_________________________________________________| |
--! |___________________________________________________________|
--! \/
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--!
--!
--!
......@@ -98,11 +98,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -129,7 +124,6 @@ entity WF_fd_transmitter is
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
tx_start_p_i : in std_logic; --! indication for the start of the production
tx_rst_p_i : in std_logic; --! transmitter timeout
-- OUTPUTS
......@@ -151,6 +145,7 @@ end entity WF_fd_transmitter;
architecture struc of WF_fd_transmitter is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
--=================================================================================================
......@@ -170,7 +165,7 @@ begin
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
tx_rst_p_i => tx_rst_p_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
-----------------------------------------------
tx_clk_o => tx_clk_o,
tx_clk_p_buff_o => s_tx_clk_p_buff);
......@@ -188,15 +183,15 @@ begin
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
tx_rst_p_i => tx_rst_p_i,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => tx_byte_request_accept_p_i,
byte_i => tx_byte_i,
last_byte_p_i => tx_last_byte_p_i,
tx_clk_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
tx_data_o => tx_data_o,
byte_request_p_o => tx_byte_request_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o );
-----------------------------------------------
......
wf_incr_counter.vhd
View file @ ad26318d
......@@ -90,6 +90,7 @@ architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......
wf_inputs_synchronizer.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_inputs_synchronizer.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_inputs_synchronizer --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit synchronizes the nanoFIP's input signals to the uclk or the wb_clk;
--! a set of 3 registers is used for each signal.
--! Notes : Regarding the WISHBONE interface, only the control signals STB, CYC, WE are
--! synchronized.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 09/12/2010
--
--
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 10/2010 v0.01 EG First version
--! 12/2010 v0.02 EG fd_rxcdn added;
--! in nanoFIP input fd_rxd we also see the nanoFIP output fd_txd; in order to
--! get only the receiver's data, we filter fd_rxd with the reception activity
--! detection fd_rxcdn.
--! 1/2011 v0.021 EG wb_rst_a_i renamed to wb_rst_i
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_inputs_synchronizer
--=================================================================================================
entity WF_inputs_synchronizer is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, NON WISHBONE
dat_a_i : in std_logic_vector(15 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
-- nanoFIP FIELDRIVE
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
-- OUTPUTS
-- nanoFIP User Interface, General signals
rstin_o : out std_logic;
-- nanoFIP User Interface, NON WISHBONE
slone_dati_o : out std_logic_vector(15 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
-- nanoFIP FIELDRIVE
fd_rxd_o : out std_logic;
fd_rxd_edge_p_o : out std_logic;
fd_rxd_f_edge_p_o : out std_logic;
fd_rxd_r_edge_p_o : out std_logic;
fd_txer_o : out std_logic;
fd_wdgn_o : out std_logic
);
end entity WF_inputs_synchronizer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_inputs_synchronizer is
signal s_wb_we_d3, s_wb_cyc_d1, s_wb_cyc_d2, s_wb_cyc_d3, s_fd_rxd_f_edge : std_logic;
signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1, s_fd_rxd_r_edge : std_logic;
signal s_var1_access_d2, s_var2_access_d2, s_var3_access_d2 : std_logic;
signal s_var1_access_d3, s_var2_access_d3, s_var3_access_d3 : std_logic;
signal s_wb_stb_d1, s_wb_stb_d2, s_wb_stb_d3, s_wb_stb_d4, s_wb_we_d1, s_wb_we_d2 : std_logic;
signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3, s_fd_rxcdn_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_u_rst_d3 : std_logic_vector(2 downto 0);
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
signal s_slone_dati_d1, s_slone_dati_d3, s_slone_dati_d2 :std_logic_vector(15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var1_access_d1 <= '0';
s_var1_access_d2 <= '0';
s_var1_access_d3 <= '0';
s_var2_access_d1 <= '0';
s_var2_access_d2 <= '0';
s_var1_access_d3 <= '0';
s_var3_access_d1 <= '0';
s_var3_access_d2 <= '0';
s_var1_access_d3 <= '0';
else
s_var1_access_d1 <= var1_access_a_i;
s_var1_access_d2 <= s_var1_access_d1;
s_var1_access_d3 <= s_var1_access_d2;
s_var2_access_d1 <= var2_access_a_i;
s_var2_access_d2 <= s_var2_access_d1;
s_var2_access_d3 <= s_var2_access_d2;
s_var3_access_d1 <= var3_access_a_i;
s_var3_access_d2 <= s_var3_access_d1;
s_var3_access_d3 <= s_var3_access_d2;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
var1_access_o <= s_var1_access_d3;
var2_access_o <= s_var2_access_d3;
var3_access_o <= s_var3_access_d3;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_manch_code_viol_check.vhd
View file @ ad26318d
......@@ -63,7 +63,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--
......@@ -117,6 +117,7 @@ architecture rtl of WF_rx_manch_code_check is
signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_signal_d : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......
wf_model_constr_decoder.vhd
View file @ ad26318d
......@@ -49,8 +49,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -107,14 +107,11 @@ entity WF_model_constr_decoder is
end entity WF_model_constr_decoder;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_model_constr_decoder is
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
......
wf_package.vhd
View file @ ad26318d
......@@ -158,7 +158,7 @@ package WF_package is
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LENGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_LGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
......@@ -174,15 +174,14 @@ package WF_package is
-- Construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(0 to 7) :=
constant c_P3_LGTH_TABLE : t_unsigned_array(7 downto 0) :=
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000010" -- reserved
);
others => "00000010"); -- reserved
......@@ -192,21 +191,21 @@ package WF_package is
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LENGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
constant c_PERIODS_COUNTER_LGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LENGTH);
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LENGTH);
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LENGTH);
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
type t_uclk_ticks is array (Natural range <>) of unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks (3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
......@@ -214,10 +213,8 @@ package WF_package is
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
constant c_2_PERIODS_COUNTER_LENGTH : natural := 12;-- length of a counter counting 4 reception/
-- transmission period
constant c_2_PERIODS_COUNTER_LGTH : natural := 12; -- length of a counter counting 2 reception/
-- transmission periods
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the turnaround and silence times --
......@@ -271,7 +268,7 @@ package WF_package is
prod_or_cons : std_logic_vector (1 downto 0);
broadcast : std_logic;
base_addr : unsigned (8 downto 0);
array_length : unsigned (7 downto 0);
array_lgth : unsigned (7 downto 0);
byte_array : t_byte_array (0 to 15);
end record;
......@@ -292,7 +289,7 @@ package WF_package is
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_length => "00000111", -- 8 bytes in total including the Control byte
array_lgth => "00000111", -- 8 bytes in total including the Control byte
-- (counting starts from 0;-))
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
3 => x"80", 4 => x"03" , 5 => x"00", 6 => x"f0",
......@@ -304,7 +301,7 @@ package WF_package is
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_length => "00001010", -- 11 bytes in total including the Control byte
array_lgth => "00001010", -- 11 bytes in total including the Control byte
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00" , 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00" , 9 => x"00", 10 => x"00",
......@@ -316,7 +313,7 @@ package WF_package is
prod_or_cons => "10",
broadcast => '0',
base_addr => "100000000",
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -327,7 +324,7 @@ package WF_package is
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -338,7 +335,7 @@ package WF_package is
prod_or_cons => "01",
broadcast => '1',
base_addr => "010000000",
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -348,7 +345,7 @@ package WF_package is
prod_or_cons => "01",
broadcast => '1',
base_addr => "---------",
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")));
......@@ -392,13 +389,13 @@ package WF_package is
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_rst_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
-----------------------------------------------------------------
byte_request_p_o : out std_logic;
tx_osc_rst_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic);
-----------------------------------------------------------------
......@@ -430,20 +427,6 @@ package WF_package is
---------------------------------------------------------------------------------------------------
component WF_cons_bytes_to_dato is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
transfer_byte_p_i : in std_logic_vector (1 downto 0);
byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
slone_data_o : out std_logic_vector (15 downto 0));
-----------------------------------------------------------------
end component WF_cons_bytes_to_dato;
---------------------------------------------------------------------------------------------------
component WF_consumption is
port (
......@@ -463,7 +446,7 @@ package WF_package is
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
data_o : out std_logic_vector (15 downto 0);
nfip_status_r_tler_o : out std_logic;
nfip_status_r_tler_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic);
-----------------------------------------------------------------
......@@ -526,13 +509,13 @@ end component WF_rx_osc;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
data_length_i : in std_logic_vector (7 downto 0);
data_lgth_i : in std_logic_vector (7 downto 0);
byte_request_accept_p_i : in std_logic;
var_i : in t_var;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
constr_id_dec_i : in std_logic_vector (7 downto 0);
model_id_dec_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
......@@ -557,7 +540,6 @@ end component WF_rx_osc;
tx_byte_request_accept_p_i : in std_logic;
tx_last_byte_p_i : in std_logic;
tx_start_p_i : in std_logic;
tx_rst_p_i : in std_logic;
-----------------------------------------------------------------
tx_byte_request_p_o : out std_logic;
tx_data_o : out std_logic;
......@@ -574,7 +556,7 @@ end component WF_rx_osc;
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_rst_p_i : in std_logic;
tx_osc_rst_p_i : in std_logic;
-----------------------------------------------------------------
tx_clk_o : out std_logic;
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0));
......@@ -600,7 +582,7 @@ end component WF_rx_osc;
nFIP_status_byte_i : in std_logic_vector (7 downto 0);
mps_status_byte_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
data_lgth_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
byte_being_sent_p_i : in std_logic;
var3_rdy_i : in std_logic;
......@@ -612,21 +594,6 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_prod_bytes_from_dati is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
slone_byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_prod_bytes_from_dati;
---------------------------------------------------------------------------------------------------
component WF_engine_control
port (
......@@ -648,9 +615,8 @@ end component WF_rx_osc;
tx_last_byte_p_o : out std_logic;
tx_start_p_o : out std_logic;
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_data_length_o : out std_logic_vector (7 downto 0);
prod_data_lgth_o : out std_logic_vector (7 downto 0);
rx_rst_p_o : out std_logic;
rst_tx_p_o : out std_logic;
var_o : out t_var);
-----------------------------------------------------------------
end component WF_engine_control;
......@@ -726,7 +692,7 @@ end component WF_rx_osc;
data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic;
-----------------------------------------------------------------
crc_ok_p : out std_logic;
crc_ok_p_o : out std_logic;
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0));
-----------------------------------------------------------------
end component WF_crc;
......@@ -735,11 +701,11 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_manch_encoder is
generic (g_word_length : natural);
generic (g_word_lgth : natural);
port (
word_i : in std_logic_vector (g_word_length-1 downto 0);
word_i : in std_logic_vector (g_word_lgth-1 downto 0);
-----------------------------------------------------------------
word_manch_o : out std_logic_vector ((2*g_word_length)-1 downto 0));
word_manch_o : out std_logic_vector ((2*g_word_lgth)-1 downto 0));
-----------------------------------------------------------------
end component WF_manch_encoder;
......@@ -789,7 +755,7 @@ end component WF_rx_osc;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
rst_status_bytes_p_i : in std_logic;
-----------------------------------------------------------------
......@@ -930,44 +896,32 @@ end component WF_rx_osc;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
-----------------------------------------------------------------
prod_data_length_o : out std_logic_vector (7 downto 0));
prod_data_lgth_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_prod_data_lgth_calc;
---------------------------------------------------------------------------------------------------
component WF_cons_frame_validator is
port (
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
var_i : in t_var;
rx_byte_index_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
cons_frame_ok_p_o : out std_logic;
nfip_status_r_tler_o : out std_logic);
-----------------------------------------------------------------
end component WF_cons_frame_validator;
---------------------------------------------------------------------------------------------------
component WF_cons_outcome is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nfip_rst_i : in std_logic;
cons_frame_ok_p_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
var_i : in t_var;
rx_byte_index_i : in std_logic_vector (7 downto 0);
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
nfip_status_r_tler_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic);
-----------------------------------------------------------------
......@@ -1016,7 +970,6 @@ end WF_package;
--=================================================================================================
--! package body
--=================================================================================================
package body WF_package is
......
wf_prod_bytes_retriever.vhd
View file @ ad26318d
......@@ -79,8 +79,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_wb_controller \n
--! WF_engine_control \n
--! WF_prod_permit \n
--! WF_status_bytes_gen \n
......@@ -103,6 +104,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 4/1/2011 v0.05 EG unit renamed from WF_prod_bytes_to_tx to WF_prod_bytes_retriever;
--! input byte_being_sent_p_i added, so that the reseting of status bytes
--! does not pass from the engine; clening-up+commenting
--! -> 2/2011 v0.051 EG WF_prod_bytes_from_dati unit removed.
--
--
---------------------------------------------------------------------------------------------------
......@@ -112,13 +114,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 1, 3, 4 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the produced variables presence, identification and var_3. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -155,7 +150,7 @@ entity WF_prod_bytes_retriever is
byte_being_sent_p_i : in std_logic; --! pulse on the beginning of the
--! delivery of a new byte
data_length_i : in std_logic_vector (7 downto 0); --! # bytes of the Conrol&Data fields
data_lgth_i : in std_logic_vector (7 downto 0); --! # bytes of the Conrol&Data fields
-- of the RP_DAT frame; includes:
-- 1 byte RP_DAT.Control,
-- 1 byte RP_DAT.Data.PDU_type,
......@@ -203,6 +198,7 @@ architecture rtl of WF_prod_bytes_retriever is
signal s_lgth_byte, s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0);
signal s_byte_index_d : std_logic_vector (7 downto 0);
signal s_mem_addr_A : std_logic_vector (8 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
--=================================================================================================
......@@ -215,7 +211,9 @@ begin
-- Produced RAM --
-- Storage (by the user) & retreival (by the unit) of produced bytes --
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a Produced Dual Port RAM
--!@brief Instantiation of a Produced Dual Port RAM.
--! Port A is used by the nanoFIP for the readings from the Produced RSM;
--! Port B is connected to the WISHBONE interface for the writings from the user.
Produced_Bytes_From_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map (
......@@ -223,42 +221,48 @@ begin
g_ram_addr_lgth => 9) -- 2^9: depth of produced ram
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
-- port A corresponds to: nanoFIP that reads from the Produced ram & B to: WISHBONE that writes
port map (
clk_porta_i => uclk_i, -- 40 MHz clock
addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory
------------------------------------------------------------------------------------
data_porta_o => s_mem_byte, -- output byte read
------------------------------------------------------------------------------------
clk_portb_i => wb_clk_i, -- WISHBONE clock
addr_portb_i => wb_adr_i (8 downto 0),-- address of byte to be written
addr_portb_i => wb_adr_i, -- address of byte to be written
data_portb_i => wb_data_i, -- byte to be written
write_en_portb_i => wb_ack_prod_p_i); -- WISHBONE write enable
write_en_portb_i => wb_ack_prod_p_i, -- WISHBONE write enable
-----------------------------------------
data_porta_o => s_mem_byte); -- output byte read
-----------------------------------------
---------------------------------------------------------------------------------------------------
-- Produced bytes from DAT_I --
-- DAT_I bus Sampling --
-- Retreival of bytes to be produced --
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the unit that in stand-alone mode is responsible for the sampling of the
--! input data bus DAT_I(15:0). The sampling takes place on the 1st clock cycle after the VAR3_RDY
--! has been de-asserted.
--!@brief Sampling of the input data bus DAT_I(15:0) for the operation in stand-alone mode.
--! The sampling takes place on the 1st clock cycle after the VAR3_RDY has been de-asserted.
Produced_Bytes_From_DATI: WF_prod_bytes_from_dati
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_data_i => slone_data_i,
var3_rdy_i => var3_rdy_i,
byte_index_i => byte_index_i,
------------------------------
slone_byte_o => s_slone_byte);
------------------------------
Sample_DAT_I_bus: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_sampled_data <= (others=>'0');
else
if var3_rdy_i = '1' then -- data latching
s_sampled_data <= slone_data_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_slone_byte <= s_sampled_data(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX
else s_sampled_data(15 downto 8);
---------------------------------------------------------------------------------------------------
-- Bytes Retreival --
-- Bytes Generation --
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Bytes_Generation: Generation of bytes for the Control and Data
--! fields of an RP_DAT frame:\n If the variable requested in the ID_DAT is of "produced" type
......@@ -269,7 +273,7 @@ begin
--! WF_status_bytes_gen or the WF_model_constr_decoder units.\n The output byte "byte_o" is sent to
--! the WF_tx_serializer unit for manchester encoding and serialization.
Bytes_Generation: process (var_i, s_byte_index_d, data_length_i, constr_id_dec_i, model_id_dec_i,
Bytes_Generation: process (var_i, s_byte_index_d, data_lgth_i, constr_id_dec_i, model_id_dec_i,
nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_byte_index_d_aux,
s_mem_byte, nostat_i, byte_being_sent_p_i, s_lgth_byte, slone_i)
......@@ -332,14 +336,14 @@ begin
-- The first (Control) and second (PDU_TYPE) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less or eq
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux);
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The c_LENGTH_BYTE_INDEX byte is the Length
-- The c_LGTH_BYTE_INDEX byte is the Length
elsif s_byte_index_d = c_LENGTH_BYTE_INDEX then
elsif s_byte_index_d = c_LGTH_BYTE_INDEX then
byte_o <= s_lgth_byte;
rst_status_bytes_p_o <= '0';
......@@ -347,13 +351,13 @@ begin
-- The one but last byte if the input nostat_i is negated is the nanoFIP status byte
-- (if nostat_i is not negated, the "else" condition takes place)
elsif (unsigned(s_byte_index_d) = (unsigned(data_length_i)-1 )) and nostat_i = '0' then
elsif (unsigned(s_byte_index_d) = (unsigned(data_lgth_i)-1 )) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i;
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The last byte is the MPS status
elsif s_byte_index_d = (data_length_i) then
elsif s_byte_index_d = (data_lgth_i) then
byte_o <= mps_status_byte_i;
rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes.
-- The reset arrives after having sent
......@@ -377,14 +381,14 @@ begin
-- The first (Control) and second (PDU type) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less or eq
if unsigned(s_byte_index_d) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux);
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The c_LENGTH_BYTE_INDEX byte is the Length
-- The c_LGTH_BYTE_INDEX byte is the Length
elsif s_byte_index_d = c_LENGTH_BYTE_INDEX then
elsif s_byte_index_d = c_LGTH_BYTE_INDEX then
byte_o <= s_lgth_byte;
rst_status_bytes_p_o <= '0';
......@@ -392,13 +396,13 @@ begin
-- The one but last byte if the input nostat_i is negated is the nanoFIP status byte
-- (if nostat_i is not negated, the "else" condition takes place)
elsif unsigned(s_byte_index_d) = (unsigned(data_length_i)-1 ) and nostat_i = '0' then
elsif unsigned(s_byte_index_d) = (unsigned(data_lgth_i)-1 ) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i;
rst_status_bytes_p_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The last byte is the MPS status
elsif s_byte_index_d = data_length_i then
elsif s_byte_index_d = data_lgth_i then
byte_o <= mps_status_byte_i;
rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes.
-- The reset arrives after having sent the
......@@ -474,7 +478,7 @@ begin
-- c_VARS_ARRAY.byte_array, with a predefined
-- width of 15 bytes
s_lgth_byte <= std_logic_vector (resize((unsigned(data_length_i)-2),byte_o'length));
s_lgth_byte <= std_logic_vector (resize((unsigned(data_lgth_i)-2),byte_o'length));
-- represents the RP_DAT.Data.LENGTH byte
-- it includes the # bytes of user-data
-- (P3_LGTH) plus 1 byte of MPS_status
......
wf_prod_bytes_to_dati.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_prod_bytes_from_dati.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_bytes_from_dati --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Unit responsible for the sampling of the DAT_I bus in stand-alone operation.
--! Following to the functional specs page 15, in stand-alone mode, the nanoFIP
--! samples the data on the first clock cycle after the de-assertion of VAR3_RDY.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 04/01/2011
--
--
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_prod_permit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 4/1/2011 v0.02 EG unit renamed from WF_slone_prod_dati_bytes_sampler to
--! WF_prod_bytes_from_dati; cleaning-up + commenting
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_prod_bytes_from_dati
--=================================================================================================
entity WF_prod_bytes_from_dati is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector (7 downto 0); --! index of the byte to be produced
-- Signals from the WF_prod_permit unit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- OUTPUTS
-- Signal to the WF_prod_bytes_retriever
slone_byte_o : out std_logic_vector (7 downto 0) --! sampled byte to be sent
);
end entity WF_prod_bytes_from_dati;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_bytes_from_dati is
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Sample_DAT_I_bus: the sampling of the DAT_I bus in stand-alone mode
--! has to take place on the first clock cycle after the de-assertion of VAR3_RDY.
--! Note: Since slone_data_i is the triply registered version of the bus DAT_I (for synchronization),
--! the signal VAR3_RDY has to be (internally) delayed for 3 uclk cycles too, before the sampling;
--! the 4th delay is added in order to have the sampling 1 uclk AFTER the de-assertion.
Sample_DAT_I_bus: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0');
else
s_var3_rdy_d4 <= s_var3_rdy_d4(2 downto 0) & var3_rdy_i;
if s_var3_rdy_d4(3) = '1' then -- data latching
s_sampled_data <= slone_data_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
slone_byte_o <= s_sampled_data(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX
else s_sampled_data(15 downto 8);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_prod_data_lgth_calc.vhd
View file @ ad26318d
......@@ -63,7 +63,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_engine_control \n
--
--
......@@ -107,7 +107,7 @@ entity WF_prod_data_lgth_calc is
-- OUTPUT
-- Signal to the WF_engine_control and WF_production units
prod_data_length_o : out std_logic_vector (7 downto 0)
prod_data_lgth_o : out std_logic_vector (7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......@@ -116,9 +116,10 @@ end entity WF_prod_data_lgth_calc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_data_lgth_calc is
architecture behavior of WF_prod_data_lgth_calc is
signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0);
signal s_prod_data_length, s_p3_length_decoded : unsigned (7 downto 0);
--=================================================================================================
-- architecture begin
......@@ -131,10 +132,10 @@ begin
--! of the presence and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the calculation.
data_length_calcul: process (var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i)
data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i)
begin
s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
s_p3_lgth_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
case var_i is
......@@ -142,13 +143,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......@@ -162,7 +163,7 @@ begin
-- 1 byte MPS status
-- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_length_decoded" indicates the amount of user-data
-- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data
-- to these, there should be added 1 byte Control
-- 1 byte PDU_TYPE
-- 1 byte Length
......@@ -172,39 +173,40 @@ begin
if slone_i = '1' then
if nostat_i = '1' then -- 6 bytes (counting starts from 0)
s_prod_data_length <= to_unsigned(5, s_prod_data_length'length);
s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length);
else -- 7 bytes
s_prod_data_length <= to_unsigned(6, s_prod_data_length'length);
s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length);
end if;
else
if nostat_i = '0' then
s_prod_data_length <= s_p3_length_decoded + 4;
s_prod_data_lgth <= s_p3_lgth_decoded + 4;
else
s_prod_data_length <= s_p3_length_decoded + 3;
s_prod_data_lgth <= s_p3_lgth_decoded + 3;
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_1 | var_2 | var_rst =>
s_prod_data_length <= (others => '0');
s_prod_data_lgth <= (others => '0');
when others =>
s_prod_data_length <= (others => '0');
s_prod_data_lgth <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output
prod_data_length_o <= std_logic_vector (s_prod_data_length);
prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth);
end architecture rtl;
end architecture behavior;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_prod_permit.vhd
View file @ ad26318d
......@@ -62,13 +62,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the variables var_1, var_2, var_3 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......
wf_production.vhd
View file @ ad26318d
......@@ -67,8 +67,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! | WF_fd_transmitter |
--! |___________________________________________________________|
--! \/
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--!
--! Note: In the entity declaration of this unit, below each input signal, we mark
--! which of the instantiated units needs it.
......@@ -91,6 +91,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_engine_control \n
--! WF_wb_controller \n
--! WF_fd_transmitter \n
--! WF_model_constr_decoder \n
--
......@@ -109,11 +110,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -185,7 +181,7 @@ entity WF_production is
-- Signals from the WF_engine_control
byte_index_i : in std_logic_vector (7 downto 0);
data_length_i : in std_logic_vector (7 downto 0);
data_lgth_i : in std_logic_vector (7 downto 0);
byte_request_accept_p_i : in std_logic;
var_i : in t_var;-- also for the WF_prod_permit for the VAR3_RDY generation
-- used by: WF_prod_bytes_retriever for the definition of the bytes to be delivered
......@@ -197,7 +193,7 @@ entity WF_production is
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
-- used by: WF_status_bytes_gen for the generation of the nanoFIP status byte, bits 2, 4, 5
......@@ -280,7 +276,7 @@ begin
var_i => var_i,
byte_index_i => byte_index_i,
byte_being_sent_p_i => byte_request_accept_p_i,
data_length_i => data_length_i,
data_lgth_i => data_lgth_i,
wb_data_i => wb_data_i,
slone_data_i => slone_data_i,
var3_rdy_i => s_var3_rdy,
......@@ -311,7 +307,7 @@ begin
var1_acc_a_i => var1_acc_a_i,
var2_acc_a_i => var2_acc_a_i,
var3_acc_a_i => var3_acc_a_i,
nfip_status_r_tler_i => nfip_status_r_tler_i,
nfip_status_r_tler_p_i => nfip_status_r_tler_p_i,
rst_status_bytes_p_i => s_rst_status_bytes_p,
-----------------------------------------------
u_cacer_o => u_cacer_o,
......
wf_reset_unit.vhd
View file @ ad26318d
......@@ -218,8 +218,8 @@ architecture rtl of WF_reset_unit is
signal s_counter_is_ten, s_counter_is_full, s_counter_full : std_logic;
signal s_var_rst_counter_is_eight, s_var_rst_counter_is_two : std_logic;
signal s_var_rst_reinit_counter, s_var_rst_counter_is_full, s_var_rst_counter_full : std_logic;
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_c, s_var_rst_c, s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_c, s_var_rst_c, s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
type rstin_st_t is (idle, rstin_eval, intern_rst_ON_FD_rst_ON,intern_rst_OFF_FD_rst_ON);
type after_a_var_rst_t is (after_a_var_rst_idle, after_a_var_rst_rston_ON,
......@@ -447,13 +447,15 @@ begin
--!@brief Instantiation of a WF_incr_counter: the counter counts from 0 to 4 FD_TXCK.
RSTIN_free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
incr_counter_i => '1',
counter_o => s_c,
counter_is_full_o => open);
counter_is_full_o => open,
----------------------------------------
counter_o => s_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_counter_is_four <= '1' when s_c = to_unsigned(4, s_c'length) else '0';
......@@ -468,12 +470,12 @@ RSTIN_free_counter: WF_incr_counter
--!@brief Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
--! to store the current state, a combinatorial process to manage state transitions and finally a
--! combinatorial process to manage the output signals), which are the three processes that follow.
--! If after the reception or a var_rst the signal assert_RSTON_p_i is asserted, the FSM
--! If after the reception of a var_rst the signal assert_RSTON_p_i is asserted, the FSM
--! asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
--! If after the reception or a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
--! If after the reception of a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
--! asserts the nanoFIP internal reset (s_intern_rst_from_var_rst) for 2 uclk cycles and the
--! "nanoFIP FIELDRIVE" output (s_FD_rst_from_var_rst) for 4 FD_TXCK cycles.
--! If after the reception or a var_rst both assert_RSTON_p_i and rst_nFIP_and_FD_p_i
--! If after the reception of a var_rst both assert_RSTON_p_i and rst_nFIP_and_FD_p_i
--! are asserted, the FSM asserts the s_intern_rst_from_var_rst for 2 uclk cycles, the RSTON for 8
--! uclk cycles and the s_FD_rst_from_var_rst for 4 FD_TXCK cycles.
--! The same counter is used for all the countings!
......@@ -666,13 +668,15 @@ RSTIN_free_counter: WF_incr_counter
--! from 0 to 4 * FD_TXCK, if rst_nFIP_and_FD_p has been activated.
free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_var_rst_reinit_counter,
incr_counter_i => '1',
counter_o => s_var_rst_c,
counter_is_full_o => open);
counter_is_full_o => open,
----------------------------------------
counter_o => s_var_rst_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_counter_is_eight <= '1' when s_var_rst_c= to_unsigned(8, s_var_rst_c'length) else '0';
......
wf_rx_deglitcher.vhd
View file @ ad26318d
......@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
......@@ -101,7 +101,9 @@ end WF_rx_deglitcher;
architecture Behavioral of WF_rx_deglitcher is
signal s_rxd_filtered, s_rxd_filtered_d1 : std_logic;
signal s_rxd_filtered_r_edge_p, s_rxd_filtered_f_edge_p : std_logic;
signal s_rxd_filtered_r_edge_p : std_logic;
signal s_rxd_filtered_f_edge_p : std_logic;
signal s_fd_rxd_no_activity : std_logic;
signal s_deglitch_c : unsigned (3 downto 0);
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
......@@ -168,6 +170,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
......
wf_rx_deserializer.vhd
View file @ ad26318d
......@@ -140,11 +140,11 @@ entity WF_rx_deserializer is
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_engine_control unit
rx_rst_p_i : in std_logic; --! receiver timeout
rx_rst_p_i : in std_logic; --! receiver reset
--! in cases when more bytes than expected are being
--! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes)
-- Signals from the WF_fd_deglitcher
-- Signals from the WF_rx_deglitcher
fd_rxd_f_edge_p_i : in std_logic; --! indicates a falling edge on the deglitched fd_rxd
fd_rxd_r_edge_p_i : in std_logic; --! indicates a rising edge on the deglitched fd_rxd
fd_rxd_i : in std_logic; --! deglitched fd_rxd
......@@ -189,9 +189,9 @@ architecture rtl of WF_rx_deserializer is
signal rx_st, nx_rx_st : rx_st_t;
signal s_idle, s_receiving_pre, s_receiving_fsd, s_receiving_bytes : std_logic;
signal s_fsd_bit, s_fes_bit, s_fsd_wrong_bit : std_logic;
signal s_fsd_bit, s_fes_bit, s_fsd_wrong_bit, s_session_timedout : std_logic;
signal s_fsd_last_bit, s_fes_wrong_bit, s_fes_detected_p : std_logic;
signal s_byte_ready_p, s_byte_ready_p_d1, s_write_bit_to_byte : std_logic;
signal s_byte_ready_p, s_byte_ready_p_d1, s_write_bit_to_byte_p : std_logic;
signal s_manch_r_edge_p, s_manch_f_edge_p, s_bit_r_edge_p, s_edge_out_manch_window_p : std_logic;
signal s_manch_bit_index_load, s_decr_manch_bit_index_p, s_manch_bit_index_is_zero : std_logic;
signal s_manch_not_ok, s_manch_code_viol_p,s_CRC_ok_p,s_CRC_ok_p_d, s_CRC_ok_p_found : std_logic;
......@@ -235,7 +235,7 @@ architecture rtl of WF_rx_deserializer is
Deserializer_FSM_Comb_State_Transitions: process (s_bit_r_edge_p, s_edge_out_manch_window_p,
rx_rst_p_i, fd_rxd_f_edge_p_i, s_manch_r_edge_p,
s_fsd_wrong_bit, s_manch_f_edge_p, rx_st,
s_fsd_last_bit, s_fes_detected_p)
s_fsd_last_bit, s_fes_detected_p, s_session_timedout)
begin
-- During the PRE, the WF_rx_osc is trying to synchronize to the transmitter's clock and every
......@@ -252,6 +252,9 @@ architecture rtl of WF_rx_deserializer is
if fd_rxd_f_edge_p_i = '1' then -- edge detection
nx_rx_st <= pre_field_first_f_edge;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= idle;
end if;
......@@ -264,6 +267,9 @@ architecture rtl of WF_rx_deserializer is
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= pre_field_first_f_edge;
end if;
......@@ -278,6 +284,9 @@ architecture rtl of WF_rx_deserializer is
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= pre_field_r_edge;
end if;
......@@ -295,6 +304,9 @@ architecture rtl of WF_rx_deserializer is
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= pre_field_f_edge;
end if;
......@@ -311,6 +323,9 @@ architecture rtl of WF_rx_deserializer is
elsif s_fsd_wrong_bit = '1' then -- wrong bit
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
nx_rx_st <= fsd_field;
end if;
......@@ -324,7 +339,13 @@ architecture rtl of WF_rx_deserializer is
-- of a correct FES, or until the arrival of a reset signal from the WF_engine_control.
when ctrl_data_fcs_fes_fields =>
if (s_fes_detected_p = '1') or (rx_rst_p_i = '1') then
if s_fes_detected_p = '1' then
nx_rx_st <= idle;
elsif rx_rst_p_i = '1' then -- arrival of more bytes than expected
nx_rx_st <= idle;
elsif s_session_timedout = '1' then -- independant timeout
nx_rx_st <= idle;
else
......@@ -418,16 +439,16 @@ architecture rtl of WF_rx_deserializer is
s_byte_ready_p_d1 <= s_byte_ready_p;
if s_write_bit_to_byte = '1' then
if s_write_bit_to_byte_p = '1' then
s_byte <= s_byte(6 downto 0) & fd_rxd_i;
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_write_bit_to_byte <= s_receiving_bytes and sample_bit_p_i;
s_write_bit_to_byte_p <= s_receiving_bytes and sample_bit_p_i;
s_byte_ready_p <= s_receiving_bytes and s_manch_bit_index_is_zero and sample_manch_bit_p_i
and (not s_fes_detected_p);
......@@ -539,11 +560,11 @@ architecture rtl of WF_rx_deserializer is
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_receiving_fsd,
data_bit_ready_p_i => s_write_bit_to_byte,
data_bit_ready_p_i => s_write_bit_to_byte_p,
data_bit_i => fd_rxd_i,
crc_o => open,
---------------------------------------------------
crc_ok_p => s_CRC_ok_p);
crc_ok_p_o => s_CRC_ok_p);
---------------------------------------------------
......@@ -615,6 +636,30 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------------------------------------------------------
-- Independant Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_decr_counter relying only on the system clock, as an additional
--! way to go back to Idle state, in case any other logic is being stuck.
Session_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
counter_load_i => s_idle,
counter_decr_p_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignments --
---------------------------------------------------------------------------------------------------
......
wf_rx_osc.vhd
View file @ ad26318d
......@@ -25,7 +25,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
---------------------------------------------------------------------------------------------------
--
--! @brief Generation the clock signals needed for the reception (WF_rx_deserializer).
--! @brief Generation of the clock signals needed for the reception (WF_rx_deserializer).
--!
--! Even if the bit rate of the communication is known, jitter is expected to affect the
--! arriving time of the incoming signal. The main idea of the unit is to recalculate
......@@ -53,7 +53,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_deglitcher \n
--! WF_rx_deserializer\n
--! WF_rx_deserializer \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -126,8 +126,8 @@ end entity WF_rx_osc;
--=================================================================================================
architecture rtl of WF_rx_osc is
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_reinit_counter, s_counter_is_full : std_logic;
signal s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
......@@ -161,7 +161,7 @@ begin
--! the counter is reinitialialized.
rx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
......
wf_rx_tx_osc.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx_tx_osc.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_tx_osc --
-- --
---------------------------------------------------------------------------------------------------
--
--! @brief Generation the clock signals needed for the receiver (WF_rx_deglitcher and
--! WF_rx_deserializer) and transmiter (WF_tx_serializer)\n
--!
--! o Concerning the reception, even if the bit rate of the communication is known,
--! jitter is expected to affect the arriving time of the incoming signal. The main idea
--! of the unit is to recalculate the expected arrival time of the next incoming bit,
--! based on the arrival of the previous one, so that drifts are not accumulated. The
--! clock recovery is based on the Manchester 2 coding which ensures that there is one
--! edge (transition) for each bit.
--!
--! In this unit, we refer to
--! o a significant edge : for the edge of a manch. encoded bit
--! (bit 0: _|-, bit 1: -|_)
--! o a transition : for the moment in between two adjacent bits,
--! that may or may not result in an edge (eg. a 0 followed by a 0 will give an edge
--! _|-|_|-, but a 0 followed by a 1 will not _|--|_ ).
--!
--!
--! o Concerning the transmission, the unit generates the nanoFIP FIELDRIVE output
--! FD_TXCK (line driver half bit clock) and the nanoFIP internal signal tx_clk_p_buff:
--!
--! FD_TXCK :___|--------...--------|________...________|--------...--------|__
--! tx_clk_p_buff (3) : |0|0|0|1 |0|0|0|1
--! tx_clk_p_buff (2) : |0|0|1|0 |0|0|1|0
--! tx_clk_p_buff (1) : |0|1|0|0 |0|1|0|0
--! tx_clk_p_buff (0) : |1|0|0|0 |1|0|0|0
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 08/12/2010
--
--
--! @version v0.03
--
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_synchronizer \n
--! WF_rx_deserializer\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 08/2009 v0.01 PS Entity Ports added, start of architecture content \n
--! -> 07/2010 v0.02 EG tx, rx counter changed from 20 bits signed, to 11 bits unsigned;
--! rx clk generation depends on edge detection;code cleanedup+commented
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! rst_rx_osc signal clearified
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.031 EG rxd_edge_i became rxd_edge_p_i; small correctiond on comments
--
---------------------------------------------------------------------------------------------------
--
--! @todo -->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_rx_tx_osc
--=================================================================================================
entity WF_rx_tx_osc is
generic (C_PERIODS_COUNTER_LENGTH : natural := 11; -- 2^ c_PERIODS_COUNTER_LENGTH: # uclk ticks
-- equivalent to the reception/ transmission
-- period. In the slowest bit rate (31.25kbps)
-- the period is 32000ns and can be measured
-- after 1280 uclk ticks. Therefore a counter
-- of 11 bits is the max needed for counting
-- transmission/ reception periods.
c_TX_CLK_BUFF_LGTH : natural := 4); -- length of tx_clk_p_buff_o (default 4)
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_synchronizer unit
rxd_edge_p_i : in std_logic; --! indication of an edge on fd_rxd
-- Signal from WF_rx_deserializer unit
rst_rx_osc_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
-- OUTPUTS
-- Output signals needed in the reception
-- Signals to the WF_rx_deserializer and the WF_rx_deglitcher
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! o on a significant edge
--! o between adjacent bits
--! ____|-|___|-|___|-|___
rx_bit_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! o between adjacent bits
--! __________|-|_________
rx_signif_edge_window_o : out std_logic; --! time window where a significant edge is expected
rx_adjac_bits_window_o : out std_logic; --! time window where a transition between adjacent
--! bits is expected
-- Output signals needed in the transmission
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; --! line driver half bit clock
-- Signal to the WF_tx_serializer unit
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
--! buffer keeping the last values of tx_clk_o
);
end entity WF_rx_tx_osc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_rx_tx_osc is
signal s_rx_counter, s_tx_counter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_period, s_jitter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_counter_full, s_half_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_one_forth_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_rx_bit_clk, s_rx_manch_clk_d1 : std_logic;
signal s_rx_bit_clk_d1, s_rx_manch_clk : std_logic;
signal s_adjac_bits_edge_found : std_logic;
signal s_signif_edge_found : std_logic;
signal s_rxd_signif_edge_window : std_logic;
signal s_rx_adjac_bits_window : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
-- # uclock ticks for a period
s_half_period <= s_period srl 1; -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
s_jitter <= s_period srl 3; -- jitter defined as 1/8 of
-- the period
s_counter_full <= s_period-1;
---------------------------------------------------------------------------------------------------
-- rx_osc --
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process rx_periods_count : the rx_counter starts counting after a falling
--! edge on the fd_rxd (indicated by the signal rst_rx_osc_i from the WF_rx_deserializer unit);
--! this edge should be representing the 1st Manchester (manch.) encoded bit '1' of the preamble.
--! Starting from this edge, other falling or rising significant edges, are expected around one
--! period later. A time window around the expected arrival time is set and its length is defined
--! as 1/4th of the period (1/8th before and 1/8th after the expected time). When the actual edge
--! arrives, the counter is reset.
--! If that first falling edge of fd_rxd is finally proven not to belong to a valid preambe
--! (the state machine of the WF_rx_deserializer unit is checking that and generating the
--! rst_rx_osc_i), the counter is reinitialialized.
rx_periods_count: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_rx_counter <= (others => '0');
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter re-initialization
if rst_rx_osc_i = '1' then
s_rx_counter <= (others => '0');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter counting
else
if (s_rxd_signif_edge_window = '1') and (rxd_edge_p_i = '1') then
s_rx_counter <= (others => '0'); -- when an edge appears inside
-- the expected window, the
-- counter is reinitialized
elsif (s_rx_counter = s_counter_full) then -- otherwise, it continues counting
s_rx_counter <= (others => '0'); -- complete nominal periods
else
s_rx_counter <= s_rx_counter + 1 ;
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Concurrent signal assignments concerning the receiver: creation of the windows where
--! "significant edges" and "adjacent bits transitions" are expected on the input signal.
--! o s_rxd_signif_edge_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the completion of a period, where significant edges are expected.
--! o s_rx_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the middle of a period, where transitions between adjacent bits are expected.
s_rxd_signif_edge_window <= '1' when ((s_rx_counter < s_jitter) or
(s_rx_counter > s_counter_full - s_jitter-1))
else '0';
s_rx_adjac_bits_window <= '1' when ((s_rx_counter >= s_half_period-s_jitter-1) and
(s_rx_counter < s_half_period+s_jitter))
else '0';
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process rx_clks: the process rx_clk is following the edges that appear on the
--! nanoFIP FIELDRIVE input fd_rxd and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- In detail, the process is looking for moments :
-- o of significant edges
-- o between boundary bits
-- the signal rx_manch_clk: is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk : is inverted only between adjacent bits
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
rx_clks: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') then
s_rx_manch_clk <='0';
s_rx_bit_clk <='0';
s_rx_bit_clk_d1 <='0';
s_rx_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_adjac_bits_edge_found <='0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding significant edges:
-- looking for a significant edge inside the corresponding window
if (s_rxd_signif_edge_window = '1') and (rxd_edge_p_i = '1') then
s_rx_manch_clk <= not s_rx_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_rx_counter = s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding edges between adjacent bits:
-- looking for an edge inside the corresponding window
elsif (s_rx_adjac_bits_window = '1') and (rxd_edge_p_i = '1') then
s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk
s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_signif_edge_found <= '0'; -- re-initialization before next cycle
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_rx_counter = s_half_period + s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk;
s_rx_bit_clk <= not s_rx_bit_clk;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_rx_manch_clk_d1 <= s_rx_manch_clk;
-- s_rx_manch_clk: ____|-----|_____|-----|____
-- s_rx_manch_clk_d1: ______|-----|_____|-----|__
-- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
s_rx_bit_clk_d1 <= s_rx_bit_clk;
-- s_rx_bit_clk: ____|-----------|___________
-- s_rx_bit_clk_d1: ______|-----------|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- tx_osc --
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process tx_periods_count: implementation of a counter counting transmission
--! periods.
tx_periods_count: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_tx_counter <= (others => '0');
s_tx_clk_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
-- free counter measuring transmission periods
if (s_tx_counter = s_counter_full) then
s_tx_counter <= (others => '0');
else
s_tx_counter <= s_tx_counter + 1 ;
end if;
-- clk signals:
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left -1 downto 0) & s_tx_clk_p;
-- buffering the s_tx_clk_p pulses
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Concurrent signal assignments concerning the transmitter:
-- Creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_tx_counter < s_one_forth_period) or
((s_tx_counter > (2*s_one_forth_period)-1) and
(s_tx_counter < 3*s_one_forth_period)))
else '0';
-- transm. period : _|----------|__________|--
-- tx_counter : 0 1/4 1/2 3/4 1
-- s_tx_clk : _|----|_____|----|_____|--
-- Creation of a pulse starting 1 uclk period before tx_clk_o
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : __|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1 : ____|-----|_____|-----|___
-- not s_tx_clk_d1 : ----|_____|-----|_____|---
-- s_tx_clk_p : __|-|___|-|___|-|___|-|___
---------------------------------------------------------------------------------------------------
-- Output signals --
---------------------------------------------------------------------------------------------------
-- Output signals construction:
-- Clocks needed for the receiver:
rx_manch_clk_p_o <= s_rx_manch_clk_d1 xor s_rx_manch_clk; -- a pulse 1-uclk period long, after
-- o a significant edge
-- o a new bit
-- ___|-|___|-|___|-|___
rx_bit_clk_p_o <= s_rx_bit_clk xor s_rx_bit_clk_d1; -- a pulse 1-uclk period long, after
-- o a new bit
-- _________|-|_________
-- Clocks needed for the transmitter:
tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
-- output signals that have also been used in this unit's processes:
rx_signif_edge_window_o <= s_rxd_signif_edge_window;
rx_adjac_bits_window_o <= s_rx_adjac_bits_window;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_status_bytes_gen.vhd
View file @ ad26318d
......@@ -100,16 +100,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_bytes_retriever \n
--! WF_prod_bytes_retriever \n
--! WF_prod_permit \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -117,9 +118,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 07/07/2009 v0.01 PA First version \n
--! -> 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status
--! errors few cycles after var_rdy deactivation
--! -> 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_i
--! -> 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i
--! for nanoFIP status bit 4; var_i input not needed as the signals
--! nfip_status_r_fcser_p_i and nfip_status_r_tler_i check the var
--! nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var
--
---------------------------------------------------------------------------------------------------
--
......@@ -154,7 +155,7 @@ port (
-- Signals from the WF_consumption unit
nfip_status_r_fcser_p_i : in std_logic; --! wrong CRC bytes received
nfip_status_r_tler_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
nfip_status_r_tler_p_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
var1_rdy_i : in std_logic; --! variable 1 ready
var2_rdy_i : in std_logic; --! variable 2 ready
......@@ -348,13 +349,15 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
s_nFIP_status_byte(c_R_TLER_INDEX) <= nfip_status_r_tler_i;
if (nfip_status_r_tler_p_i = '1') then
s_nFIP_status_byte(c_R_TLER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
s_nFIP_status_byte(c_R_FCSER_INDEX) <= nfip_status_r_fcser_p_i;
if (nfip_status_r_fcser_p_i = '1') then
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
wf_tx_osc.vhd
View file @ ad26318d
......@@ -25,16 +25,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
---------------------------------------------------------------------------------------------------
--
--! @brief Generation the clock signals needed for the transmission (WF_tx_serializer)\n
--! @brief Generation of the clock signals needed for the transmission (WF_tx_serializer)\n
--!
--! The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock)
--! and the nanoFIP internal signal tx_clk_p_buff:
--!
--! FD_TXCK : ___|--------...--------|________...________|--------...--------|_
--! tx_clk_p_buff(3) : |0|0|0|1 |0|0|0|1
--! tx_clk_p_buff(2) : |0|0|1|0 |0|0|1|0
--! tx_clk_p_buff(1) : |0|1|0|0 |0|1|0|0
--! tx_clk_p_buff(0) : |1|0|0|0 |1|0|0|0
--! uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|
--! FD_TXCK : _____|--------...--------|________...________|--------...--------|__
--! tx_clk_p_buff(3) : 0 0 0 1 0 0 0 1
--! tx_clk_p_buff(2) : 0 0 1 0 0 0 1 0
--! tx_clk_p_buff(1) : 0 1 0 0 0 1 0 0
--! tx_clk_p_buff(0) : 1 0 0 0 1 0 0 0
--!
--
--
......@@ -64,7 +65,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned;
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_rst_p_i
--! -> 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_osc_rst_p_i
--
---------------------------------------------------------------------------------------------------
--
......@@ -89,7 +90,7 @@ entity WF_tx_osc is
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control
tx_rst_p_i : in std_logic; --! transmitter timeout
tx_osc_rst_p_i : in std_logic; --! transmitter timeout
-- OUTPUTS
......@@ -110,8 +111,8 @@ end entity WF_tx_osc;
--=================================================================================================
architecture rtl of WF_tx_osc is
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LENGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LENGTH -1 downto 0);
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p, s_counter_is_full, s_reinit_counter : std_logic;
......@@ -132,7 +133,7 @@ begin
--!@brief Instantiation of a WF_incr_counter counting transmission periods.
tx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
......@@ -144,9 +145,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_rst_p_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
s_reinit_counter <= nfip_rst_i or tx_rst_p_i or s_counter_is_full;
s_reinit_counter <= nfip_rst_i or tx_osc_rst_p_i or s_counter_is_full;
......@@ -176,7 +177,7 @@ begin
clk_Signals_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then
s_tx_clk_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
......
wf_tx_serializer.vhd
View file @ ad26318d
......@@ -110,8 +110,7 @@ entity WF_tx_serializer is
-- Signals from the WF_production
byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control
tx_rst_p_i : in std_logic;
-- Signals from the WF_engine_control unit
tx_start_p_i : in std_logic; --! indication for the start of the production
byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
......@@ -126,6 +125,9 @@ entity WF_tx_serializer is
-- Signal to the WF_engine_control unit
byte_request_p_o : out std_logic;
-- Signal to the WF_tx_osc unit
tx_osc_rst_p_o : out std_logic;
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter serial data
tx_enable_o : out std_logic --! transmitter enable
......@@ -144,6 +146,7 @@ architecture rtl of WF_tx_serializer is
send_fes, stop_transmission);
signal tx_state, nx_tx_state : tx_state_t;
signal s_session_timedout : std_logic;
signal s_prepare_to_produce, s_sending_fss, s_sending_data, s_sending_crc : std_logic;
signal s_sending_fes, s_stop_transmission, s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero, s_tx_enable : std_logic;
......@@ -214,7 +217,7 @@ begin
--! transitions of the FSM
Serializer_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
tx_rst_p_i, tx_start_p_i, tx_clk_p_buff_i)
s_session_timedout,tx_start_p_i, tx_clk_p_buff_i)
begin
nx_tx_state <= idle;
......@@ -232,7 +235,7 @@ begin
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4) = '1' then
nx_tx_state <= send_fss;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -241,10 +244,10 @@ begin
when send_fss =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1' then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1') then
nx_tx_state <= send_data_byte;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -256,7 +259,7 @@ begin
if last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -265,11 +268,11 @@ begin
when send_crc_bytes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= send_fes; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_clk_p_buff_i(3), to get the 31 as top value
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -279,11 +282,11 @@ begin
when send_fes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= stop_transmission; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_clk_p_buff_i(3) to get the 15 as top value
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -295,7 +298,7 @@ begin
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -449,7 +452,7 @@ Input_Byte_Retrieval: process (uclk_i)
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
crc_ok_p => open,
crc_ok_p_o => open,
-------------------------------------------------
crc_o => s_crc_bytes);
-------------------------------------------------
......@@ -560,6 +563,28 @@ Input_Byte_Retrieval: process (uclk_i)
---------------------------------------------------------------------------------------------------
-- Independant Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_decr_counter relying only on the system clock as an additional
--! way to go back to Idle state, in case any other logic is being stuck.
Session_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
counter_load_i => s_prepare_to_produce,
counter_decr_p_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Outputs --
......@@ -569,6 +594,8 @@ Input_Byte_Retrieval: process (uclk_i)
tx_enable_o <= s_tx_enable;
tx_osc_rst_p_o <= s_session_timedout;
byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
-- request for a new byte from the WF_prod_bytes_retriever unit (passing from WF_engine_control)
......
wf_wb_controller.vhd
View file @ ad26318d
......@@ -45,7 +45,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b> \n
--! WF_production \n
--! WF_consumption \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -63,11 +62,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -107,10 +101,13 @@ architecture rtl of WF_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_stb_r_edge_p : std_logic;
signal s_wb_we_d3, s_wb_cyc_d3 : std_logic_vector (2 downto 0);
signal s_wb_stb_d4 : std_logic_vector (3 downto 0);
signal s_wb_we_synch, s_wb_cyc_synch : std_logic_vector (2 downto 0);
signal s_wb_stb_synch : std_logic_vector (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
......@@ -120,20 +117,20 @@ begin
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_stb_d4 <= (others => '0');
s_wb_cyc_d3 <= (others => '0');
s_wb_we_d3 <= (others => '0');
s_wb_stb_synch <= (others => '0');
s_wb_cyc_synch <= (others => '0');
s_wb_we_synch <= (others => '0');
else
s_wb_stb_d4 <= s_wb_stb_d4 (2 downto 0) & wb_stb_i;
s_wb_cyc_d3 <= s_wb_cyc_d3 (1 downto 0) & wb_cyc_i;
s_wb_we_d3 <= s_wb_we_d3 (1 downto 0) & wb_we_i;
s_wb_stb_synch <= s_wb_stb_synch (2 downto 0) & wb_stb_i;
s_wb_cyc_synch <= s_wb_cyc_synch (1 downto 0) & wb_cyc_i;
s_wb_we_synch <= s_wb_we_synch (1 downto 0) & wb_we_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_wb_stb_r_edge_p <= (not s_wb_stb_d4(3)) and s_wb_stb_d4(2);
s_wb_stb_r_edge_p <= (not s_wb_stb_synch(3)) and s_wb_stb_synch(2);
---------------------------------------------------------------------------------------------------
......@@ -143,8 +140,8 @@ begin
--! address corresponds to an address in the Produced memory block.
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_d3 (2) = '1') and
(s_wb_cyc_d3(2) = '1') and
(s_wb_we_synch (2) = '1') and
(s_wb_cyc_synch(2) = '1') and
(wb_adr_id_i = "010"))
else '0';
......@@ -156,8 +153,8 @@ begin
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_d3(2) = '1') and
(s_wb_we_d3(2) = '0') and
(s_wb_cyc_synch(2) = '1') and
(s_wb_we_synch(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00"))
else '0';
......
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