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nanoFIP - Gateware
Commit afec7029 authored by egousiou's avatar egousiou
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changes in slone mode to include PDU_TYPE, Length, mps bytes on production. 

changes on treatment of reset variable
temp alternative file for wf_reset_unit that assumes a PoR input
small changes regarding reseting the rx_tx_osc unit 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@96 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 7a2e56fc
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DualClkRAM.vhd
View file @ afec7029
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file DualClkRAM.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
......@@ -20,8 +28,6 @@ use PROASIC3.all;
-- --
-- DualClkRAM --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
--
......@@ -31,7 +37,7 @@ use PROASIC3.all;
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 16/08/2010
......@@ -71,14 +77,14 @@ entity DualClkRAM is
port(
-- INPUTS
-- Inpouts concerning port A
DINA : in std_logic_vector (7 downto 0); --! data in A
ADDRA : in std_logic_vector (8 downto 0); --! address A
DINA : in std_logic_vector (7 downto 0); --! data in A
ADDRA : in std_logic_vector (8 downto 0); --! address A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations
-- may be indipendant of clock B
-- Inpouts concerning port B
DINB : in std_logic_vector (7 downto 0); --! data in B
ADDRB : in std_logic_vector (8 downto 0); --! address B
DINB : in std_logic_vector (7 downto 0); --! data in B
ADDRB : in std_logic_vector (8 downto 0); --! address B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations
-- may be indipendant of clock A
......@@ -87,10 +93,10 @@ entity DualClkRAM is
-- OUTPUTS
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0); --! data out A
DOUTA : out std_logic_vector (7 downto 0);--! data out A
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) --! data out B
DOUTB : out std_logic_vector (7 downto 0) --! data out B
);
end DualClkRAM;
......
nanofip.vhd
View file @ afec7029
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file nanofip.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -199,19 +199,18 @@ architecture struc of nanofip is
signal s_cons_byte_we_from_control : std_logic;
signal s_var_from_control : t_var;
signal s_add_offset_from_control : std_logic_vector (7 downto 0);
signal s_CRC_ok_from_rx : std_logic;
signal fss_decoded_p_from_rx : std_logic;
signal s_CRC_ok_from_rx, s_urst_r_edge : std_logic;
signal fss_decoded_p_from_rx, s_assert_RSTON_p : std_logic;
signal s_stat : std_logic_vector (7 downto 0);
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_reset_status_bytes, s_sending_mps: std_logic;
signal s_crc_bad_p : std_logic;
signal s_rst_status_bytes, s_sending_mps: std_logic;
signal s_crc_bad_p, s_reset_nFIP_and_FD_p : std_logic;
signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic;
signal s_mps : std_logic_vector (7 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector (7 downto 0);
signal s_reset_rx_unit_p : std_logic;
signal s_rst_rx_unit_p : std_logic;
signal s_ctrl_byte_received, s_pdu_byte_received, s_length_byte_received : std_logic_vector (7 downto 0);
signal s_rst_var_byte_1, s_rst_var_byte_2 : std_logic_vector (7 downto 0);
signal s_rsti_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
signal s_urst_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
signal s_fd_rxd_synch, s_fd_rxd_edge, s_rxd_r_edge, s_rxd_f_edge, s_wb_cyc_synch: std_logic;
signal s_wb_we_synch, s_wb_stb_synch, s_wb_stb_r_edge: std_logic;
signal s_wb_dati_synch: std_logic_vector(7 downto 0);
......@@ -219,7 +218,7 @@ architecture struc of nanofip is
signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch: std_logic;
signal s_slone_dati_synch: std_logic_vector(15 downto 0);
signal s_rate_synch: std_logic_vector(1 downto 0);
signal s_subs_synch : std_logic_vector(7 downto 0);
signal s_subs_synch, s_rx_var_rst_byte_1, s_rx_var_rst_byte_2 : std_logic_vector(7 downto 0);
signal s_m_id_synch, s_c_id_synch : std_logic_vector(3 downto 0);
signal s_p3_lgth_synch : std_logic_vector(2 downto 0);
......@@ -229,52 +228,58 @@ begin
--=================================================================================================
---------------------------------------------------------------------------------------------------
reset_unit : wf_reset_unit
reset_unit : WF_reset_unit
port map(
uclk_i => uclk_i,
rsti_i => s_rsti_synch,
var_i => s_var_from_control,
subs_i => s_subs_synch,
rst_var_byte_1_i => s_rst_var_byte_1,
rst_var_byte_2_i => s_rst_var_byte_2,
rston_o => rston_o,
nFIP_rst_o => s_rst,
fd_rstn_o => fd_rstn_o
uclk_i => uclk_i,
urst_i => s_urst_synch,
rate_i => s_rate_synch,
urst_r_edge_i => s_urst_r_edge,
var_i => s_var_from_control,
subs_i => s_subs_synch,
rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p,
assert_RSTON_p_i => s_assert_RSTON_p,
rston_o => rston_o,
nFIP_rst_o => s_rst,
fd_rstn_o => fd_rstn_o
);
---------------------------------------------------------------------------------------------------
engine_control : wf_engine_control
engine_control : WF_engine_control
generic map( C_QUARTZ_PERIOD => C_QUARTZ_PERIOD)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => s_rst,
tx_request_byte_p_i => s_request_byte_from_tx_p,
uclk_i => uclk_i,
nFIP_urst_i => s_rst,
tx_request_byte_p_i => s_request_byte_from_tx_p,
rx_FSS_received_p_i => fss_decoded_p_from_rx,
rx_byte_ready_p_i => s_byte_from_rx_ready_p,
rx_byte_i => s_byte_from_rx,
rx_CRC_FES_ok_p_i => s_CRC_ok_from_rx,
tx_sending_mps_i => s_sending_mps,
rx_Ctrl_byte_i => s_ctrl_byte_received,
rx_PDU_byte_i => s_pdu_byte_received,
rx_Length_byte_i => s_length_byte_received,
rate_i => s_rate_synch,
subs_i => s_subs_synch,
p3_lgth_i => s_p3_lgth_synch,
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
tx_start_produce_p_o => s_start_send_p ,
tx_byte_ready_p_o => s_byte_to_tx_ready_p,
tx_last_byte_p_o => s_last_byte_to_tx_p,
tx_rx_byte_index_o => s_add_offset_from_control,
tx_data_length_o => s_data_length_from_control,
rx_byte_ready_p_o => s_cons_byte_we_from_control,
reset_rx_unit_p_o => s_reset_rx_unit_p,
reset_status_bytes_o => s_reset_status_bytes
rx_byte_ready_p_i => s_byte_from_rx_ready_p,
rx_byte_i => s_byte_from_rx,
rx_CRC_FES_ok_p_i => s_CRC_ok_from_rx,
tx_sending_mps_i => s_sending_mps,
rx_Ctrl_byte_i => s_ctrl_byte_received,
rx_PDU_byte_i => s_pdu_byte_received,
rx_Length_byte_i => s_length_byte_received,
rx_var_rst_byte_1_i => s_rx_var_rst_byte_1,
rx_var_rst_byte_2_i => s_rx_var_rst_byte_2,
rate_i => s_rate_synch,
subs_i => s_subs_synch,
p3_lgth_i => s_p3_lgth_synch,
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
tx_start_produce_p_o => s_start_send_p ,
tx_byte_ready_p_o => s_byte_to_tx_ready_p,
tx_last_byte_p_o => s_last_byte_to_tx_p,
tx_rx_byte_index_o => s_add_offset_from_control,
tx_data_length_o => s_data_length_from_control,
rx_byte_ready_p_o => s_cons_byte_we_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p,
assert_RSTON_p_o => s_assert_RSTON_p,
rst_nFIP_and_FD_p_o => s_reset_nFIP_and_FD_p,
rst_status_bytes_o => s_rst_status_bytes
);
var1_rdy_o <= s_var1_rdy;
......@@ -284,38 +289,38 @@ begin
tx_rx : wf_tx_rx
tx_rx : WF_tx_rx
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => s_rst,
reset_rx_unit_p_i => s_reset_rx_unit_p,
start_produce_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p,
byte_i => s_byte_to_tx,
last_byte_p_i => s_last_byte_to_tx_p,
tx_data_o => fx_txd_o,
tx_enable_o => fd_txena_o,
d_clk_o => fd_txck_o,
fd_rxd => s_fd_rxd_synch,
fd_rxd_edge_i => s_fd_rxd_edge,
fd_rxd_r_edge_i => s_rxd_r_edge,
fd_rxd_f_edge_i => s_rxd_f_edge,
rate_i => s_rate_synch,
byte_ready_p_o => s_byte_from_rx_ready_p,
byte_o => s_byte_from_rx,
CRC_wrong_p_o => s_crc_bad_p,
FSS_received_p_o => fss_decoded_p_from_rx,
uclk_i => uclk_i,
nFIP_urst_i => s_rst,
rst_rx_unit_p_i => s_rst_rx_unit_p,
start_produce_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p,
byte_i => s_byte_to_tx,
last_byte_p_i => s_last_byte_to_tx_p,
tx_data_o => fx_txd_o,
tx_enable_o => fd_txena_o,
d_clk_o => fd_txck_o,
fd_rxd => s_fd_rxd_synch,
fd_rxd_edge_i => s_fd_rxd_edge,
fd_rxd_r_edge_i => s_rxd_r_edge,
fd_rxd_f_edge_i => s_rxd_f_edge,
rate_i => s_rate_synch,
byte_ready_p_o => s_byte_from_rx_ready_p,
byte_o => s_byte_from_rx,
CRC_wrong_p_o => s_crc_bad_p,
FSS_received_p_o => fss_decoded_p_from_rx,
FSS_CRC_FES_viol_ok_p_o => s_CRC_ok_from_rx
);
---------------------------------------------------------------------------------------------------
consumed_vars : wf_cons_bytes_from_rx
consumed_vars : WF_cons_bytes_from_rx
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => s_rst,
nFIP_urst_i => s_rst,
slone_i => s_slone_synch,
byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control,
......@@ -330,13 +335,13 @@ begin
rx_Ctrl_byte_o => s_ctrl_byte_received,
rx_PDU_byte_o => s_PDU_byte_received,
rx_Length_byte_o => s_length_byte_received,
rst_var_byte_1_o => s_rst_var_byte_1,
rst_var_byte_2_o => s_rst_var_byte_2
rx_var_rst_byte_1_o => s_rx_var_rst_byte_1,
rx_var_rst_byte_2_o => s_rx_var_rst_byte_2
);
---------------------------------------------------------------------------------------------------
produced_vars : wf_prod_bytes_to_tx
produced_vars : WF_prod_bytes_to_tx
port map(
uclk_i => uclk_i,
......@@ -344,7 +349,7 @@ begin
c_id_dec_i => s_c_id_dec_o,
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
nFIP_u_rst_i => s_rst,
nFIP_urst_i => s_rst,
wb_clk_i => wclk_i,
wb_adr_i => s_wb_adri_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
......@@ -364,10 +369,10 @@ begin
);
---------------------------------------------------------------------------------------------------
status_bytes_gen : wf_status_bytes_gen
status_bytes_gen : WF_status_bytes_gen
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => s_rst,
nFIP_urst_i => s_rst,
slone_i => s_slone_synch,
fd_wdgn_i => s_fd_wdgn_synch,
fd_txer_i => s_fd_txer_synch,
......@@ -379,17 +384,17 @@ begin
var1_acc_i => s_var1_access_synch,
var2_acc_i => s_var2_access_synch,
var3_acc_i => s_var3_access_synch,
reset_status_bytes_i => s_reset_status_bytes,
rst_status_bytes_i => s_rst_status_bytes,
nFIP_status_byte_o => s_stat,
mps_status_byte_o => s_mps
);
---------------------------------------------------------------------------------------------------
model_constr_decoder : wf_model_constr_decoder
model_constr_decoder : WF_model_constr_decoder
generic map (C_RELOAD_MID_CID => C_RELOAD_MID_CID)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => s_rst,
nFIP_urst_i => s_rst,
s_id_o => s_id_o,
m_id_dec_o => s_m_id_dec_o,
c_id_dec_o => s_c_id_dec_o,
......@@ -400,11 +405,11 @@ begin
---------------------------------------------------------------------------------------------------
synchronizer: wf_inputs_synchronizer
synchronizer: WF_inputs_synchronizer
port map(
uclk_i => uclk_i,
wbclk_i => wclk_i,
nFIP_u_rst_i => s_rst,
nFIP_urst_i => s_rst,
rstin_a_i => rstin_i,
wb_rst_a_i => rst_i,
slone_a_i => slone_i,
......@@ -425,7 +430,8 @@ begin
m_id_a_i => m_id_i,
c_id_a_i => c_id_i,
p3_lgth_a_i => p3_lgth_i,
u_rsti_o => s_rsti_synch,
rsti_o => s_urst_synch,
urst_r_edge_o => s_urst_r_edge,
slone_o => s_slone_synch,
nostat_o => s_nostat_synch,
fd_wdgn_o => s_fd_wdgn_synch,
......
tmp_wf_reset_unit_with_PoR.vhd 0 → 100644
View file @ afec7029
--=================================================================================================
--! @file WF_reset_unit.vhd
--=================================================================================================
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
---------------------------------------------------------------------------------------------------
-- --
-- WF_reset_unit --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_reset_unit
--
--! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset
--! and user interface reset (RSTON)
--
--
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 08/2010
--
--
--! @version v0.02
--
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_cons_bytes_from_rx\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 07/2009 v0.01 EB First version \n
--! 08/2010 v0.02 EG checking of bytes1 and2 of reset var added \n
--! fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for > 16 uclk \n
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_reset_unit
--=================================================================================================
entity WF_reset_unit is
port (
-- INPUTS
-- User Interface general signals (synchronized) (after synchronization)
uclk_i : in std_logic; --! 40 MHz clock
urst_i : in std_logic; --! initialisation control, active low
urst_r_edge_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
rate_i : in std_logic_vector (1 downto 0);
-- Signal from the central control unit WF_engine_control
var_i : in t_var; --! variable type
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
-- OUTPUTS
-- nanoFIP internal reset
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
-- nanoFIP output to the User Interface
rston_o : out std_logic; --! reset output, active low
-- nanoFIP output to FIELDRIVE
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
);
end entity WF_reset_unit;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_reset_unit is
signal s_intern_rst : std_logic;
signal s_urst_c_is_eight, s_reinit_counter, s_FD_rst : std_logic;
signal s_urst_c_is_full, s_urst_c_is_ten, s_incr_counter : std_logic;
signal s_urst_c_is_two, s_RSTON_counter_is_full : std_logic;
signal s_RSTON_counter : unsigned (1 downto 0);
signal s_counter : unsigned(C_PERIODS_COUNTER_LENGTH-1 downto 0)
:= (others=>'0'); -- init for simulation
type rstin_st_t is (idle, rstin_eval, intern_rst_ON_FD_rst_ON,intern_rst_OFF_FD_rst_ON);
signal rstin_st, nx_rstin_st : rstin_st_t;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process s_rst_creation: the process follows the input signal rstin
--! and confirms that it stays active for more than 2^(C_RSTIN_C_LGTH-1) uclk cycles;
--! If so, it enables the signal s_intern_rst to follow it.
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
RSTIN_FSM_Sync: process(uclk_i)
begin
if rising_edge(uclk_i) then
-- if urst_i = '0' then --has to be the PoR; otherwise i ll always be sent to idle (coundn t count the 40cycles for ex)---------
-- rstin_st <= idle;
-- else
rstin_st <= nx_rstin_st;
-- end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process RSTIN_FSM_Comb_State_Transitions:
--! definition of the state transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st,var_i,rst_nFIP_and_FD_p_i,urst_r_edge_i,
s_urst_c_is_two,urst_i,s_urst_c_is_eight,
s_urst_c_is_ten, s_urst_c_is_full)
begin
nx_rstin_st <= idle;
case rstin_st is
when idle =>
if var_i = var_rst then
if rst_nFIP_and_FD_p_i = '1' then
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
else
nx_rstin_st <= idle;
end if;
else
if urst_r_edge_i = '1' then -- rising edges of reset move the FSM to the next state,
nx_rstin_st <= rstin_eval;-- so as not to be getting stuck if the reset is stuck
else
nx_rstin_st <= idle;
end if;
end if;
when rstin_eval =>
if urst_i = '0' then
nx_rstin_st <= idle;
else
if s_urst_c_is_eight = '1' then
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
else
nx_rstin_st <= rstin_eval;
end if;
end if;
when intern_rst_ON_FD_rst_ON =>
if var_i = var_rst then
if s_urst_c_is_two ='1' then
nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
else
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
end if;
else
if s_urst_c_is_ten ='1' then
nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
else
nx_rstin_st <= intern_rst_ON_FD_rst_ON;
end if;
end if;
when intern_rst_OFF_FD_rst_ON =>
if s_urst_c_is_full ='1' then
nx_rstin_st <= idle;
else
nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
end if;
when others =>
nx_rstin_st <= idle;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process RSTIN_FSM_Comb_Output_Signals:
--! definition of the output signals of the FSM
RSTIN_FSM_Comb_Output_Signals: process (rstin_st, urst_i)
begin
case rstin_st is
when idle =>
s_reinit_counter <= '1'; -- counter initialized
s_intern_rst <= '0';
s_FD_rst <= '0';
s_incr_counter <= '0';
when rstin_eval =>
s_reinit_counter <= '0'; -- counting (until 8)
s_intern_rst <= '0'; -- the urst_i signal
s_FD_rst <= '0';
s_incr_counter <= urst_i;
when intern_rst_ON_FD_rst_ON =>
s_reinit_counter <= '0'; -- free counter continuing counting 2 uclk periods
s_intern_rst <= '1';
s_FD_rst <= '1';
s_incr_counter <= '1';
when intern_rst_OFF_FD_rst_ON =>
s_reinit_counter <= '0'; -- free counter continuing counting (until counter full)
s_intern_rst <= '0';
s_FD_rst <= '1';
s_incr_counter <= '1';
when others =>
s_reinit_counter <= '1';
s_intern_rst <= '0';
s_FD_rst <= '0';
s_incr_counter <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- used for the evaluation of the RSTIN signal, also for counting 2 clock cycles the internal rest,
-- & ...clock cycles the fieldrive reset.
counter: WF_incr_counter
generic map (counter_length => C_PERIODS_COUNTER_LENGTH)
port map(
uclk_i => uclk_i,
nFIP_urst_i => '0' , --has to be the PoR--------------
reinit_counter_i => s_reinit_counter,
incr_counter_i => s_incr_counter,
counter_o => s_counter,
counter_is_full_o => s_urst_c_is_full);
s_urst_c_is_two <= '1' when s_counter = to_unsigned(2, s_counter'length)
else '0';
s_urst_c_is_ten <= '1' when s_counter = to_unsigned(10, s_counter'length)
else '0';
s_urst_c_is_eight <= '1' when s_counter = to_unsigned(8, s_counter'length)
else '0';
s_urst_c_is_ten <= '1' when s_counter = to_unsigned(10, s_counter'length)
else '0';
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process RSTON_generator: Generation of the RSTON signal that is enabled when
--! at the end of a valid consumed frame of a reset variable, where the 2nd data byte contains
--! the station's address. The signal stays enabled for four cycles.
---------------------------------------------------------------------------------------------------
RSTON_generator: process(uclk_i)
begin
if rising_edge(uclk_i) then
if s_intern_rst = '1' then
rston_o <= '1';
else
if assert_RSTON_p_i = '1' then -- activation after the pulse that indicates that
rston_o <= '0'; -- a valid consumed frame has arrived with its 2nd
end if; -- data byte containing the station's address.
if s_RSTON_counter_is_full = '1' then -- deactivation after 4 clock cycles
rston_o <= '1';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RSTON_free_counter: WF_incr_counter
generic map (counter_length => 2)
port map(
uclk_i => uclk_i,
nFIP_urst_i => s_intern_rst,
reinit_counter_i => assert_RSTON_p_i,
incr_counter_i => '1',
counter_o => s_RSTON_counter,
counter_is_full_o => s_RSTON_counter_is_full
);
---------------------------------------------------------------------------------------------------
--! nFIP_rst_o: nanoFIP internal reset, active high;
--! fd_rstn_o : FIELDRIVE reset, active low;
--! They are both activated by the signals:
--! Signal |Stays active for (Uclk cycles) |Constraint
--!------------------------------------------------------------------------------------------------
--! PoR |full PoR duration |No
--! RSTIN |2 |RSTIN active > 8 uclk cycles
--! s_rst_nFIP_and_FD |2 |No
nFIP_and_FD_Resets: process (uclk_i)
begin
if rising_edge(uclk_i) then
nFIP_rst_o <= s_intern_rst or s_intern_rst; -- or PoR
fd_rstn_o <= not (s_intern_rst or s_FD_rst); -- or PoR
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ afec7029
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file wf_DualClkRAM_clka_rd_clkb_wr.vhd
--! @file WF_DualClkRAM_clka_rd_clkb_wr.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
--! Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- wf_DualClkRAM_clka_rd_clkb_wr --
-- --
-- CERN, BE/CO/HT --
-- WF_DualClkRAM_clka_rd_clkb_wr --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name wf_DualClkRAM_clka_rd_clkb_wr.vhd
-- unit name WF_DualClkRAM_clka_rd_clkb_wr.vhd
--
--
--! @brief The unit provides, transparently to the outside world, the memory triplication.
......@@ -27,7 +33,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 08/2010
......@@ -58,10 +64,10 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
--! Entity declaration for wf_DualClkRAM_clka_rd_clkb_wr
--! Entity declaration for WF_DualClkRAM_clka_rd_clkb_wr
--=================================================================================================
entity wf_DualClkRAM_clka_rd_clkb_wr is
entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (C_RAM_DATA_LGTH : integer; -- length of data word
C_RAM_ADDR_LGTH : integer); -- memory depth
......@@ -77,13 +83,13 @@ entity wf_DualClkRAM_clka_rd_clkb_wr is
data_A_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
);
end wf_DualClkRAM_clka_rd_clkb_wr;
end WF_DualClkRAM_clka_rd_clkb_wr;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture syn of wf_DualClkRAM_clka_rd_clkb_wr is
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
---------------------------------------------------------------------------------------------------
--!@brief: component DualClkRam declaration
......
wf_VAR_RDY_generator.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_VAR_RDY_generator.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_VAR_RDY_generator.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,15 +14,15 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_VAR_RDY_generator --
-- WF_VAR_RDY_generator --
-- --
-- CERN, BE/CO/HT --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Generation of the nanoFIP output signals VAR1_RDY, VAR2_RDY, VAR3_RDY according to
--! the variable that is being treated (wf_engine_control signal)
--! the variable that is being treated (WF_engine_control signal)
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
......@@ -46,50 +46,61 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--
-- EG treatment of reset vars
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--! -> rename the unit to include actions for var reset.
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for wf_VAR_RDY_generator
--! Entity declaration for WF_VAR_RDY_generator
--=================================================================================================
entity wf_VAR_RDY_generator is
entity WF_VAR_RDY_generator is
port (
-- INPUTS
-- User Interface general signals
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signals from WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --!pulse after a valid consumed frame
var_i : in t_var; --! variable that is being treated
-- Signals from wf_engine_control
cons_frame_ok_p_i : in std_logic; --! pulse after a valid consumed frame
var_i : in t_var; --! variable that is being treated
-- Signals from WF_cons_bytes_from_rx
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0); --! First & second data bytes of a
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0); --! reset variable
-- OUTPUT
-- Signal to wf_engine_control
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic
-- nanoFIP output signals
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
-- Signals for the WF_reset_unit
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic
);
end entity wf_VAR_RDY_generator;
end entity WF_VAR_RDY_generator;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_VAR_RDY_generator is
architecture rtl of WF_VAR_RDY_generator is
signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
signal s_rst_nFIP_and_FD, s_assert_RSTON : std_logic;
--=================================================================================================
-- architecture begin
......@@ -130,7 +141,7 @@ signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
VAR_RDY_Generation: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
var1_rdy_o <= '0';
var2_rdy_o <= '0';
var3_rdy_o <= '0';
......@@ -207,7 +218,7 @@ signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
Cons_frame_ok_p_delay: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
cons_frame_ok_p_d1 <= '0';
else
cons_frame_ok_p_d1 <= cons_frame_ok_p_i;
......@@ -215,6 +226,50 @@ Cons_frame_ok_p_delay: process(uclk_i)
end if;
end process;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@ brief: Generation of the signals s_rst_nFIP_and_FD: signals that the 1st byte of a consumed
--! reset var contains the station address
--! and s_assert_RSTON: signals that the 2nd byte of a consumed
--! reset var contains the station address
Reset_Signals: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_rst_nFIP_and_FD <= '0';
s_assert_RSTON <= '0';
else
if var_i = var_rst then
if rx_var_rst_byte_1_i = subs_i then
s_rst_nFIP_and_FD <= '1'; -- rst_nFIP_and_FD_o stays asserted until
end if; -- the end of the current rp_dat frame
if rx_var_rst_byte_2_i = subs_i then
s_assert_RSTON <= '1'; -- assert_RSTON_o stays asserted until
end if; -- the end of the current rp_dat frame
else
s_rst_nFIP_and_FD <= '0';
s_assert_RSTON <= '0';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_nFIP_and_FD_p_o <= '1' when s_rst_nFIP_and_FD = '1' and cons_frame_ok_p_d1= '1'
else '0';
assert_RSTON_p_o <= '1' when s_assert_RSTON = '1' and cons_frame_ok_p_d1= '1'
else '0';
end architecture rtl;
--=================================================================================================
......
wf_bits_to_txd.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_bits_to_txd.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_bits_to_txd.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_bits_to_txd --
-- WF_bits_to_txd --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -59,20 +59,20 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_bits_to_txd
--! Entity declaration for WF_bits_to_txd
--=================================================================================================
entity wf_bits_to_txd is
entity WF_bits_to_txd is
generic(C_TXCLKBUFFLENTGTH: natural);
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from wf_tx
-- Signals from WF_tx
txd_bit_index_i : in unsigned(4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
......@@ -83,23 +83,23 @@ entity wf_bits_to_txd is
stop_transmission_i : in std_logic;
-- Signals for the receiver wf_tx_rx_osc
-- Signals for the receiver WF_tx_rx_osc
tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH-1 downto 0);
--! clk for transmission synchronization
-- OUTPUTS
-- Signal to wf_prod_bytes_to_tx
-- Signal to WF_prod_bytes_to_tx
txd_o : out std_logic;
tx_enable_o : out std_logic
);
end entity wf_bits_to_txd;
end entity WF_bits_to_txd;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_bits_to_txd is
architecture rtl of WF_bits_to_txd is
signal s_start_tx_enable, s_tx_enable : std_logic;
......@@ -117,7 +117,7 @@ signal s_start_tx_enable, s_tx_enable : std_logic;
Bits_Delivery: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
txd_o <= '0';
else
......@@ -158,7 +158,7 @@ signal s_start_tx_enable, s_tx_enable : std_logic;
tx_enable_manager: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
tx_enable_o <= '0';
s_start_tx_enable <= '0';
......
wf_cons_bytes_from_rx.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_cons_bytes_from_rx.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_cons_bytes_from_rx.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,15 +14,15 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_cons_bytes_from_rx --
-- WF_cons_bytes_from_rx --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: wf_cons_bytes_from_rx
-- unit name: WF_cons_bytes_from_rx
--
--! @brief Consumption of data bytes, arriving from the wf_rx unit, by registering them in
--! @brief Consumption of data bytes, arriving from the WF_rx unit, by registering them in
--! the Consumend memory, if the operation is in memory mode, or by transferring them
--! to the user interface data bus, if the operation is stand-alone.
--! In the case of a consumed reset variable, the 1st and 2nd data byte are registered
......@@ -42,9 +42,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! wf_reset_unit \n
--! wf_rx \n
--! wf_engine_control\n
--! WF_reset_unit \n
--! WF_rx \n
--! WF_engine_control\n
--
--
--! \n<b>Modified by:</b>\n
......@@ -75,18 +75,18 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_cons_bytes_from_rx
--! Entity declaration for WF_cons_bytes_from_rx
--=================================================================================================
entity wf_cons_bytes_from_rx is
entity WF_cons_bytes_from_rx is
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode (active high)
-- Signal from the wf_reset_unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nFIP_urst_i : in std_logic; --! internal reset
-- User Interface WISHBONE Slave
......@@ -100,11 +100,11 @@ port (
wb_cyc_i : in std_logic; --! WISHBONE cycle
-- Signals from the receiver wf_rx
-- Signals from the receiver WF_rx
byte_i : in std_logic_vector (7 downto 0); --! de-serialized byte
byte_ready_p_i : in std_logic; --! indication of a valid byte
-- Signals from the wf_engine_control
-- Signals from the WF_engine_control
byte_index_i : in std_logic_vector (7 downto 0); --! index of a byte inside the frame
var_i : in t_var; --! variable type
......@@ -114,26 +114,23 @@ port (
data_o : out std_logic_vector (15 downto 0);--! DAT_O bus
wb_ack_cons_p_o : out std_logic; --! WISHBONE acknowledge
-- OUTPUTS to the wf_VAR_RDY_generator
-- OUTPUTS to the WF_VAR_RDY_generator
rx_Ctrl_byte_o : out std_logic_vector (7 downto 0); --! received Control byte
rx_PDU_byte_o : out std_logic_vector (7 downto 0); --! received PDY_TYPE byte
rx_Length_byte_o : out std_logic_vector (7 downto 0); --! received Length byte
-- OUTPUTS to the wf_reset_logic
rst_var_byte_1_o : out std_logic_vector (7 downto 0); --! content of the 1st data byte of
rx_var_rst_byte_1_o : out std_logic_vector (7 downto 0); --! content of the 1st data byte of
--! a reset variable
rst_var_byte_2_o : out std_logic_vector (7 downto 0) --! content of the 2nd data byte of
rx_var_rst_byte_2_o : out std_logic_vector (7 downto 0) --! content of the 2nd data byte of
--! a reset variable
);
end entity wf_cons_bytes_from_rx;
end entity WF_cons_bytes_from_rx;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_cons_bytes_from_rx is
architecture rtl of WF_cons_bytes_from_rx is
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
......@@ -154,7 +151,7 @@ begin
-- !@brief Instantiation of a dual port Consumed RAM
--! (for both the consumed and consumed broadcast variables)
Consumption_DPRAM: wf_DualClkRAM_clka_rd_clkb_wr
Consumption_DPRAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(C_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
C_RAM_ADDR_LGTH => 9) -- 2^9: depth of consumed RAM
......@@ -204,7 +201,7 @@ begin
--! bytes are written and which are not (example Ctrl byte, CRC bytes).
--! The byte_index_i signal is counting each byte after the FSS and before the FES (therefore,
--! apart from all the pure data-bytes, it also includes the Ctrl, PDU, Length, MPS and CRC bytes).
--! The Length byte (s_rx_Length_byte) is received from the wf_rx when byte_index_i is equal to 3
--! The Length byte (s_rx_Length_byte) is received from the WF_rx when byte_index_i is equal to 3
--! and if it is correct, it indicates the amount of bytes after in the frame the Ctrl, PDU_TYPE
--! and Length and before the CRC.
......@@ -230,10 +227,10 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_1 =>
rst_var_byte_1_o <= (others => '0');
rst_var_byte_2_o <= (others => '0');
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_addr; -- base address info
-- from wf_package
-- from WF_package
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
if slone_i = '0' then
......@@ -280,8 +277,8 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
when var_2 =>
rst_var_byte_1_o <= (others => '0');
rst_var_byte_2_o <= (others => '0');
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_addr;
-- -- -- -- -- -- -- -- -- -- -- --
......@@ -327,26 +324,26 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when reset_var =>
when var_rst =>
s_write_byte_to_mem_p <= '0';
s_slone_write_byte_p <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_RESET_VAR_INDEX).base_addr;
s_base_addr <= c_VARS_ARRAY(c_VAR_RST_INDEX).base_addr;
if ((byte_ready_p_i = '1')and(byte_index_i = c_1st_DATA_BYTE_INDEX)) then -- 1st byte
rst_var_byte_1_o <= byte_i;
rst_var_byte_2_o <= (others => '0');
rx_var_rst_byte_1_o <= byte_i;
rx_var_rst_byte_2_o <= (others => '0');
elsif ((byte_ready_p_i='1')and(byte_index_i=c_2nd_DATA_BYTE_INDEX)) then -- 2nd byte
rst_var_byte_2_o <= byte_i;
rst_var_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= byte_i;
rx_var_rst_byte_1_o <= (others => '0');
else
rst_var_byte_1_o <= (others => '0');
rst_var_byte_2_o <= (others => '0');
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
end if;
......@@ -356,8 +353,8 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
rst_var_byte_1_o <= (others => '0');
rst_var_byte_2_o <= (others => '0');
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
end case;
......@@ -368,16 +365,16 @@ end process;
--! @brief Instantiation of the unit responsible for the transfer of 2 de-serialized data bytes
--! to DAT_O;
Bytes_Transfer_To_DATO: wf_slone_bytes_to_DATO
Bytes_Transfer_To_DATO: WF_slone_bytes_to_DATO
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
transfer_byte_p_i => s_slone_write_byte_p,
byte_i => byte_i,
slone_data_o => s_slone_data);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- in stand-alone mode the 16 bits DAT_O fills up with the output of the wf_slone_bytes_to_DATO
-- in stand-alone mode the 16 bits DAT_O fills up with the output of the WF_slone_bytes_to_DATO
-- unit.
-- In memory mode, the lsb of DAT_O contains the output of the reading of the consumed memory.
data_o <= s_slone_data when slone_i = '1'
......@@ -385,14 +382,14 @@ end process;
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Buffer_Ctrl_PDU_Length_bytes: Storage of the rp_dat.Control, PDU_TYPE
--! and Length bytes of an incoming rp_dat frame. The bytes are sent to the wf_VAR_RDY_generator
--! and Length bytes of an incoming rp_dat frame. The bytes are sent to the WF_VAR_RDY_generator
--! unit that accordingly enables or not the signals VAR1_RDY, VAR2_RDY.
Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
rx_Ctrl_byte_o <= (others=>'0');
rx_PDU_byte_o <= (others=>'0');
s_rx_Length_byte <= (others=>'0');
......
wf_cons_frame_validator.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_cons_frame_validator.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_cons_frame_validator.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_cons_frame_validator --
-- WF_cons_frame_validator --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -56,37 +56,37 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_cons_frame_validator
--! Entity declaration for WF_cons_frame_validator
--=================================================================================================
entity wf_cons_frame_validator is
entity WF_cons_frame_validator is
port (
-- INPUTS
-- Signals from the wf_cons_bytes_from_rx unit
-- Signals from the WF_cons_bytes_from_rx unit
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
rx_PDU_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
rx_Length_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
-- Signal from the wf_rx unit
-- Signal from the WF_rx unit
rx_FSS_CRC_FES_viol_ok_p_i : in std_logic; --! indication that CRC and FES have
-- Signals from wf_engine_control
-- Signals from WF_engine_control
var_i: in t_var;
rx_byte_index_i : in unsigned(7 downto 0);
-- OUTPUT
-- Signal to wf_engine_control
-- Signal to WF_engine_control
cons_frame_ok_p_o : out std_logic
);
end entity wf_cons_frame_validator;
end entity WF_cons_frame_validator;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_cons_frame_validator is
architecture rtl of WF_cons_frame_validator is
signal s_rx_ctrl_byte_ok, s_rx_PDU_byte_ok, s_rx_length_byte_ok : std_logic;
......
wf_crc.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_crc.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_crc.vhd
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
......@@ -9,15 +17,16 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
---------------------------------------------------------------------------------------------------
-- --
-- wf_crc --
-- --
-- CERN, BE/CO/HT --
-- WF_crc --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name wf_crc
-- unit name WF_crc
--
--
--! @brief The unit includes the modules for the generation of the CRC of serialized data,
......@@ -25,7 +34,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 08/2010
......@@ -59,14 +68,14 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
--! Entity declaration for wf_crc
--! Entity declaration for WF_crc
--=================================================================================================
entity wf_crc is
generic(c_GENERATOR_POLY_length : natural := 16);
entity WF_crc is
generic(c_GENERATOR_POLY_length : natural);
port (
-- INPUTS
uclk_i : in std_logic; --! 40 MHz clock
nFIP_u_rst_i : in std_logic; --! internal reset
nFIP_urst_i : in std_logic; --! internal reset
start_CRC_p_i : in std_logic; --! signaling the beginning of the CRC calculation
data_bit_i : in std_logic; --! incoming data bit stream
data_bit_ready_p_i : in std_logic; --! signaling that data_bit_i can be sampled
......@@ -74,24 +83,15 @@ port (
-- OUTPUTS
CRC_ok_p : out std_logic; --! signaling of a correct received CRC syndrome
CRC_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
-- 2 bytes
);
end entity wf_crc;
end entity WF_crc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_crc is
--! shift register xor mask
constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0) :=
"0001110111001111";
--! CRC check mask
constant c_VERIFICATION_MASK:std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
"0001110001101011";
architecture rtl of WF_crc is
signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0);
......@@ -126,7 +126,7 @@ end generate;
CRC_calculation: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to annex A)
......
wf_decr_counter.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_decr_counter.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -11,7 +11,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- wf_decr_counter --
-- WF_decr_counter --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -52,18 +52,18 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
--! Entity declaration for wf_decr_counter
--! Entity declaration for WF_decr_counter
--=================================================================================================
entity wf_decr_counter is
entity WF_decr_counter is
generic(counter_length : natural);
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from any unit
counter_top : in unsigned (counter_length-1 downto 0); --! load value
......@@ -76,13 +76,13 @@ entity wf_decr_counter is
counter_o : out unsigned (counter_length-1 downto 0);--! counter
counter_is_zero_o : out std_logic --! empty counter indication
);
end entity wf_decr_counter;
end entity WF_decr_counter;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_decr_counter is
architecture rtl of WF_decr_counter is
signal s_counter : unsigned(counter_length-1 downto 0);
......@@ -95,7 +95,7 @@ signal s_counter : unsigned(counter_length-1 downto 0);
Decr_Counter: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_counter <= (others => '0');
else
......
wf_engine_control.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_engine_control.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_engine_control.vhd
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
......@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all;
---------------------------------------------------------------------------------------------------
-- --
-- wf_engine_control --
-- WF_engine_control --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name wf_control
-- unit name WF_control
--
--
--! @brief Nanofip control unit. It treats variable production and consuptions requests and manage timeouts. \n
......@@ -40,10 +40,10 @@ use work.WF_PACKAGE.all;
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! wf_engine \n
--! WF_engine \n
--! tx_engine \n
--! clk_gen \n
--! wf_reset_unit \n
--! WF_reset_unit \n
--! consumed_ram \n
--
--
......@@ -69,82 +69,88 @@ use work.WF_PACKAGE.all;
--=================================================================================================
--! Entity declaration for wf_engine_control
--! Entity declaration for WF_engine_control
--=================================================================================================
entity wf_engine_control is
entity WF_engine_control is
generic( C_QUARTZ_PERIOD : real);
port (
-- INPUTS
-- User Interface general signals
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! no NanoFIP status transmission
rate_i : in std_logic_vector (1 downto 0); --! Worldfip bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the wf_tx unit
tx_request_byte_p_i : in std_logic; --!
-- Signals from the wf_rx unit
rx_FSS_received_p_i : in std_logic; --! correct FSS detected by wf_rx
rx_byte_ready_p_i : in std_logic; --! new byte from the receiver on rx_byte_i
rx_byte_i : in std_logic_vector (7 downto 0); -- Decoded byte
rx_CRC_FES_ok_p_i : in std_logic;
-- Signal from the wf_prod_bytes_to_tx
tx_sending_mps_i : in std_logic;
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! no NanoFIP status transmission
rate_i : in std_logic_vector (1 downto 0); --! Worldfip bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_tx unit
tx_request_byte_p_i : in std_logic; --!
-- Signals from the WF_rx unit
rx_FSS_received_p_i : in std_logic; --! correct FSS detected by WF_rx
rx_byte_ready_p_i : in std_logic; --! new byte from the receiver on rx_byte_i
rx_byte_i : in std_logic_vector (7 downto 0); -- Decoded byte
rx_CRC_FES_ok_p_i : in std_logic;
-- Signal from the WF_prod_bytes_to_tx
tx_sending_mps_i : in std_logic;
-- Signal from the WF_prod_bytes_to_tx
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-- OUTPUTS
-- User interface, non-WISHBONE nanoFIP outputs
var1_rdy_o : out std_logic; --! signals new data received and can safely be read
var2_rdy_o : out std_logic; --! signals new data received and can safely be read
var3_rdy_o : out std_logic; --! signals that data can safely be written in the memory
var1_rdy_o : out std_logic; --! signals new data received and can safely be read
var2_rdy_o : out std_logic; --! signals new data received and can safely be read
var3_rdy_o : out std_logic; --! signals that data can safely be written in the memory
-- Outputs to the wf_tx unit
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
-- Outputs to the WF_tx unit
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
-- Output to wf_rx
reset_rx_unit_p_o : out std_logic; --! if an FES has not arrived after 8 bytes of an id_dat,
-- Output to WF_rx
rst_rx_unit_p_o : out std_logic;--! if an FES has not arrived after 8 bytes of an id_dat,
--! or after 134 bytes of an rp_dat, the state machine
--! of the wf_rx unit returns to idle state
--! of the WF_rx unit returns to idle state
-- Output to WF_concumed_vars and WF_prod_bytes_to_tx
var_o : out t_var;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
-- Output to wf_concumed_vars and wf_prod_bytes_to_tx
var_o : out t_var;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
-- Output to WF_prod_bytes_to_tx
tx_data_length_o : out std_logic_vector (7 downto 0);
-- Output to wf_prod_bytes_to_tx
tx_data_length_o : out std_logic_vector (7 downto 0);
-- Output to WF_tx
tx_byte_ready_p_o : out std_logic;
-- Output to wf_tx
tx_byte_ready_p_o : out std_logic;
-- output to WF_cons_bytes_from_rx
rx_byte_ready_p_o : out std_logic;
-- output to wf_cons_bytes_from_rx
rx_byte_ready_p_o : out std_logic;
-- Output to WF_reset_unit
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic;
-- output to the wf_reset_unit
reset_status_bytes_o : out std_logic
-- output to the WF_status_bytes_gen
rst_status_bytes_o : out std_logic
);
end entity wf_engine_control;
end entity WF_engine_control;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_engine_control is
architecture rtl of WF_engine_control is
type control_st_t is (idle, id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte, consume, consume_wait_FSS,
......@@ -192,7 +198,7 @@ begin
Central_Control_FSM_Sync: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
control_st <= idle;
else
control_st <= nx_control_st;
......@@ -462,7 +468,7 @@ begin
---------------------------------------------------------------------------------------------------
Prod_Data_Length_Calculator: wf_prod_data_lgth_calc
Prod_Data_Length_Calculator: WF_prod_data_lgth_calc
port map(
slone_i => slone_i,
nostat_i => nostat_i,
......@@ -475,7 +481,7 @@ begin
tx_data_length_o <= s_tx_data_length;
---------------------------------------------------------------------------------------------------
Cons_Frame_Validator: wf_cons_frame_validator
Cons_Frame_Validator: WF_cons_frame_validator
port map(
rx_Ctrl_byte_i => rx_Ctrl_byte_i,
rx_PDU_byte_i => rx_PDU_byte_i,
......@@ -489,42 +495,48 @@ begin
);
---------------------------------------------------------------------------------------------------
VAR_RDY_Signals_Generation: wf_VAR_RDY_generator
VAR_RDY_Signals_Generation: WF_VAR_RDY_generator
port map (
uclk_i => uclk_i,
slone_i => slone_i,
nFIP_u_rst_i => nFIP_u_rst_i,
cons_frame_ok_p_i => s_cons_frame_ok_p,
var_i => s_var,
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
nFIP_urst_i => nFIP_urst_i,
cons_frame_ok_p_i => s_cons_frame_ok_p,
var_i => s_var,
rx_var_rst_byte_1_i => rx_var_rst_byte_1_i,
rx_var_rst_byte_2_i => rx_var_rst_byte_2_i,
---------------------------------------
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
var3_rdy_o => var3_rdy_o
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
var3_rdy_o => var3_rdy_o,
assert_RSTON_p_o => assert_RSTON_p_o,
rst_nFIP_and_FD_p_o => rst_nFIP_and_FD_p_o
---------------------------------------
);
---------------------------------------------------------------------------------------------------
--!@brief Counter that counts the number of produced or consumed bytes of data.
Rx_Bytes_Counter: wf_incr_counter
Rx_Bytes_Counter: WF_incr_counter
generic map(counter_length => 8)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
reset_counter_i => s_rst_rx_bytes_counter,
incr_counter_i => s_inc_rx_bytes_counter,
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
reinit_counter_i => s_rst_rx_bytes_counter,
incr_counter_i => s_inc_rx_bytes_counter,
---------------------------------------------
counter_o => s_rx_bytes_c
counter_o => s_rx_bytes_c,
counter_is_full_o => open
---------------------------------------------
);
---------------------------------------------------------------------------------------------------
--!@brief Counter that counts the number of produced or consumed bytes of data.
Tx_Bytes_Counter: wf_incr_counter
Tx_Bytes_Counter: WF_incr_counter
generic map(counter_length => 8)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
reset_counter_i => s_rst_tx_bytes_counter,
nFIP_urst_i => nFIP_urst_i,
reinit_counter_i => s_rst_tx_bytes_counter,
incr_counter_i => s_inc_tx_bytes_counter,
---------------------------------------------
counter_o => s_tx_bytes_c
......@@ -584,11 +596,11 @@ begin
-- Managing the counter that counts either response or silence times in uclk ticks.
-- The same counter is used in both cases. The signal s_time_counter_top initializes the counter
-- to either the response or the silence time.
Response_and_Silence_Time_Counter: wf_decr_counter
Response_and_Silence_Time_Counter: WF_decr_counter
generic map(counter_length => 15)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
counter_top => s_time_counter_top,
counter_load_i => s_load_time_c,
counter_decr_p_i => '1',
......@@ -600,7 +612,7 @@ Response_and_Silence_Time_Counter: wf_decr_counter
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of response and silence times information (in equivalent number of uclk ticks) from
-- the c_TIMEOUTS_TABLE declared in the wf_package unit.
-- the c_TIMEOUTS_TABLE declared in the WF_package unit.
s_response_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).response),
s_response_time'length);
......@@ -666,7 +678,7 @@ Response_and_Silence_Time_Counter: wf_decr_counter
id_dat_var: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_var <= var_whatever;
s_var_aux <= var_whatever;
else
......@@ -714,7 +726,7 @@ Response_and_Silence_Time_Counter: wf_decr_counter
end if;
end loop;
if ((s_var_aux = var_2) or (s_var_aux = reset_var)) then
if ((s_var_aux = var_2) or (s_var_aux = var_rst)) then
s_broadcast_var <= '1';
end if;
......@@ -728,7 +740,7 @@ Response_and_Silence_Time_Counter: wf_decr_counter
process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
tx_last_byte_p_o <= '0';
s_tx_last_byte_p_d <= '0';
s_tx_byte_ready_p_d1 <= '0';
......@@ -754,11 +766,11 @@ Response_and_Silence_Time_Counter: wf_decr_counter
tx_byte_ready_p_o <= s_tx_byte_ready_p_d2;
s_tx_last_byte_p <= s_producing and s_tx_data_length_match and tx_request_byte_p_i;
reset_status_bytes_o <= s_producing and s_tx_byte_ready_p_d2 and tx_sending_mps_i;
rst_status_bytes_o <= s_producing and s_tx_byte_ready_p_d2 and tx_sending_mps_i;
rx_byte_ready_p_o <= s_consuming and rx_byte_ready_p_i;
reset_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i;
rst_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i;
---------------------------------------------------------------------------------------------------
......
wf_incr_counter.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_incr_counter.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------
--! @file WF_incr_counter.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -11,18 +19,16 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- wf_incr_counter --
-- --
-- CERN, BE/CO/HT --
-- WF_incr_counter --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Synchronous increasing counter with a reset and an increase enable signal;
--! @brief Fully synchronous increasing counter with a reset, a reinitialise & an enable signal
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--
--
--! @date 06/2010
......@@ -52,51 +58,53 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
--! Entity declaration for wf_incr_counter
--! Entity declaration for WF_incr_counter
--=================================================================================================
entity wf_incr_counter is
entity WF_incr_counter is
generic(counter_length : natural);
port (
-- INPUTS
-- User Interface general signals
uclk_i : in std_logic; --! 40MHz clock
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from any unit
reset_counter_i : in std_logic; --! resets counter to 0
incr_counter_i: in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0
incr_counter_i: in std_logic; --! increment enable
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned(counter_length-1 downto 0) --! counter
counter_o : out unsigned(counter_length-1 downto 0); --! counter
counter_is_full_o : out std_logic --! all counter bits at '1'
);
end entity wf_incr_counter;
end entity WF_incr_counter;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_incr_counter is
architecture rtl of WF_incr_counter is
signal s_counter : unsigned(counter_length-1 downto 0);
signal s_counter, s_counter_full : unsigned(counter_length-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_counter_full <= (others => '1');
---------------------------------------------------------------------------------------------------
Incr_Counter: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_counter <= (others => '0');
elsif reset_counter_i = '1' then
elsif reinit_counter_i = '1' then
s_counter <= (others => '0');
elsif incr_counter_i = '1' then
......@@ -106,7 +114,9 @@ signal s_counter : unsigned(counter_length-1 downto 0);
end if;
end process;
counter_o <= s_counter;
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter= s_counter_full
else '0';
end architecture rtl;
--=================================================================================================
......
wf_inputs_synchronizer.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_inputs_synchronizer.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_inputs_synchronizer.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_inputs_synchronizer --
-- WF_inputs_synchronizer --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -56,21 +56,21 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_inputs_synchronizer
--! Entity declaration for WF_inputs_synchronizer
--=================================================================================================
entity wf_inputs_synchronizer is
entity WF_inputs_synchronizer is
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- User Interface WISHBONE slave
wbclk_i : in std_logic; --! WISHBONE clock
wb_rst_a_i : in std_logic; --! WISHBONE reset
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Rest of input signals
rstin_a_i : in std_logic;
......@@ -95,8 +95,8 @@ entity wf_inputs_synchronizer is
-- OUTPUTS
-- Signals to nanofip
u_rsti_o : out std_logic; -- rstin_a_i synchronized to uclk
-- wb_rsti_o : out std_logic; -- rstin_a_i synchronized to wbclk
rsti_o : out std_logic; -- rstin_a_i synchronized to uclk
urst_r_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
fd_wdgn_o : out std_logic;
......@@ -121,13 +121,13 @@ entity wf_inputs_synchronizer is
c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0)
);
end entity wf_inputs_synchronizer;
end entity WF_inputs_synchronizer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_inputs_synchronizer is
architecture rtl of WF_inputs_synchronizer is
signal s_wb_we_d3, s_wb_cyc_d1, s_wb_cyc_d2, s_wb_cyc_d3, s_fd_rxd_f_edge : std_logic;
signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1, s_fd_rxd_r_edge : std_logic;
......@@ -136,8 +136,9 @@ architecture rtl of wf_inputs_synchronizer is
signal s_wb_stb_d1, s_wb_stb_d2, s_wb_stb_d3, s_wb_stb_d4, s_wb_we_d1, s_wb_we_d2 : std_logic;
signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3, s_u_rst_d3 : std_logic_vector(2 downto 0);
signal s_nostat_d3, s_slone_d3, s_rsti_w_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_u_rst_d3 : std_logic_vector(3 downto 0);--:= "0000";
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_wb_adr_d1, s_wb_adr_d2, s_wb_adr_d3 : std_logic_vector(9 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
......@@ -157,32 +158,19 @@ architecture rtl of wf_inputs_synchronizer is
begin
if rising_edge(uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (1 downto 0) & (not rstin_a_i);
s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & (not rstin_a_i);
end if;
end process;
u_rsti_o <= s_u_rst_d3(2); -- active high
---------------------------------------------------------------------------------------------------
-- rstin_synchronisation_with_wclk: process (wbclk_i)
-- begin
-- if rising_edge(wbclk_i) then
-- s_wb_rsti_d3 <= s_wb_rsti_d3 (1 downto 0) & (not rstin_a_i);
-- end if;
-- end process;
-- rsti_wb_o <= s_wb_rsti_d3(2); -- active high
rsti_o <= s_u_rst_d3(2); -- active high
urst_r_edge_o <= not s_u_rst_d3(3) and s_u_rst_d3(2);
---------------------------------------------------------------------------------------------------
User_interf_general_signals_synchronisation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_slone_d3 <= (others => '0');
s_nostat_d3 <= (others => '0');
else
......@@ -201,7 +189,7 @@ architecture rtl of wf_inputs_synchronizer is
fieldrive_inputs_synchronisation: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_fd_rxd_d3 <= (others => '0');
s_fd_wdgn_d3 <= (others => '0');
s_fd_txer_d3 <= (others => '0');
......@@ -230,7 +218,7 @@ architecture rtl of wf_inputs_synchronizer is
VAR_ACC_synchronisation: process(uclk_i)
begin
if rising_edge (uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_var1_access_d1 <= '0';
s_var1_access_d2 <= '0';
s_var1_access_d3 <= '0';
......@@ -321,7 +309,7 @@ architecture rtl of wf_inputs_synchronizer is
Slone_dat_i_synchronization: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_slone_dati_d1 <= (others => '0');
s_slone_dati_d2 <= (others => '0');
s_slone_dati_d3 <= (others => '0');
......@@ -340,7 +328,7 @@ architecture rtl of wf_inputs_synchronizer is
WFIP_settings_synchronisation: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_rate_d1 <= (others => '0');
s_rate_d2 <= (others => '0');
s_rate_d3 <= (others => '0');
......
wf_manch_code_viol_check.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_decr_counter.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,21 +22,19 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_manch_code_viol_check --
-- --
-- CERN, BE/CO/HT --
-- WF_manch_code_viol_check --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit follows the incoming serial signal and outputs a pulse
--! @brief The unit follows an incoming serial signal and outputs a pulse
--! if a manchester 2 code violation is detected.
--! It is assumed that a violation happens if after half reception period
--! plus 2 uclck periods, the incoming signal has not had a transition.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 06/2010
......@@ -58,37 +64,37 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_manch_code_viol_check
--! Entity declaration for WF_manch_code_viol_check
--=================================================================================================
entity wf_manch_code_viol_check is
entity WF_manch_code_viol_check is
port (
-- INPUTS
-- User Interface general signals
uclk_i : in std_logic; --! 40MHz clock
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from wf_rx
serial_input_signal_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
-- Signals from WF_rx
serial_input_signal_i : in std_logic; --! input signal
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
-- OUTPUTS
-- Signal to wf_rx
manch_code_viol_p_o : out std_logic
-- Signal to WF_rx
manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
);
end entity wf_manch_code_viol_check;
end entity WF_manch_code_viol_check;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_manch_code_viol_check is
architecture rtl of WF_manch_code_viol_check is
signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input_signal_d : std_logic;
signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_signal_d : std_logic;
--=================================================================================================
-- architecture begin
......@@ -99,9 +105,9 @@ signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Check_Code_Violations:in order to check the existance code violations
--!@brief Synchronous process Check_Code_Violations:in order to check the existance code violations
--! the input signal is delayed by half reception period.
--! The signal s_check_code_viol_p is a pulse with period the reception period. The pulse occurs
--! The signal check_code_viol_p is a pulse with period the reception period. The pulse occurs
--! 2 uclk periods after a manch. transition is expected.
--! As the following drawing roughly indicates, a violation exists if the signal and its delayed
--! version are identical on the s_check_code_viol_p moments.
......@@ -114,7 +120,7 @@ signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input
Check_code_violations: process(uclk_i)
begin
if rising_edge (uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_check_code_viol_p <='0';
s_sample_bit_p_d1 <='0';
s_sample_bit_p_d2 <='0';
......
wf_model_constr_decoder.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_model_constr_decoder.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_model_constr_decoder.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -12,13 +20,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- wf_model_constr_decoder --
-- --
-- CERN, BE/CO/HT --
-- WF_model_constr_decoder --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name wf_model_constr_decoder
-- unit name WF_model_constr_decoder
--
--
--! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
......@@ -44,7 +50,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! wf_reset_unit\n
--! WF_reset_unit\n
--
--
--! \n<b>Modified by:</b>\n
......@@ -74,9 +80,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
--! Entity declaration for wf_model_constr_decoder
--! Entity declaration for WF_model_constr_decoder
--=================================================================================================
entity wf_model_constr_decoder is
entity WF_model_constr_decoder is
generic (C_RELOAD_MID_CID : natural); --! reloading of model & constructor
--! every 2^(C_RELOAD_MID_CID) uclk ticks
port (
......@@ -84,8 +90,8 @@ entity wf_model_constr_decoder is
-- User Interface general signal
uclk_i : in std_logic; --! 40 Mhz clock
-- Signal from the wf_reset_unit
nFIP_u_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_reset_unit
nFIP_urst_i : in std_logic; --! nanoFIP internal reset
-- WorldFIP settings
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
......@@ -96,12 +102,12 @@ entity wf_model_constr_decoder is
-- WorldFIP settings nanoFIP output
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- Output to wf_prod_bytes_to_tx
-- Output to WF_prod_bytes_to_tx
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
);
end entity wf_model_constr_decoder;
end entity WF_model_constr_decoder;
......@@ -109,7 +115,7 @@ end entity wf_model_constr_decoder;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_model_constr_decoder is
architecture rtl of WF_model_constr_decoder is
signal s_load_model_constr_p : std_logic;
......@@ -138,7 +144,7 @@ begin
Model_Constructor_Decoder: process(uclk_i)
begin
if rising_edge(uclk_i) then -- initializations
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_counter <= (others => '0');
m_id_dec_o <= (others => '0');
c_id_dec_o <= (others => '0');
......
wf_package.vhd
View file @ afec7029
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
package wf_package is
package WF_package is
constant C_QUARTZ_PERIOD : real := 25.0;
......@@ -26,7 +26,17 @@ package wf_package is
constant C_RELOAD_MID_CID : natural := 8;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the CRC calcutator
constant c_GENERATOR_POLY_length : natural:= 16;
-- shift register xor mask
constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length- 1 downto 0) :=
"0001110111001111";
-- CRC check mask
constant c_VERIFICATION_MASK:std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
"0001110001101011";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the manchester coding
constant VP : std_logic_vector (1 downto 0) := "11";
......@@ -88,7 +98,7 @@ package wf_package is
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000010" -- reserved ----------!!!!!!!!!!
others => "00000010" -- reserved
);
......@@ -96,23 +106,24 @@ package wf_package is
-- calculations of the number of uclk ticks equivalent to the reception/ transmission period
constant C_PERIODS_COUNTER_LENGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- transmission/reception periods.
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- transmission/reception periods.
constant c_UCLK_TICKS_31_25Kbit:unsigned:=
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit:unsigned:=
to_unsigned((32000/ integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
constant c_UCLK_TICKS_1_Mbit:unsigned:=
constant c_BIT_RATE_UCLK_TICKS_1_Mbit:unsigned:=
to_unsigned((1000/ integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
constant c_UCLK_TICKS_2_5_Mbit:unsigned:=
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit:unsigned:=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
-- formation of a table with the c_uclk_ticks info per bit rate
-- formation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
constant C_UCLK_TICKS : t_uclk_ticks(3 downto 0) := (0 => (c_UCLK_TICKS_31_25Kbit),
1 => (c_UCLK_TICKS_1_Mbit),
2 => (c_UCLK_TICKS_2_5_Mbit),
3 => (c_UCLK_TICKS_2_5_Mbit));
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks(3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table with the timeout and silence times for each bit rate
......@@ -150,7 +161,7 @@ package wf_package is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table with that gathers all the main information for all the variables
type t_var is (presence_var, identif_var, var_1, var_2, var_3, reset_var, var_whatever);
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector (7 downto 0);
......@@ -168,17 +179,17 @@ package wf_package is
type t_var_array is array (natural range <>) of t_var_record;
constant c_PRESENCE_VAR_INDEX : integer := 0;
constant c_IDENTIF_VAR_INDEX : integer := 1;
constant c_VAR_PRESENCE_INDEX : integer := 0;
constant c_VAR_IDENTIF_INDEX : integer := 1;
constant c_VAR_3_INDEX : integer := 2;
constant c_VAR_1_INDEX : integer := 3;
constant c_VAR_2_INDEX : integer := 4;
constant c_RESET_VAR_INDEX : integer := 5;
constant c_VAR_RST_INDEX : integer := 5;
constant c_VARS_ARRAY : t_var_array(0 to 5) :=
(c_PRESENCE_VAR_INDEX => (var => presence_var,
(c_VAR_PRESENCE_INDEX => (var => var_presence,
hexvalue => x"14",
response => produce,
base_addr => "---------",
......@@ -190,7 +201,7 @@ package wf_package is
7 => x"00", others => x"ff")),
c_IDENTIF_VAR_INDEX => (var => identif_var,
c_VAR_IDENTIF_INDEX => (var => var_identif,
hexvalue => x"10",
response => produce,
array_length => "00001010", -- 11 bytes in total including the Control byte
......@@ -235,7 +246,7 @@ package wf_package is
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
c_RESET_VAR_INDEX => (var => reset_var,
c_VAR_RST_INDEX => (var => var_rst,
hexvalue => x"e0",
response => reset,
base_addr => "010000000",
......@@ -251,12 +262,12 @@ package wf_package is
-- Components definitions: --
---------------------------------------------------------------------------------------------------
component wf_inputs_synchronizer is
component WF_inputs_synchronizer is
port (
uclk_i : in std_logic;
wbclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
rstin_a_i : in std_logic;
wb_rst_a_i : in std_logic;
slone_a_i : in std_logic;
......@@ -278,7 +289,8 @@ component wf_inputs_synchronizer is
c_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
u_rsti_o : out std_logic;
rsti_o : out std_logic;
urst_r_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
fd_wdgn_o : out std_logic;
......@@ -303,16 +315,16 @@ component wf_inputs_synchronizer is
c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0)
);
end component wf_inputs_synchronizer;
end component WF_inputs_synchronizer;
---------------------------------------------------------------------------------------------------
component wf_rx
component WF_rx
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
reset_rx_unit_p_i : in std_logic;
nFIP_urst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
rxd_r_edge_i : in std_logic;
......@@ -327,18 +339,18 @@ component wf_rx
CRC_wrong_p_o : out std_logic;
FSS_CRC_FES_viol_ok_p_o : out std_logic;
FSS_received_p_o : out std_logic;
wait_rxd_first_f_edge_o : out std_logic
rst_rx_osc_o : out std_logic
);
end component wf_rx;
end component WF_rx;
---------------------------------------------------------------------------------------------------
component wf_tx
component WF_tx
generic (C_TXCLKBUFFLENTGTH : natural);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
......@@ -349,11 +361,11 @@ component wf_rx
tx_data_o : out std_logic;
tx_enable_o : out std_logic
);
end component wf_tx;
end component WF_tx;
---------------------------------------------------------------------------------------------------
component wf_rx_tx_osc
component WF_rx_tx_osc
generic (C_PERIODS_COUNTER_LENGTH : natural;
C_QUARTZ_PERIOD : real;
C_TXCLKBUFFLENTGTH : natural);
......@@ -361,10 +373,10 @@ component wf_rx
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
rxd_edge_i : in std_logic;
rxd_f_edge_i : in std_logic;
wait_rxd_first_f_edge_i : in std_logic;
rst_rx_osc_i : in std_logic;
rx_manch_clk_p_o : out std_logic;
rx_bit_clk_p_o : out std_logic;
......@@ -374,17 +386,17 @@ component wf_rx
tx_clk_p_buff_o : out std_logic_vector (C_TXCLKBUFFLENTGTH -1 downto 0)
);
end component wf_rx_tx_osc;
end component WF_rx_tx_osc;
---------------------------------------------------------------------------------------------------
component wf_tx_rx
component WF_tx_rx
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nFIP_u_rst_i : in std_logic;
reset_rx_unit_p_i : in std_logic;
nFIP_urst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
......@@ -404,15 +416,15 @@ component wf_rx
FSS_CRC_FES_viol_ok_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0)
);
end component wf_tx_rx;
end component WF_tx_rx;
---------------------------------------------------------------------------------------------------
component wf_cons_bytes_from_rx
component WF_cons_bytes_from_rx
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
......@@ -426,33 +438,33 @@ component wf_rx
rx_Ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_PDU_byte_o : out std_logic_vector (7 downto 0);
rx_Length_byte_o : out std_logic_vector (7 downto 0);
rst_var_byte_1_o : out std_logic_vector (7 downto 0);
rst_var_byte_2_o : out std_logic_vector (7 downto 0)
rx_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
rx_var_rst_byte_2_o : out std_logic_vector (7 downto 0)
);
end component wf_cons_bytes_from_rx;
end component WF_cons_bytes_from_rx;
---------------------------------------------------------------------------------------------------
component wf_slone_bytes_to_DATO is
component WF_slone_bytes_to_DATO is
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
transfer_byte_p_i: in std_logic_vector (1 downto 0);
byte_i : in std_logic_vector (7 downto 0);
slone_data_o : out std_logic_vector(15 downto 0)
);
end component wf_slone_bytes_to_DATO;
end component WF_slone_bytes_to_DATO;
---------------------------------------------------------------------------------------------------
component wf_prod_bytes_to_tx is
component WF_prod_bytes_to_tx is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
m_id_dec_i : in std_logic_vector (7 downto 0);
c_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic;
......@@ -473,83 +485,87 @@ end component wf_slone_bytes_to_DATO;
byte_o : out std_logic_vector (7 downto 0);
wb_ack_prod_p_o : out std_logic
);
end component wf_prod_bytes_to_tx;
end component WF_prod_bytes_to_tx;
---------------------------------------------------------------------------------------------------
component wf_slone_DATI_bytes_sampler is
component WF_slone_DATI_bytes_sampler is
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
slone_byte_o : out std_logic_vector (7 downto 0)
);
end component wf_slone_DATI_bytes_sampler;
end component WF_slone_DATI_bytes_sampler;
---------------------------------------------------------------------------------------------------
component wf_engine_control
component WF_engine_control
generic( C_QUARTZ_PERIOD : real);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_request_byte_p_i : in std_logic;
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_request_byte_p_i : in std_logic;
rx_FSS_received_p_i : in std_logic;
rx_byte_ready_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_CRC_FES_ok_p_i : in std_logic;
tx_sending_mps_i : in std_logic;
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
var1_rdy_o: out std_logic;
var2_rdy_o: out std_logic;
var3_rdy_o: out std_logic;
tx_byte_ready_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
tx_data_length_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
reset_status_bytes_o : out std_logic;
reset_rx_unit_p_o : out std_logic;
var_o : out t_var
rx_byte_ready_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_CRC_FES_ok_p_i : in std_logic;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
tx_sending_mps_i : in std_logic;
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
var1_rdy_o: out std_logic;
var2_rdy_o: out std_logic;
var3_rdy_o: out std_logic;
tx_byte_ready_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
tx_data_length_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rst_status_bytes_o : out std_logic;
rst_rx_unit_p_o : out std_logic;
var_o : out t_var;
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic
);
end component wf_engine_control;
end component WF_engine_control;
---------------------------------------------------------------------------------------------------
component wf_reset_unit
generic(C_RSTIN_C_LGTH : integer := 4);
component WF_reset_unit
port (
uclk_i : in std_logic;
rsti_i : in std_logic;
var_i : in t_var;
subs_i : in std_logic_vector (7 downto 0);
rst_var_byte_1_i : in std_logic_vector (7 downto 0);
rst_var_byte_2_i : in std_logic_vector (7 downto 0);
uclk_i : in std_logic;
urst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
urst_r_edge_i : in std_logic;
var_i : in t_var;
subs_i : in std_logic_vector (7 downto 0);
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
rston_o : out std_logic;
nFIP_rst_o : out std_logic;
fd_rstn_o : out std_logic
rston_o : out std_logic;
nFIP_rst_o : out std_logic;
fd_rstn_o : out std_logic
);
end component wf_reset_unit;
end component WF_reset_unit;
---------------------------------------------------------------------------------------------------
component wf_DualClkRAM_clka_rd_clkb_wr
component WF_DualClkRAM_clka_rd_clkb_wr
generic (C_RAM_DATA_LGTH : integer;
C_RAM_ADDR_LGTH : integer);
......@@ -564,15 +580,15 @@ end component wf_slone_DATI_bytes_sampler;
data_A_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
);
end component wf_DualClkRAM_clka_rd_clkb_wr;
end component WF_DualClkRAM_clka_rd_clkb_wr;
---------------------------------------------------------------------------------------------------
component wf_crc
component WF_crc
generic (c_GENERATOR_POLY_length : natural := 16);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
start_CRC_p_i : in std_logic;
data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic;
......@@ -580,38 +596,38 @@ end component wf_slone_DATI_bytes_sampler;
CRC_ok_p : out std_logic;
CRC_o : out std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0)
);
end component wf_crc;
end component WF_crc;
---------------------------------------------------------------------------------------------------
component wf_manch_encoder is
component WF_manch_encoder is
generic(word_length : natural);
port (
word_i : in std_logic_vector(word_length-1 downto 0);
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0)
);
end component wf_manch_encoder;
end component WF_manch_encoder;
---------------------------------------------------------------------------------------------------
component wf_manch_code_viol_check is
component WF_manch_code_viol_check is
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
serial_input_signal_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
manch_code_viol_p_o : out std_logic
);
end component wf_manch_code_viol_check;
end component WF_manch_code_viol_check;
---------------------------------------------------------------------------------------------------
component wf_rx_deglitcher
component WF_rx_deglitcher
generic (C_ACULENGTH : integer := 10);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
......@@ -621,16 +637,16 @@ end component wf_manch_code_viol_check;
rxd_filtered_f_edge_p_o : out std_logic;
sample_bit_p_o : out std_logic
);
end component wf_rx_deglitcher;
end component WF_rx_deglitcher;
---------------------------------------------------------------------------------------------------
component wf_status_bytes_gen
component WF_status_bytes_gen
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic;
var1_acc_i : in std_logic;
......@@ -641,20 +657,20 @@ end component wf_manch_code_viol_check;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
crc_wrong_p_i : in std_logic;
reset_status_bytes_i : in std_logic;
rst_status_bytes_i : in std_logic;
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_status_byte_o : out std_logic_vector (7 downto 0)
);
end component wf_status_bytes_gen;
end component WF_status_bytes_gen;
---------------------------------------------------------------------------------------------------
component wf_bits_to_txd
component WF_bits_to_txd
generic (C_TXCLKBUFFLENTGTH : natural := 4);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
txd_bit_index_i : in unsigned(4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
......@@ -668,7 +684,7 @@ end component wf_manch_code_viol_check;
txd_o : out std_logic;
tx_enable_o : out std_logic
);
end component wf_bits_to_txd;
end component WF_bits_to_txd;
---------------------------------------------------------------------------------------------------
......@@ -715,11 +731,11 @@ end component wf_bits_to_txd;
---------------------------------------------------------------------------------------------------
component wf_model_constr_decoder
component WF_model_constr_decoder
generic (C_RELOAD_MID_CID : natural);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
......@@ -727,14 +743,14 @@ component wf_model_constr_decoder
m_id_dec_o : out std_logic_vector (7 downto 0);
c_id_dec_o : out std_logic_vector (7 downto 0)
);
end component wf_model_constr_decoder;
end component WF_model_constr_decoder;
---------------------------------------------------------------------------------------------------
component wf_decr_counter is
component WF_decr_counter is
generic(counter_length : natural := 5);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
nFIP_urst_i : in std_logic;
counter_top : in unsigned (counter_length-1 downto 0);
counter_load_i : in std_logic;
counter_decr_p_i : in std_logic;
......@@ -742,26 +758,27 @@ component wf_decr_counter is
counter_o : out unsigned (counter_length-1 downto 0);
counter_is_zero_o : out std_logic
);
end component wf_decr_counter;
end component WF_decr_counter;
---------------------------------------------------------------------------------------------------
component wf_incr_counter is
component WF_incr_counter is
generic(counter_length : natural := 8);
port (
uclk_i : in std_logic;
nFIP_u_rst_i : in std_logic;
reset_counter_i : in std_logic;
incr_counter_i: in std_logic;
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
reinit_counter_i : in std_logic;
incr_counter_i: in std_logic;
counter_o : out unsigned(counter_length-1 downto 0)
counter_o : out unsigned(counter_length-1 downto 0);
counter_is_full_o : out std_logic
);
end component wf_incr_counter;
end component WF_incr_counter;
---------------------------------------------------------------------------------------------------
component wf_prod_data_lgth_calc is
component WF_prod_data_lgth_calc is
port (
slone_i : in std_logic;
nostat_i : in std_logic;
......@@ -770,10 +787,10 @@ component wf_prod_data_lgth_calc is
tx_data_length_o : out std_logic_vector(7 downto 0)
);
end component wf_prod_data_lgth_calc;
end component WF_prod_data_lgth_calc;
---------------------------------------------------------------------------------------------------
component wf_cons_frame_validator is
component WF_cons_frame_validator is
port (
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
......@@ -785,31 +802,34 @@ component wf_cons_frame_validator is
cons_frame_ok_p_o : out std_logic
);
end component wf_cons_frame_validator;
end component WF_cons_frame_validator;
---------------------------------------------------------------------------------------------------
component wf_VAR_RDY_generator is
component WF_VAR_RDY_generator is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nFIP_u_rst_i : in std_logic;
cons_frame_ok_p_i : in std_logic;
var_i : in t_var;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nFIP_urst_i : in std_logic;
cons_frame_ok_p_i : in std_logic;
var_i : in t_var;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic
);
end component wf_VAR_RDY_generator;
end component WF_VAR_RDY_generator;
end wf_package;
package body wf_package is
end wf_package;
end WF_package;
package body WF_package is
end WF_package;
--=================================================================================================
-- package end
--=================================================================================================
......
wf_prod_bytes_to_tx.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_prod_bytes_to_tx.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_prod_bytes_to_tx.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_prod_bytes_to_tx --
-- WF_prod_bytes_to_tx --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -22,7 +22,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--
--! @brief After an id_dat frame requesting for a variable to be produced, this unit provides
--! to the transmitter (wf_tx) one by one, \n all the bytes of data needed for the
--! to the transmitter (WF_tx) one by one, \n all the bytes of data needed for the
--! rp_dat frame (apart from fss, fcs and fes bytes).
--
--
......@@ -39,7 +39,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! wf_status_bytes_gen \n
--! WF_status_bytes_gen \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -51,8 +51,8 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! -> egousiou: subs_i is not sent in the rp_dat frames \n
--! -> egousiou: signal s_wb_we includes the wb_stb_r_edge_p_i \n
--! -> egousiou: signal s_mem_byte was not in sensitivity list in v0.01! by adding it,
--! changes were essential in the timing of the tx (wf_osc, wf_tx,
--! wf_engine_control and the configuration of the memory needed few changes)
--! changes were essential in the timing of the tx (WF_osc, WF_tx,
--! WF_engine_control and the configuration of the memory needed few changes)
--
---------------------------------------------------------------------------------------------------
--
......@@ -63,20 +63,20 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_prod_bytes_to_tx
--! Entity declaration for WF_prod_bytes_to_tx
--=================================================================================================
entity wf_prod_bytes_to_tx is
entity WF_prod_bytes_to_tx is
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode
nostat_i : in std_logic; --! if negated, nFIP status is sent
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- User Interface WISHBONE Slave
......@@ -105,7 +105,7 @@ entity wf_prod_bytes_to_tx is
-- (buffered twice with uclk)
-- Signals from wf_engine_control
-- Signals from WF_engine_control
var_i : in t_var; --! variable received from id_dat
data_length_i: in std_logic_vector (7 downto 0); --! # bytes of Conrol&Data fields of rp_dat
......@@ -121,33 +121,33 @@ entity wf_prod_bytes_to_tx is
-- includes rp_dat.Control and rp_dat.Data
var3_rdy_i : in std_logic;
-- Signals from wf_status_bytes_gen
-- Signals from WF_status_bytes_gen
nFIP_status_byte_i : in std_logic_vector (7 downto 0); --! nanoFIP status byte
mps_status_byte_i : in std_logic_vector (7 downto 0); --! MPS status byte
-- Signals from the wf_model_constr_decoder unit
-- Signals from the WF_model_constr_decoder unit
m_id_dec_i : in std_logic_vector (7 downto 0); --! model identification settings (decoded)
c_id_dec_i : in std_logic_vector (7 downto 0); --! constructor id settings (decoded)
-- OUTPUTS
-- Signal to wf_status_bytes_gen
-- Signal to WF_status_bytes_gen
sending_mps_o : out std_logic; --!indication: mps byte being sent
-- Signal to wf_tx
-- Signal to WF_tx
byte_o : out std_logic_vector (7 downto 0); --! output byte to be serialized and sent
-- nanoFIP output
wb_ack_prod_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe signal
);
end entity wf_prod_bytes_to_tx;
end entity WF_prod_bytes_to_tx;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_prod_bytes_to_tx is
architecture rtl of WF_prod_bytes_to_tx is
signal s_wb_ack_prod_p : std_logic;
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
......@@ -168,9 +168,9 @@ architecture rtl of wf_prod_bytes_to_tx is
--! on the stand-alone operation. The sampling takes place on the 1st clock cycle after the
--! VAR3_RDY has been deasserted.
Slone_Data_Sampler: wf_slone_DATI_bytes_sampler
Slone_Data_Sampler: WF_slone_DATI_bytes_sampler
port map( uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
slone_data_i => slone_data_i,
var3_rdy_i => var3_rdy_i,
byte_index_i => byte_index_i,
......@@ -180,7 +180,7 @@ architecture rtl of wf_prod_bytes_to_tx is
---------------------------------------------------------------------------------------------------
-- !@brief Instantiation of a "Produced ram"
production_dpram: wf_DualClkRAM_clka_rd_clkb_wr
production_dpram: WF_DualClkRAM_clka_rd_clkb_wr
generic map (C_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
C_RAM_ADDR_LGTH => 9) -- 2^9: depth of produced ram
......@@ -204,9 +204,9 @@ architecture rtl of wf_prod_bytes_to_tx is
--! fields of an rp_dat frame:\n If the variable requested in the id_dat is of "produced" type(id/
--! presence/ var3) the process prepares accordingly, one by one, bytes of data to be sent. \n The
--! pointer "byte_index_i" indicates which byte of the frame is to be sent. Some of the bytes are
--! defined in the wf_package, the rest come either from the memory (if slone=0) or from the the
--! input bus data_i or from the wf_status_gen or wf_model_constr_decoder units.\n
--! The output byte "byte_o" is sent to the transmitter(wf_tx)for serialization
--! defined in the WF_package, the rest come either from the memory (if slone=0) or from the the
--! input bus data_i or from the WF_status_gen or WF_model_constr_decoder units.\n
--! The output byte "byte_o" is sent to the transmitter(WF_tx)for serialization
Bytes_Generation: process (var_i, s_byte_index, data_length_i, c_id_dec_i, m_id_dec_i,
nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_length,
......@@ -222,9 +222,9 @@ architecture rtl of wf_prod_bytes_to_tx is
-- case: presence variable
-- all the bytes for the rp_dat.Control and rp_dat.Data fields of the rp_dat frame to be sent,
-- are predefined in the c_VARS_ARRAY(0).byte_array matrix
when presence_var =>
when var_presence =>
byte_o <= c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).byte_array(s_byte_index_aux);
byte_o <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).byte_array(s_byte_index_aux);
s_base_addr <= (others => '0');
sending_mps_o <= '0';
......@@ -234,9 +234,9 @@ architecture rtl of wf_prod_bytes_to_tx is
--case: identification variable
-- The Constructor and Model bytes of the identification variable arrive from the decoding unit
-- (wf_model_constr_decoder), wereas all the rest are predefined in the c_VARS_ARRAY matrix
-- (WF_model_constr_decoder), wereas all the rest are predefined in the c_VARS_ARRAY matrix
when identif_var =>
when var_identif =>
if s_byte_index = c_CONSTR_BYTE_INDEX then
byte_o <= c_id_dec_i;
......@@ -245,7 +245,7 @@ architecture rtl of wf_prod_bytes_to_tx is
byte_o <= m_id_dec_i;
else
byte_o <= c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).byte_array(s_byte_index_aux);
byte_o <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).byte_array(s_byte_index_aux);
end if;
s_base_addr <= (others => '0');
......@@ -257,7 +257,7 @@ architecture rtl of wf_prod_bytes_to_tx is
-- case: variable 3 (06h)
-- For a var3 there is a separation according to the operational mode (stand-alone or memory)
-- In general, few of the bytes are predefined in the c_VARS_ARRAY matrix, wereas the rest come
-- either from the memory or from the data_i bus or from status_generator unit (wf_status_gen)
-- either from the memory or from the data_i bus or from status_generator unit (WF_status_gen)
when var_3 =>
......@@ -269,7 +269,7 @@ architecture rtl of wf_prod_bytes_to_tx is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (rp_dat.Control) and second (PDU type) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the wf_package
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux);
......@@ -312,7 +312,7 @@ architecture rtl of wf_prod_bytes_to_tx is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (rp_dat.Control) and second (PDU type) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the wf_package
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less equal than
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux);
......@@ -377,7 +377,7 @@ architecture rtl of wf_prod_bytes_to_tx is
---------------------------------------------------------------------------------------------------
-- auxiliary signals generation:
-- address of the byte to be read from memory: base_address(from wf_package) + byte_index_i - 1
-- address of the byte to be read from memory: base_address(from WF_package) + byte_index_i - 1
-- (the -1 is because when byte_index_i is on the 4th byte (control, pdu and length have
-- preceeded and a byte from the memory is now requested), the 3rd byte from the memory has to
-- be retrieved (in cell 00000010) etc)
......@@ -416,14 +416,14 @@ architecture rtl of wf_prod_bytes_to_tx is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! synchronous process Delay_index_offset_i: in the combinatorial process Bytes_Generation,
--! according to the value of the signal s_byte_index, a byte is retrieved either from the memory,
--! or from the wf_package or from the wf_status_bytes_gen or dec_m_ids units.
--! or from the WF_package or from the WF_status_bytes_gen or dec_m_ids units.
--! Since the memory needs one clock cycle to output its data the signal s_byte_index has to be a
--! delayed version of the byte_index_i (byte_index_i is the signal used as address for the mem)
Delay_index_offset_i: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_byte_index <= (others=> '0');
else
......
wf_prod_data_lgth_calc.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_prod_data_lgth_calc.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_prod_data_lgth_calc.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_prod_data_lgth_calc --
-- WF_prod_data_lgth_calc --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -57,32 +57,32 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_prod_data_lgth_calc
--! Entity declaration for WF_prod_data_lgth_calc
--=================================================================================================
entity wf_prod_data_lgth_calc is
entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
-- Signals from wf_engine_control
-- Signals from WF_engine_control
var_i: in t_var;
-- OUTPUT
-- Signal to wf_engine_control
-- Signal to WF_engine_control
tx_data_length_o : out std_logic_vector(7 downto 0)
);
end entity wf_prod_data_lgth_calc;
end entity WF_prod_data_lgth_calc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_prod_data_lgth_calc is
architecture rtl of WF_prod_data_lgth_calc is
signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
--=================================================================================================
......@@ -93,7 +93,7 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
--!@brief:Combinatorial process data_length_calcul: calculation of the total amount of data
--! bytes that have to be transferreed when a variable is produced, including the rp_dat.Control as
--! well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes. In the case of the presence
--! and the identification variables, the data length is predefined in the wf_package.
--! and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation.
data_length_calcul: process ( var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i )
......@@ -106,15 +106,15 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when presence_var =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
s_tx_data_length <= c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).array_length;
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when identif_var =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
s_tx_data_length <= c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).array_length;
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......@@ -160,7 +160,7 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
when var_2 =>
s_tx_data_length <= (others => '0');
when reset_var =>
when var_rst =>
s_tx_data_length <= (others => '0');
when others =>
......
wf_reset_unit.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_reset_unit.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_reset_unit.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -15,13 +15,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_reset_unit --
-- WF_reset_unit --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: wf_reset_unit
-- unit name: WF_reset_unit
--
--! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset
--! and user interface reset (RSTON)
......@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details
--
--! \n<b>Dependencies:</b>\n
--! wf_cons_bytes_from_rx\n
--! WF_cons_bytes_from_rx\n
--
--
--! \n<b>Modified by:</b>\n
......@@ -64,49 +64,45 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_reset_unit
--! Entity declaration for WF_reset_unit
--=================================================================================================
entity wf_reset_unit is
generic (C_RSTIN_C_LGTH : integer := 3); --! rstin counter length
entity WF_reset_unit is
port (
-- INPUTS
-- User Interface general signals
uclk_i : in std_logic; --! 40 MHz clock
rsti_i : in std_logic; --! initialisation control, active low
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
-- User Interface general signals (synchronized) (after synchronization)
uclk_i : in std_logic; --! 40 MHz clock
urst_i : in std_logic; --! initialisation control, active low
urst_r_edge_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
rate_i : in std_logic_vector (1 downto 0);
-- Signal from the central control unit wf_engine_control
var_i : in t_var; --! variable type
-- Signals from the wf_cons_bytes_from_rx unit
rst_var_byte_1_i : in std_logic_vector (7 downto 0);
rst_var_byte_2_i : in std_logic_vector (7 downto 0);
-- Signal from the central control unit WF_engine_control
var_i : in t_var; --! variable type
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
-- OUTPUTS
-- nanoFIP internal reset
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
-- nanoFIP output to the User Interface
rston_o : out std_logic; --! reset output, active low
rston_o : out std_logic; --! reset output, active low
-- nanoFIP output to FIELDRIVE
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
);
end entity wf_reset_unit;
end entity WF_reset_unit;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_reset_unit is
architecture rtl of WF_reset_unit is
signal s_rst, s_reset_nFIP_and_FD, s_reset_RSTON : std_logic;
signal s_rstin_c : unsigned(C_RSTIN_C_LGTH downto 0)
:= (others=>'0'); -- init for simulation
signal s_rst : std_logic;
signal s_rstin_c : unsigned(4 downto 0) := (others=>'0');
-- counter init for simulation purpuses
--=================================================================================================
......@@ -115,27 +111,27 @@ architecture rtl of wf_reset_unit is
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process s_rst_creation: the process follows the input signal rstin
--! and confirms that it stays active for more than 2^(C_RSTIN_C_LGTH-1) uclk cycles;
--! If so, it enables the signal s_rst to follow it.
--!@brief Synchronous process s_rst_creation: the process follows the (buffered) input signal rstin
--! and confirms that it stays active for more than 16 uclk cycles;
--! if so, it enables the signal s_rst to follow it.
s_rst_creation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if (rsti_i = '1') then -- when the rstin in ON
if (s_rstin_c(s_rstin_c'left) = '0') then -- counter counts until 2^(C_RSTIN_C_LGTH-1)
s_rstin_c <= s_rstin_c+1; -- then stays at 2^(C_RSTIN_C_LGTH-1)
if (urst_i = '1') then -- when the rstin in ON
if (s_rstin_c(s_rstin_c'left) = '0') then -- counter counts until 16 (then stays at 16)
s_rstin_c <= s_rstin_c+1;
end if;
else -- when the reset is OFF
s_rstin_c <= (others => '0'); -- counter reinitialized
s_rstin_c <= (others => '0'); -- counter reinitialised
end if;
-------------------------------------------------
if (s_rstin_c(s_rstin_c'left) = '1') then -- if rstin was ON for > 2^(C_RSTIN_C_LGTH-1)
s_rst <= rsti_i; -- uclk ticks, the s_rst starts following rstin
if (s_rstin_c(s_rstin_c'left) = '1') then -- if rstin was ON for at least 16 uclk ticks
s_rst <= urst_i; -- the signal s_rst starts following rstin
else
s_rst <= '0'; -- otherwise it stays to 0
......@@ -147,42 +143,6 @@ end process;
---------------------------------------------------------------------------------------------------
--!@ brief: Generation of the signals s_reset_nFIP_and_FD: signals that the 1st byte of a consumed
--! reset var contains the station address
--! and s_reset_RSTON: signals that the 2nd byte of a consumed
--! reset var contains the station address
Reset_Signals: process (uclk_i)
begin
if rising_edge(uclk_i) then
if s_rst = '1' then
s_reset_nFIP_and_FD <= '0';
s_reset_RSTON <= '0';
else
if var_i = reset_var then
if rst_var_byte_1_i = subs_i then
s_reset_nFIP_and_FD <= '1'; -- reset_nFIP_and_FD_o stays asserted until
end if; -- the end of the current rp_dat frame
if rst_var_byte_2_i = subs_i then
s_reset_RSTON <= '1'; -- reset_RSTON_o stays asserted until
end if; -- the end of the current rp_dat frame
else
s_reset_nFIP_and_FD <= '0';
s_reset_RSTON <= '0';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Reset_Outputs: definitions of the three reset outputs:
--! rston_o: user interface reset, active low; active when a reset variable is received and the 2nd
......@@ -201,15 +161,16 @@ end process;
begin
if rising_edge(uclk_i) then
rston_o <= not s_reset_RSTON;
nFIP_rst_o <= s_rst or s_reset_nFIP_and_FD;
fd_rstn_o <= not (s_rst or s_reset_nFIP_and_FD);
rston_o <= not assert_RSTON_p_i;
nFIP_rst_o <= s_rst or rst_nFIP_and_FD_p_i;
fd_rstn_o <= not (s_rst or rst_nFIP_and_FD_p_i);
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_rx.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_rx.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,15 +22,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_rx --
-- --
-- CERN, BE/CO/HT --
-- WF_rx --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief De-serialization of the input signal fd_rxd and construction of bytes of data
--! to be provided to the wf_cons_bytes_from_rx unit.
--! to be provided to the WF_cons_bytes_from_rx unit.
--
--! Remark: We refer to a significant edge for an edge of a Manchester 2 (manch.)
--! encoded bit (eg: bit0: _|-, bit 1: -|_) and to a transition between adjacent bits
......@@ -47,11 +53,11 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! wf_reset_unit \n
--! wf_rx_tx_osc \n
--! wf_deglitcher \n
--! wf_engine_control \n
--! wf_inputs_synchronizer\n
--! WF_reset_unit \n
--! WF_rx_tx_osc \n
--! WF_deglitcher \n
--! WF_engine_control \n
--! WF_inputs_synchronizer\n
--
--
--! \n<b>Modified by:</b>\n
......@@ -64,9 +70,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n\n<b>Last changes:</b>\n
--! -> 09/2009 v0.01 PS First version \n
--! -> 10/2010 v0.02 EG state switch_to_deglitched added;
--! output signal wait_rxd_first_f_edge_o added; signals renamed;
--! output signal rst_rx_osc_o added; signals renamed;
--! state machine rewritten (mealy style);
--! units wf_manch_code_viol_check and Incoming_Bits_Index created;
--! units WF_manch_code_viol_check and Incoming_Bits_Index created;
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
--! code cleaned-up + commented.\n
--
---------------------------------------------------------------------------------------------------
......@@ -85,66 +92,66 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_rx
--! Entity declaration for WF_rx
--=================================================================================================
entity wf_rx is
entity WF_rx is
port (
-- INPUTS
-- User interface general signal
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the wf_engine_control
reset_rx_unit_p_i : in std_logic; --! signals that more bytes than expected are being
--! received (ex: ID_DAT > 8 bytes etc) and the unit
--! has to be reset
-- Signal from the WF_engine_control
rst_rx_unit_p_i : in std_logic; --! signals that more bytes than expected are being
--! received (ex: ID_DAT > 8 bytes etc) and the unit
--! has to be reset
-- Signals from the wf_rx_tx_osc
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
-- Signals from the WF_rx_tx_osc
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
-- Signals from wf_inputs_synchronizer
rxd_r_edge_i : in std_logic; --! indicates a rising edge on fd_rxd
rxd_f_edge_i : in std_logic; --! indicates a falling edge on fd_rxd
-- Signals from WF_inputs_synchronizer
rxd_r_edge_i : in std_logic; --! indicates a rising edge on fd_rxd
rxd_f_edge_i : in std_logic; --! indicates a falling edge on fd_rxd
-- Signals from the wf_deglitcher
rxd_filtered_o : in std_logic; --! deglitched fd_rxd
rxd_filtered_f_edge_p_i : in std_logic; --! falling edge on the deglitched fd_rxd
sample_manch_bit_p_i : in std_logic; --! pulse indicating a valid sampling time for a manch. bit
sample_bit_p_i : in std_logic; --! pulse indicating a valid sampling time for a bit
-- Signals from the WF_deglitcher
rxd_filtered_o : in std_logic; --! deglitched fd_rxd
rxd_filtered_f_edge_p_i : in std_logic; --! falling edge on the deglitched fd_rxd
sample_manch_bit_p_i : in std_logic; --! pulse indicating a valid sampling time for a manch. bit
sample_bit_p_i : in std_logic; --! pulse indicating a valid sampling time for a bit
-- OUTPUTS
-- Signals to the wf_consumed and wf_engine_control
byte_o : out std_logic_vector (7 downto 0) ; --! retrieved data byte
byte_ready_p_o : out std_logic; --! pulse indicating a valid retrieved data byte
-- Signals to the wf_engine_control
FSS_CRC_FES_viol_ok_p_o : out std_logic; --! indication of a frame with a correct FSS,FES,CRC
--! and with no unexpected manch code violations
CRC_wrong_p_o : out std_logic; --! indication of a wrong CRC reception
FSS_received_p_o : out std_logic; --! indication of a correct FSS reception
-- Signal to the wf_rx_tx_osc
wait_rxd_first_f_edge_o : out std_logic--! indication that wf_rx is in idle state
-- Signals to the WF_consumed and WF_engine_control
byte_o : out std_logic_vector (7 downto 0) ; --! retrieved data byte
byte_ready_p_o : out std_logic; --! pulse indicating a valid retrieved data byte
-- Signals to the WF_engine_control
FSS_CRC_FES_viol_ok_p_o : out std_logic; --! indication of a frame with a correct FSS,FES,CRC
--! and with no unexpected manch code violations
CRC_wrong_p_o : out std_logic; --! indication of a wrong CRC reception
FSS_received_p_o : out std_logic; --! indication of a correct FSS reception
-- Signal to the WF_rx_tx_osc
rst_rx_osc_o : out std_logic --! resets the clock recovery procedure of the rx_osc
);
end entity wf_rx;
end entity WF_rx;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_rx is
architecture rtl of WF_rx is
-- states of the receiver's state machine
type rx_st_t is (idle, preamble_field_first_fe, preamble_field_re, preamble_field_fe,
type rx_st_t is (idle, preamble_field_first_f_edge, preamble_field_r_edge,preamble_field_f_edge,
frame_start_field, switch_to_deglitched, data_field_byte);
signal rx_st, nx_rx_st : rx_st_t;
......@@ -175,7 +182,7 @@ architecture rtl of wf_rx is
--! for the detection of the the preamble, FSS and FES of a received id_dat or consumed
--! rp_dat frame, as well as for the formation of bytes of data.
--! The main outputs of the unit (byte_o and byte_ready_p_o) are the main inputs of the unit
--! wf_cons_bytes_from_rx.
--! WF_cons_bytes_from_rx.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
......@@ -183,7 +190,7 @@ architecture rtl of wf_rx is
Receiver_FSM_Sync: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
rx_st <= idle;
else
rx_st <= nx_rx_st;
......@@ -201,7 +208,7 @@ architecture rtl of wf_rx is
s_frame_start_wrong_bit, s_manch_f_edge, rx_st,
s_frame_end_detected_p, s_frame_end_wrong_bit,
rxd_f_edge_i, s_edge_outside_manch_window,
reset_rx_unit_p_i)
rst_rx_unit_p_i)
begin
nx_rx_st <= idle;
......@@ -213,36 +220,36 @@ architecture rtl of wf_rx is
when idle => -- in idle state until falling
if rxd_f_edge_i = '1' then -- edge detection
nx_rx_st <= preamble_field_first_fe;
nx_rx_st <= preamble_field_first_f_edge;
else
nx_rx_st <= idle;
end if;
when preamble_field_first_fe=>
when preamble_field_first_f_edge=>
if s_manch_r_edge = '1' then -- arrival of a manch.
nx_rx_st <= preamble_field_re; -- rising edge
nx_rx_st <= preamble_field_r_edge; -- rising edge
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= preamble_field_first_fe;
nx_rx_st <= preamble_field_first_f_edge;
end if;
when preamble_field_re =>
when preamble_field_r_edge =>
if s_manch_f_edge = '1' then -- arrival of a manch. falling edge
nx_rx_st <= preamble_field_fe; -- note: several loops between
nx_rx_st <= preamble_field_f_edge; -- note: several loops between
-- a rising and a falling edge are
-- expected for the preamble
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= preamble_field_re;
nx_rx_st <= preamble_field_r_edge;
end if;
when preamble_field_fe =>
when preamble_field_f_edge =>
if s_manch_r_edge = '1' then -- arrival of a manch. rising edge
nx_rx_st <= preamble_field_re;
nx_rx_st <= preamble_field_r_edge;
elsif s_bit_r_edge = '1' then -- arrival of a bit rising edge,
nx_rx_st <= switch_to_deglitched; -- signaling the beginning of the
-- first V+ violation
......@@ -250,11 +257,11 @@ architecture rtl of wf_rx is
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= preamble_field_fe;
nx_rx_st <= preamble_field_f_edge;
end if;
-- A small delay is expected between the rxd and the rxd_filtered (output of the
-- wf_rx_deglitcher) which means that the last falling edge of the preamble of rxd arrives
-- WF_rx_deglitcher) which means that the last falling edge of the preamble of rxd arrives
-- earlier than the one of the rxd_filtered. The state switch_to_deglitched is used for
-- this purpose.
......@@ -284,7 +291,7 @@ architecture rtl of wf_rx is
when data_field_byte =>
if s_frame_end_detected_p = '1' or reset_rx_unit_p_i = '1' then
if s_frame_end_detected_p = '1' or rst_rx_unit_p_i = '1' then
nx_rx_st <= idle;
elsif s_frame_end_wrong_bit = '1' and s_manch_code_viol_p = '1' then
......@@ -316,7 +323,7 @@ architecture rtl of wf_rx is
s_receiving_bytes <= '0';
when preamble_field_first_fe | preamble_field_re | preamble_field_fe =>
when preamble_field_first_f_edge | preamble_field_r_edge | preamble_field_f_edge =>
s_idle <= '0';
s_receiving_preamble <= '1';
......@@ -367,11 +374,11 @@ architecture rtl of wf_rx is
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a counter that manages the position of an incoming deglitched bit
--! inside a manch encoded byte (16 bits)
Incoming_Bits_Index: wf_decr_counter
Incoming_Bits_Index: WF_decr_counter
generic map(counter_length => 4)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_bit_index_p,
......@@ -441,7 +448,7 @@ architecture rtl of wf_rx is
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
byte_ready_p_o <='0';
s_byte <= (others => '0');
else
......@@ -463,11 +470,11 @@ architecture rtl of wf_rx is
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the CRC calculator unit
Check_CRC : wf_crc
Check_CRC : WF_crc
generic map(c_GENERATOR_POLY_length => 16)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
start_CRC_p_i => s_receiving_FSS,
data_bit_ready_p_i => s_write_bit_to_byte,
data_bit_i => rxd_filtered_o,
......@@ -476,10 +483,10 @@ architecture rtl of wf_rx is
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the unit that checks for code violations
Check_code_violations: wf_manch_code_viol_check
Check_code_violations: WF_manch_code_viol_check
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
serial_input_signal_i => rxd_filtered_o,
sample_bit_p_i => sample_bit_p_i,
sample_manch_bit_p_i => sample_manch_bit_p_i,
......@@ -495,7 +502,7 @@ architecture rtl of wf_rx is
CRC_Code_viol_signals: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_CRC_ok <= '0';
s_manch_code_violations <= '0';
......@@ -529,7 +536,7 @@ architecture rtl of wf_rx is
FES_Detector: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_frame_end_detection <= '1';
else
......@@ -555,7 +562,7 @@ architecture rtl of wf_rx is
---------------------------------------------------------------------------------------------------
-- output signals:
byte_o <= s_byte;
wait_rxd_first_f_edge_o <= s_idle;
rst_rx_osc_o <= s_idle;
FSS_received_p_o <= s_receiving_FSS and s_frame_start_last_bit;
CRC_wrong_p_o <= s_frame_end_detected_p and (not s_CRC_ok);
FSS_CRC_FES_viol_ok_p_o <= s_frame_end_detected_p and s_CRC_ok and (not s_manch_code_violations);
......
wf_rx_deglitcher.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_rx_deglitcher.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx_deglitcher.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
......@@ -12,9 +20,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- wf_rx_deglitcher --
-- --
-- CERN, BE/CO/HT --
-- WF_rx_deglitcher --
-- --
---------------------------------------------------------------------------------------------------
--
......@@ -24,7 +30,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- @date 08/2010
......@@ -36,8 +42,8 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details
--
--! \n<b>Dependencies:</b>\n
--! wf_osc \n
--! wf_reset_unit \n
--! WF_osc \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -59,10 +65,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
--! Entity declaration for wf_deglitcher
--! Entity declaration for WF_deglitcher
--=================================================================================================
entity wf_rx_deglitcher is
entity WF_rx_deglitcher is
generic (C_ACULENGTH : integer := 10);
port(
......@@ -70,31 +76,31 @@ entity wf_rx_deglitcher is
-- User interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- FIELDRIVE input signal
rxd_i : in std_logic; --! buffered fd_rxd
-- Signals from the wf_osc unit
-- Signals from the WF_osc unit
sample_bit_p_i : in std_logic; --! pulsed signal signaling a new bit
sample_manch_bit_p_i : in std_logic; --! pulsed signal signaling a new manchestered bit
-- OUTPUTS
-- Output signals needed for the receiverwf_rx
-- Output signals needed for the receiverWF_rx
sample_bit_p_o : out std_logic;
rxd_filtered_o : out std_logic;
rxd_filtered_f_edge_p_o : out std_logic;
sample_manch_bit_p_o : out std_logic
);
end wf_rx_deglitcher;
end WF_rx_deglitcher;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture Behavioral of wf_rx_deglitcher is
architecture Behavioral of WF_rx_deglitcher is
signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0);
signal s_rxd_filtered : std_logic;
......@@ -114,7 +120,7 @@ process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_count_ones_c <= (others =>'0');
else
......@@ -136,7 +142,7 @@ process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_rxd_filtered <= '0';
s_rxd_filtered_d <= '0';
else
......@@ -162,7 +168,7 @@ end process;
Detect_f_edge_rx_data_filtered: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_rxd_filtered_buff <= (others => '0');
rxd_filtered_f_edge_p_o <= '0';
else
......@@ -190,32 +196,3 @@ end Behavioral;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
wf_rx_tx_osc.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_rx_tx_osc.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx_tx_osc.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
......@@ -13,15 +21,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
---------------------------------------------------------------------------------------------------
-- --
-- wf_rx_tx_osc --
-- --
-- CERN, BE/CO/HT --
-- WF_rx_tx_osc --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name wf_rx_tx_osc
-- unit name WF_rx_tx_osc
--
--! @brief Generation the clock signals needed for the receiver(wf_rx)and transmiter(wf_tx)\n
--! @brief Generation the clock signals needed for the receiver(WF_rx)and transmiter(WF_tx)\n
--!
--! Concerning the reception, even if the bit rate of the communication is known, jitter
--! is expected to affect the arriving time of the incoming signal. The main idea of the
......@@ -55,9 +61,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--
--
--! \n<b>Dependencies:</b>\n
--! wf_reset_unit \n
--! wf_synchronizer\n
--! wf_rx \n
--! WF_reset_unit \n
--! WF_synchronizer\n
--! WF_rx \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -71,10 +77,11 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--! -> 07/2010 v0.02 EG tx, rx counter changed from 20 bits signed, to 11 bits unsigned;
--! rx clk generation depends on edge detection; code cleaned-up+commented
--! C_TXCLKBUFFLENTGTH got 1 bit more\n
--! rst_rx_osc signal clearified
--
---------------------------------------------------------------------------------------------------
--
--! @todo --> better use of the preamble (in case 1st edge detected does not belong to preamble)/!\
--! @todo -->
--
---------------------------------------------------------------------------------------------------
......@@ -86,33 +93,33 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--=================================================================================================
--! Entity declaration for wf_rx_tx_osc
--! Entity declaration for WF_rx_tx_osc
--=================================================================================================
entity wf_rx_tx_osc is
entity WF_rx_tx_osc is
generic (C_PERIODS_COUNTER_LENGTH : natural;
C_QUARTZ_PERIOD : real;
C_TXCLKBUFFLENTGTH : natural);
port (
-- INPUTS
-- User interface general signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! bit rate
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the wf_synchronizer
rxd_edge_i : in std_logic; --! indication of an edge on rxd_i
rxd_f_edge_i : in std_logic; --! indication of a falling edge on rxd_i
-- Signals from the WF_synchronizer
rxd_edge_i : in std_logic; --! indication of an edge on rxd_i
rxd_f_edge_i : in std_logic; --! indication of a falling edge on rxd_i
-- Signal from wf_rx
wait_rxd_first_f_edge_i : in std_logic; --! indication that wf_rx state machine is in idle,
--! waiting for the 1st falling edge of rxd_i
-- Signal from WF_rx
rst_rx_osc_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
-- OUTPUTS
-- Output signals needed in the reception
-- Outputs to wf_rx and wf_rx_deglitcher
-- Outputs to WF_rx and WF_rx_deglitcher
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! 1) on a significant edge
--! 2) between adjacent bits
......@@ -129,21 +136,22 @@ entity wf_rx_tx_osc is
-- Output signals needed in the transmission
-- nanoFIP output
tx_clk_o : out std_logic; --! line driver half bit clock
-- Output to the wf_tx
-- Output to the WF_tx
tx_clk_p_buff_o : out std_logic_vector (C_TXCLKBUFFLENTGTH -1 downto 0)
);
end entity wf_rx_tx_osc;
end entity WF_rx_tx_osc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_rx_tx_osc is
architecture rtl of WF_rx_tx_osc is
signal s_counter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_counter_rx, s_counter_tx : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_rx_counter, s_tx_counter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_period, s_jitter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_counter_full, s_half_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_one_forth_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
......@@ -162,8 +170,8 @@ architecture rtl of wf_rx_tx_osc is
--=================================================================================================
begin
s_period <= C_UCLK_TICKS(to_integer(unsigned(rate_i))); -- # uclock ticks for a period
s_half_period <= (s_period srl 1); -- s_period shifted 1 bit
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i))); -- # uclock ticks for a period
s_half_period <= s_period srl 1; -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
s_jitter <= s_period srl 3; -- jitter defined as 1/8 of
-- the period
......@@ -171,39 +179,45 @@ begin
---------------------------------------------------------------------------------------------------
-- synchronous rx_process periods_count:
-- the process is looking for the 1st falling edge of the serial input rxd_i; this should be
-- representing the 1st Manchester (manch.) encoded bit '1'of the preamble. Starting from this
-- edge, other falling or rising significant edges, are expected around one period later.
-- A time window around the expected arrival time is set and its length is defined as 1/4th of
-- the period (1/8th before and 1/8th after the expected time). When the actual edge arrives,
-- the counter resets.
-- rx_osc
---------------------------------------------------------------------------------------------------
-- Synchronous process rx_periods_count:
-- in this process the rx_counter stops being initialized after a falling edge of the rxd
-- (according to the signal rst_rx_osc_i from the WF_rx_unit); this edge should be representing
-- the 1st Manchester (manch.) encoded bit '1' of the preamble.
-- Starting from this edge, other falling or rising significant edges, are expected around one
-- period later. A time window around the expected arrival time is set and its length is defined
-- as 1/4th of the period (1/8th before and 1/8th after the expected time). When the actual edge
-- arrives, the counter resets.
-- If on the other hand, that edge is proven not to belong to a valid preambe, the signal
-- rst_rx_osc_i is re-enabled from the rx unit.
rx_periods_count: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
s_counter_rx <= (others => '0');
if nFIP_urst_i = '1' then
s_rx_counter <= (others => '0');
else
---------------------------------------------------------------------------------------------
-- counter initialized after the first falling edge of a new frame
if (wait_rxd_first_f_edge_i = '1' and rxd_f_edge_i = '1' ) then
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter re-initialization
if rst_rx_osc_i = '1' then
s_rx_counter <= (others => '0');
s_counter_rx <= (others => '0');
-- for the rest of the frame
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter counting
else
if (s_rxd_signif_edge_window = '1') and (rxd_edge_i ='1') then
s_counter_rx <= (others => '0'); -- when an edge appears inside
s_rx_counter <= (others => '0'); -- when an edge appears inside
-- the expected window, the
-- counter is reinitialized
elsif (s_counter_rx=s_counter_full) then -- otherwise, it continues counting
s_counter_rx <= (others => '0'); -- complete nominal periods
elsif (s_rx_counter=s_counter_full) then -- otherwise, it continues counting
s_rx_counter <= (others => '0'); -- complete nominal periods
else
s_counter_rx <= s_counter_rx + 1 ;
s_rx_counter <= s_rx_counter + 1 ;
end if;
end if;
......@@ -211,11 +225,11 @@ begin
end if;
end process;
--------------------------------------------------------------------------------------------------
-- concurrent signal assignments concerning the receiver:
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignments concerning the receiver:
--creation of the windows where significant edges and adjacent bits transitions are expected on the
-- input signal
-- reminder:in principle, s_counter_rx is initialized after the detection of a significant edge and
-- reminder:in principle, s_rx_counter is initialized after the detection of a significant edge and
-- it is counting a complete period, according to the bit rate.
-- s_rxd_signif_edge_window extends s_jitter uclk ticks before and s_jitter uclk ticks after the
......@@ -223,34 +237,34 @@ begin
-- s_rx_adjac_bits_window extends s_jitter uclk ticks before and s_jitter uclk ticks after the
-- middle of a period, where transitions between adjacent bits are expected
s_rxd_signif_edge_window <= '1' when ((s_counter_rx < s_jitter) or
(s_counter_rx > s_counter_full - s_jitter-1))
s_rxd_signif_edge_window <= '1' when ((s_rx_counter < s_jitter) or
(s_rx_counter > s_counter_full - s_jitter-1))
else '0';
s_rx_adjac_bits_window <= '1' when ((s_counter_rx >= s_half_period-s_jitter-1) and
(s_counter_rx < s_half_period+s_jitter))
s_rx_adjac_bits_window <= '1' when ((s_rx_counter >= s_half_period-s_jitter-1) and
(s_rx_counter < s_half_period+s_jitter))
else '0';
---------------------------------------------------------------------------------------------------
-- synchronous process rx_clk:
-- the process rx_clk is following the edges that appear on the input signal and constructs two
-- clock signals: rx_manch_clk and rx_bit_clk.
-- Synchronous process rx_clk:
-- the process rx_clk is following the edges that appear on the input signal and constructs two
-- clock signals: rx_manch_clk and rx_bit_clk.
-- In detail, the process is looking for moments:
-- 1) of significant edges
-- 2) between boundary bits
-- In detail, the process is looking for moments:
-- 1) of significant edges
-- 2) between boundary bits
-- the signal rx_manch_clk is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk is inverted only between adjacent bits
-- the signal rx_manch_clk is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk is inverted only between adjacent bits
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
rx_clk: process (uclk_i)
......@@ -258,7 +272,7 @@ begin
begin
if rising_edge(uclk_i) then
-- initializations:
if (nFIP_u_rst_i = '1') then
if (nFIP_urst_i = '1') then
s_rx_manch_clk <='0';
s_rx_bit_clk <='0';
s_rx_bit_clk_d1 <='0';
......@@ -276,7 +290,7 @@ begin
s_adjac_bits_edge_found <= '0';
end if;
elsif (s_signif_edge_found='0')and(s_counter_rx=s_jitter) then
elsif (s_signif_edge_found='0')and(s_rx_counter=s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk;
--if a significant edge is not found where
-- expected (code violation), the
......@@ -295,7 +309,7 @@ begin
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
elsif (s_adjac_bits_edge_found='0')and(s_counter_rx=s_half_period+s_jitter) then
elsif (s_adjac_bits_edge_found='0')and(s_rx_counter=s_half_period+s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk; -- if no edge occurs inside the
s_rx_bit_clk <= not s_rx_bit_clk; --adjac_bits_edge_window,both clks are
-- inverted right after the end of it
......@@ -318,28 +332,31 @@ begin
end if;
end process;
---------------------------------------------------------------------------------------------------
-- tx_osc
---------------------------------------------------------------------------------------------------
-- synchronous tx_process periods_count: implementation of a counter counting transmission periods.
-- Synchronous process tx_periods_count: implementation of a counter counting transmission periods.
tx_periods_count: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
s_counter_tx <= (others => '0');
if nFIP_urst_i = '1' then
s_tx_counter <= (others => '0');
s_tx_clk_d1 <= '0';
s_tx_clk_p_buff <= (others => '0');
else
-- free counter measuring transmission periods
if (s_counter_tx = s_counter_full) then
s_counter_tx <= (others => '0');
if (s_tx_counter = s_counter_full) then
s_tx_counter <= (others => '0');
else
s_counter_tx <= s_counter_tx + 1 ;
s_tx_counter <= s_tx_counter + 1 ;
end if;
-- clk signals:
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left -1 downto 0) & s_tx_clk_p; -- buffer
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left -1 downto 0) & s_tx_clk_p;--buffer
end if;
end if;
end process;
......@@ -348,8 +365,8 @@ begin
-- concurrent signal assignments concerning the transmitter:
-- creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_counter_tx < s_one_forth_period) or
((s_counter_tx > (2*s_one_forth_period)-1) and (s_counter_tx < 3*s_one_forth_period)))
s_tx_clk <= '1' when ((s_tx_counter < s_one_forth_period) or
((s_tx_counter > (2*s_one_forth_period)-1) and (s_tx_counter < 3*s_one_forth_period)))
else '0';
-- creation of a pulse starting 1 uclk period before s_tx_clk_o (s_tx_clk_d1)
......
wf_slone_DATI_bytes_sampler.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_slone_DATI_bytes_sampler.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_slone_DATI_bytes_sampler.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_slone_DATI_bytes_sampler --
-- WF_slone_DATI_bytes_sampler --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -57,40 +57,40 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_slone_DATI_bytes_sampler
--! Entity declaration for WF_slone_DATI_bytes_sampler
--=================================================================================================
entity wf_slone_DATI_bytes_sampler is
entity WF_slone_DATI_bytes_sampler is
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- User Interface Non WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- (triply buffered with uclk)
-- Signals from wf_engine_control
-- Signals from WF_engine_control
var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- includes rp_dat.Control and rp_dat.Data
-- OUTPUTS
-- Signal to wf_prod_bytes_to_tx
-- Signal to WF_prod_bytes_to_tx
slone_byte_o : out std_logic_vector (7 downto 0)
);
end entity wf_slone_DATI_bytes_sampler;
end entity WF_slone_DATI_bytes_sampler;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_slone_DATI_bytes_sampler is
architecture rtl of WF_slone_DATI_bytes_sampler is
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
......@@ -109,7 +109,7 @@ architecture rtl of wf_slone_DATI_bytes_sampler is
Sample_Data_i: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0');
else
......
wf_slone_bytes_to_DATO.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_slone_bytes_to_DATO.vhd
--=================================================================================================
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_slone_bytes_to_DATO.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,9 +22,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_slone_bytes_to_DATO --
-- --
-- CERN, BE/CO/HT --
-- WF_slone_bytes_to_DATO --
-- --
---------------------------------------------------------------------------------------------------
--
......@@ -59,40 +65,38 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_slone_bytes_to_DATO
--! Entity declaration for WF_slone_bytes_to_DATO
--=================================================================================================
entity wf_slone_bytes_to_DATO is
entity WF_slone_bytes_to_DATO is
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from wf_cons_bytes_from_rx
-- Signals from WF_cons_bytes_from_rx
transfer_byte_p_i: in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_o(7:0)
--! 10: byte_i transfered to DAT_o(15:8)
-- Signals for the receiver wf_rx
-- Signals for the receiver WF_rx
byte_i : in std_logic_vector (7 downto 0); --! byte received from the rx unit
-- OUTPUTS
-- Signal to wf_prod_bytes_to_tx
-- Signal to WF_prod_bytes_to_tx
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
);
end entity wf_slone_bytes_to_DATO;
end entity WF_slone_bytes_to_DATO;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_slone_bytes_to_DATO is
architecture rtl of WF_slone_bytes_to_DATO is
--=================================================================================================
......@@ -109,7 +113,7 @@ architecture rtl of wf_slone_bytes_to_DATO is
Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization
else
......
wf_status_bytes_gen.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_status_bytes_gen.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_status_bytes_gen.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_status_bytes_generator --
-- WF_status_bytes_generator --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name wf_status_bytes_gen
-- unit name WF_status_bytes_gen
--
--
--! @brief Generation of the NanoFIP status, as well as the MPS status bytes.
......@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n<b>Dependencies:</b>\n
--! data_if \n
--! tx_engine \n
--! wf_tx_rx \n
--! WF_tx_rx \n
--! reset_logic \n
--
--
......@@ -65,18 +65,18 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
-- Entity declaration for wf_status_bytes_gen
-- Entity declaration for WF_status_bytes_gen
--=================================================================================================
entity wf_status_bytes_gen is
entity WF_status_bytes_gen is
port (
-- INPUTS
-- User Interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! Stand-alone mode
-- Signal from the reset_logic unit
nFIP_u_rst_i : in std_logic; --! internal reset
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from the fieldrive interface
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
......@@ -87,10 +87,10 @@ port (
var2_acc_i : in std_logic; --! Variable 2 access (asynchronous)
var3_acc_i : in std_logic; --! Variable 3 access (asynchronous)
-- Signal from the receiver wf_rx
-- Signal from the receiver WF_rx
crc_wrong_p_i : in std_logic;
-- Signals from the central control unit wf_engine_control
-- Signals from the central control unit WF_engine_control
var_i : in t_var; --! variable type
var1_rdy_i : in std_logic; --! Variable 1 ready
var2_rdy_i : in std_logic; --! Variable 2 ready
......@@ -98,20 +98,20 @@ port (
-- Signal from nanofip
reset_status_bytes_i : in std_logic; --! both status bytes are reinitialized
rst_status_bytes_i : in std_logic; --! both status bytes are reinitialized
--! right after having been delivered
-- OUTPUTS
-- Output to wf_prod_bytes_to_tx
-- Output to WF_prod_bytes_to_tx
nFIP_status_byte_o : out std_logic_vector (7 downto 0); --! status byte
mps_status_byte_o : out std_logic_vector (7 downto 0) --! mps byte
);
end entity wf_status_bytes_gen;
end entity WF_status_bytes_gen;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_status_bytes_gen is
architecture rtl of WF_status_bytes_gen is
signal s_refreshment : std_logic;
......@@ -131,7 +131,7 @@ begin
if rising_edge(uclk_i) then
if ((nFIP_u_rst_i = '1') or (reset_status_bytes_i = '1')) then -- the byte is reinitialized
if ((nFIP_urst_i = '1') or (rst_status_bytes_i = '1')) then -- the byte is reinitialized
nFIP_status_byte_o <= (others => '0'); -- after having been delivered
else
......@@ -182,7 +182,7 @@ end process;
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' or reset_status_bytes_i = '1' then -- the bit is reinitialized
if nFIP_urst_i = '1' or rst_status_bytes_i = '1' then -- the bit is reinitialized
s_refreshment <= '0'; -- after having been delivered
else
......
wf_tx.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_tx.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_tx.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_tx --
-- WF_tx --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: wf_tx
-- unit name: WF_tx
--
--
--! @brief Serializes the WorldFIP data.
......@@ -38,10 +38,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! wf_engine \n
--! WF_engine \n
--! tx_engine \n
--! clk_gen \n
--! wf_reset_unit \n
--! WF_reset_unit \n
--! consumed_ram \n
--
--
......@@ -65,20 +65,20 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_tx_rx
--! Entity declaration for WF_tx_rx
--=================================================================================================
entity wf_tx is
entity WF_tx is
generic(C_TXCLKBUFFLENTGTH: natural);
port (
-- INPUTS
-- user interface general signals
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from the wf_engine_control
start_produce_p_i : in std_logic; --! indication that wf_engine_control is in prod_watchdog state
-- Signals from the WF_engine_control
start_produce_p_i : in std_logic; --! indication that WF_engine_control is in prod_watchdog state
-- a correct id_dat asking for a produced var has been
-- received and ............
......@@ -86,17 +86,17 @@ entity wf_tx is
last_byte_p_i : in std_logic; --! indication that it is the last byte of data
-- CRC bytes follow
-- Signals from the wf_prod_bytes_to_tx
-- Signals from the WF_prod_bytes_to_tx
byte_i : in std_logic_vector (7 downto 0);
--! data byte to be delivered
-- Signal from the wf_rx_tx_osc
-- Signal from the WF_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH-1 downto 0);
--! clk for transmission synchronization
-- OUTPUTS
-- Signal to wf_engine_control
-- Signal to WF_engine_control
request_byte_p_o : out std_logic;
-- nanoFIP output signals
......@@ -104,14 +104,14 @@ entity wf_tx is
tx_enable_o : out std_logic --! transmitter enable
);
end entity wf_tx;
end entity WF_tx;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_tx is
architecture rtl of WF_tx is
type tx_state_t is (idle, send_fss, send_data_byte, send_crc_bytes, send_queue, stop_transmission);
......@@ -161,7 +161,7 @@ begin
-- "idle state": signals initializations
-- jump to "send_fss" state after a pulse on the signal start_produce_p_i (controlled by the
-- wf_engine_control)
-- WF_engine_control)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_fss" state: delivery of the manchester encoded bits of the Frame Start Sequence (including
......@@ -176,7 +176,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_data_byte" state: delivery of manchester encoded bits of data that arrive from the
-- wf_prod_bytes_to_tx unit (byte_i), with the coordination of the wf_engine_control (byte_ready_p_i)
-- WF_prod_bytes_to_tx unit (byte_i), with the coordination of the WF_engine_control (byte_ready_p_i)
-- request of a new byte on tx_clk_p_buff (0) assertion (with s_bit_index = 0)
-- bit delivery after tx_clk_p_buff (1) assertion
-- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1))
......@@ -184,10 +184,10 @@ begin
-- (between 0 and 16 for each byte, until the
-- last_byte_p_i gives a pulse)
-- the first data byte from the wf_prod_bytes_to_tx unit is already available after the assertion of the
-- the first data byte from the WF_prod_bytes_to_tx unit is already available after the assertion of the
-- start_produce_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal
-- triggers the wf_control_engine to send a new address to the memory of the produced_vars unit (new
-- triggers the WF_control_engine to send a new address to the memory of the produced_vars unit (new
-- address available on tx_clk_p_buff (1)), which in turn will give an output one uclk cycle later
-- (on tx_clk_p_buff (2)), exactly on the assertion of the byte_ready_p_i. Finally the first bit of
-- this new byte starts being delivered after tx_clk_p_buff (3) assertion.
......@@ -217,7 +217,7 @@ begin
Transmitter_FSM_Sync: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
tx_state <= idle;
else
tx_state <= nx_tx_state;
......@@ -378,7 +378,7 @@ begin
---------------------------------------------------------------------------------------------------
--@brief Instantiation of a manchester encoder for a data byte (8 bits long)
data_byte_manc_encoder: wf_manch_encoder
data_byte_manc_encoder: WF_manch_encoder
generic map(word_length => 8)
port map(
word_i => s_byte,
......@@ -387,7 +387,7 @@ data_byte_manc_encoder: wf_manch_encoder
---------------------------------------------------------------------------------------------------
--@brief Instantiation of a manchester encoder for the CRC bytes (16 bits long)
crc_bytes_manc_encoder: wf_manch_encoder
crc_bytes_manc_encoder: WF_manch_encoder
generic map(word_length => 16)
port map(
word_i => s_crc_bytes,
......@@ -399,12 +399,12 @@ crc_bytes_manc_encoder: wf_manch_encoder
--!@brief CRC calculator
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the CRC unit
crc_generation: wf_crc
crc_generation: WF_crc
generic map(
c_GENERATOR_POLY_length => 16)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
start_CRC_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
......@@ -426,11 +426,11 @@ crc_bytes_manc_encoder: wf_manch_encoder
--! CRC or a FES byte.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a bits counter:
Outgoing_Bits_Index: wf_decr_counter
Outgoing_Bits_Index: WF_decr_counter
generic map(counter_length => 5)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_index_p,
......@@ -483,10 +483,10 @@ crc_bytes_manc_encoder: wf_manch_encoder
--!@brief Instantiation of the unit that according to the state of the FSM and the
--! bits index counter, outputs FSS, data, CRC or FES manchester encoded bits to the txd_o.
--! The unit also and manages the tx_enable_o signal.
bits_to_txd: wf_bits_to_txd
bits_to_txd: WF_bits_to_txd
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
......@@ -503,7 +503,7 @@ crc_bytes_manc_encoder: wf_manch_encoder
Input_Byte_Sampling: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then
if nFIP_urst_i = '1' then
s_byte <= (others => '0');
else
......@@ -521,7 +521,7 @@ Input_Byte_Sampling: process(uclk_i)
tx_data_o <= s_txd;
request_byte_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-4);
-- request for a new byte from the wf_prod_bytes_to_tx unit (passing from wf_engine_control)
-- request for a new byte from the WF_prod_bytes_to_tx unit (passing from WF_engine_control)
end architecture rtl;
......
wf_tx_rx.vhd
View file @ afec7029
--=================================================================================================
--! @file wf_tx_rx.vhd
--=================================================================================================
---------------------------------------------------------------------------------------------------
--! @file WF_tx_rx.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
-- --
-- wf_tx_rx --
-- WF_tx_rx --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: wf_tx_rx
-- unit name: WF_tx_rx
--
--! @brief Serializes and deserializes the WorldFIP data.
--!
......@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! On reception it depacketises the data and only presents the actual data
--! contents. It also verifies the FCS (Frame Checksum, CRC).\n
--! On transmission it packetises the data and adds the FCS.
--! The unit wf_rx_tx_osc recovers the carrier clock during
--! The unit WF_rx_tx_osc recovers the carrier clock during
--!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--
......@@ -39,10 +39,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details
--!
--! <b>Dependencies:</b>\n
--! wf_engine \n
--! WF_engine \n
--! tx_engine \n
--! clk_gen \n
--! wf_reset_unit \n
--! WF_reset_unit \n
--! consumed_ram \n
--!
--!
......@@ -64,14 +64,14 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for wf_tx_rx
--! Entity declaration for WF_tx_rx
--=================================================================================================
entity wf_tx_rx is
entity WF_tx_rx is
port (
uclk_i : in std_logic; --! User Clock
nFIP_u_rst_i : in std_logic;
reset_rx_unit_p_i : in std_logic;
nFIP_urst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
......@@ -92,14 +92,14 @@ entity wf_tx_rx is
FSS_CRC_FES_viol_ok_p_o : out std_logic
);
end entity wf_tx_rx;
end entity WF_tx_rx;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of wf_tx_rx is
architecture rtl of WF_tx_rx is
signal s_d_filtered, s_first_fe : std_logic;
signal s_rx_data_filtered_f_edge_p : std_logic;
......@@ -114,11 +114,11 @@ architecture rtl of wf_tx_rx is
begin
---------------------------------------------------------------------------------------------------
tx: wf_tx
tx: WF_tx
generic map(C_TXCLKBUFFLENTGTH => C_TXCLKBUFFLENTGTH)
PORT MAP(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
start_produce_p_i => start_produce_p_i,
byte_ready_p_i => byte_ready_p_i,
byte_i => byte_i,
......@@ -130,11 +130,11 @@ begin
);
---------------------------------------------------------------------------------------------------
rx: wf_rx
rx: WF_rx
PORT MAP(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
reset_rx_unit_p_i => reset_rx_unit_p_i,
nFIP_urst_i => nFIP_urst_i,
rst_rx_unit_p_i => rst_rx_unit_p_i,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
......@@ -146,25 +146,25 @@ begin
byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o,
FSS_CRC_FES_viol_ok_p_o => FSS_CRC_FES_viol_ok_p_o,
wait_rxd_first_f_edge_o => s_first_fe,
rst_rx_osc_o => s_first_fe,
FSS_received_p_o => FSS_received_p_o,
CRC_wrong_p_o => CRC_wrong_p_o
);
---------------------------------------------------------------------------------------------------
rx_tx_osc :wf_rx_tx_osc
generic map(C_PERIODS_COUNTER_LENGTH => C_PERIODS_COUNTER_LENGTH,
C_QUARTZ_PERIOD => C_QUARTZ_PERIOD,
C_TXCLKBUFFLENTGTH => C_TXCLKBUFFLENTGTH)
rx_tx_osc :WF_rx_tx_osc
generic map(C_PERIODS_COUNTER_LENGTH => 11,
C_QUARTZ_PERIOD => 24.8,
C_TXCLKBUFFLENTGTH => 4)
port map(
uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
rxd_edge_i => fd_rxd_edge_i,
rxd_f_edge_i => fd_rxd_f_edge_i,
wait_rxd_first_f_edge_i => s_first_fe,
rst_rx_osc_i => s_first_fe,
rate_i => rate_i,
tx_clk_p_buff_o => s_clk_fixed_carrier_p_d,
tx_clk_o => d_clk_o,
......@@ -175,10 +175,10 @@ begin
);
---------------------------------------------------------------------------------------------------
deglitcher : wf_rx_deglitcher
deglitcher : WF_rx_deglitcher
generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i,
nFIP_urst_i => nFIP_urst_i,
rxd_i => fd_rxd,
sample_bit_p_i => s_rx_bit_clk_p,
sample_manch_bit_p_i => s_rx_manch_clk_p,
......
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