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nanoFIP - Gateware
Commit b35a6d7a authored by palvarez's avatar palvarez
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Wishbone seems ok... 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@30 7f0067c9-7624-46c7-bd39-3fb5400c0213
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DualClkRAM.vhd
View file @ b35a6d7a
-- Version: 8.6 SP1 8.6.1.3
-------------------------------------------------------------------------------
--! @file DualClkRAM.vhd
-------------------------------------------------------------------------------
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- --
-- CERN, BE --
-- --
-------------------------------------------------------------------------------
--
-- unit name: dpblockram.vhd
--
--! @brief The DualClkRAM instantiates a template for a true dual port ram clocked on both ports by different clocks. The architecture RAM4K9 instantiates the same Proasic3 component.
--!
--!
--! @author <Pablo Alvarez(pablo.alvarez.sanchez@cern.ch)>
--
--! @date 24\01\2009
--
--! @version 1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--!
--!
--! <b>References:</b>\n
--! <reference one> \n
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 24\01\2009 paas header included\n
--! <extended description>
-------------------------------------------------------------------------------
--! @todo Adapt vhdl sintax to ohr standard\n
--! <another thing to do> \n
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -15,7 +62,7 @@ entity DualClkRAM is
end DualClkRAM;
architecture DEF_ARCH of DualClkRAM is
architecture RAM4K9 of DualClkRAM is
component RAM4K9
generic (MEMORYFILE:string := "");
......@@ -75,4 +122,4 @@ architecture DEF_ARCH of DualClkRAM is
DOUTB(6), DOUTB5 => DOUTB(5), DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3), DOUTB2 => DOUTB(2), DOUTB1 =>
DOUTB(1), DOUTB0 => DOUTB(0));
end DEF_ARCH;
\ No newline at end of file
end RAM4K9;
\ No newline at end of file
NanoFip.pdc
View file @ b35a6d7a
......@@ -3,7 +3,7 @@
# Version: 8.6 SP1 8.6.1.3
# Family: ProASIC3 , Die: A3P400 , Package: 144 FBGA
# Date generated: Fri Feb 19 17:54:33 2010
# Date generated: Thu Apr 08 16:39:17 2010
#
......@@ -105,6 +105,12 @@ set_io {c_id_i[3]} \
-DIRECTION Input
set_io cyc_i \
-pinname C2 \
-fixed yes \
-DIRECTION Input
set_io {dat_i[0]} \
-pinname H2 \
-fixed yes \
......@@ -574,6 +580,7 @@ set_io we_i \
# set_io {c_id_i[1]} -pinname D8 -fixed yes -DIRECTION Input
# set_io {c_id_i[2]} -pinname D9 -fixed yes -DIRECTION Input
# set_io {c_id_i[3]} -pinname G9 -fixed yes -DIRECTION Input
# set_io cyc_i -pinname C2 -fixed yes -DIRECTION Input
# set_io {dat_i[0]} -pinname H2 -fixed yes -DIRECTION Input
# set_io {dat_i[1]} -pinname H3 -fixed yes -DIRECTION Input
# set_io {dat_i[2]} -pinname H4 -fixed yes -DIRECTION Input
......@@ -600,7 +607,7 @@ set_io we_i \
# set_io {dat_o[7]} -pinname J6 -fixed yes -DIRECTION Output
# set_io {dat_o[8]} -pinname H6 -fixed yes -DIRECTION Output
# set_io {dat_o[9]} -pinname G1 -fixed yes -DIRECTION Output
# set_io {dat_o[10]} -pinname G4 -fixed yes -DIRECTION Output
# set_io {dat_o[10]} -pinname K8 -fixed yes -DIRECTION Output
# set_io {dat_o[11]} -pinname F1 -fixed yes -DIRECTION Output
# set_io {dat_o[12]} -pinname F3 -fixed yes -DIRECTION Output
# set_io {dat_o[13]} -pinname F4 -fixed yes -DIRECTION Output
......@@ -611,7 +618,7 @@ set_io we_i \
# set_io fd_txena_o -pinname E11 -fixed yes -DIRECTION Output
# set_io fd_txer_i -pinname G11 -fixed yes -DIRECTION Input
# set_io fd_wdgn_i -pinname F11 -fixed yes -DIRECTION Input
# set_io fx_rxa_i -pinname F12 -fixed yes -DIRECTION Input
# set_io fx_rxa_i -pinname K12 -fixed yes -DIRECTION Input
# set_io fx_rxd_i -pinname E12 -fixed yes -DIRECTION Input
# set_io fx_txd_o -pinname G12 -fixed yes -DIRECTION Output
# set_io {m_id_i[0]} -pinname C9 -fixed yes -DIRECTION Input
......@@ -639,12 +646,12 @@ set_io we_i \
# set_io {subs_i[5]} -pinname B10 -fixed yes -DIRECTION Input
# set_io {subs_i[6]} -pinname A10 -fixed yes -DIRECTION Input
# set_io {subs_i[7]} -pinname A11 -fixed yes -DIRECTION Input
# set_io uclk_i -pinname C2 -fixed yes -DIRECTION Input
# set_io uclk_i -pinname F12 -fixed yes -DIRECTION Input
# set_io var1_acc_i -pinname C1 -fixed yes -DIRECTION Input
# set_io var1_rdy_o -pinname D5 -fixed yes -DIRECTION Output
# set_io var2_acc_i -pinname D1 -fixed yes -DIRECTION Input
# set_io var2_rdy_o -pinname D3 -fixed yes -DIRECTION Output
# set_io var3_acc_i -pinname D4 -fixed yes -DIRECTION Input
# set_io var3_rdy_o -pinname D2 -fixed yes -DIRECTION Output
# set_io wclk_i -pinname L3 -fixed yes -DIRECTION Input
# set_io wclk_i -pinname G4 -fixed yes -DIRECTION Input
# set_io we_i -pinname L7 -fixed yes -DIRECTION Input
deglitcher.vhd
View file @ b35a6d7a
......@@ -46,8 +46,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--! Pablo Alvarez Sanchez
--! Author: Pablo Alvarez Sanchez
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/08/2009 v0.02 PAAS Entity Ports added, start of architecture content
......
dpblockram_clka_rd_clkb_wr_syn.vhd
View file @ b35a6d7a
......@@ -35,7 +35,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: <name>
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 24\01\2009 paas header included\n
......@@ -77,10 +77,14 @@ end component DualClkRam;
signal s_zeros_da : std_logic_vector(7 downto 0);
signal zero : std_logic;
signal one : std_logic;
signal s_rw : std_logic;
begin
s_zeros_da <= (others => '0');
zero <= '0';
one <= '1';
s_rw <= not web_i;
UDualClkRam : DualClkRam
port map ( DINA => s_zeros_da,
DOUTA => da_o,
......@@ -88,13 +92,13 @@ UDualClkRam : DualClkRam
DOUTB => open,
ADDRA => aa_i,
ADDRB => ab_i,
RWA => zero,
RWB => web_i,
RWA => one,
RWB => s_rw,
BLKA => zero,
BLKB => zero,
CLKA => clka_i,
CLKB => clkb_i,
RESET => zero) ;
RESET => one) ;
end syn;
\ No newline at end of file
nanofip.vhd
View file @ b35a6d7a
--===========================================================================
--! @file nanofip.vhd
--! @brief Top level design file of nanofip
--===========================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
use work.wf_package.all;
library synplify;
-------------------------------------------------------------------------------
-- --
-- nanofip --
-- --
-- CERN, BE/CO/HT --
-- --
-------------------------------------------------------------------------------
--
-- unit name: nanofip (nanofip / nanofip)
--
--! @mainpage NanoFIP
--! <HR>
--! @section intro_sec Introduction
--! The NanoFIP is an FPGA component implementing the WorldFIP protocol that
--! can be used in field devices able to communicate at the three standard
--! speeds. The NanoFIP, that is developed as part of the WorldFIP insourcing
--! project, is designed to be radiation tolerant by using different single
--! event upset mitigation techniques such as triple module redundancy. \n\n
--! The NanoFIP design is to be implemented in an Actel ProASIC3 Flash family
--! FPGA that is supposedly to not loose its configuration or have serious
--! total dose effects or latchup problems. SEE still exists but should not
--! give any problems because of SEE mitigation techniques used in the NanoFIP
--! design. \n
--! \n
--! The device is used in conjunction with a FielDrive driver chip and FieldTR
--! insulating transformer, both available from the company ALSTOM.
--!
--! <HR>
--! @section more_sec More information
--! This design is based on the <em>NanoFIP functional specification v1.2</em>
--! http://www.ohwr.org/twiki/pub/OHR/CernFIP/WP3/cernfip_fspec1_2.pdf
--!
--! Complete information about this project at
--! http://www.ohwr.org/twiki/bin/view/OHR/CernFIP/ \n\n
--!
--! <HR>
--! @image html nanofip_image_1s.gif "Block diagram of the NanoFIP design"
--!
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
--
--! @date 07/07/2009
--
--! @version v0.1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--!
--!
--! <b>References:</b>\n
--!
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 30/06/2009 v0.010 EB First version \n
--! 06/07/2009 v0.011 EB Dummy blocks \n
--! 07/07/2009 v0.011 EB Comments \n
--!
-------------------------------------------------------------------------------
--! @todo Create entity \n
--
-------------------------------------------------------------------------------
--! @brief Top level design file of nanofip
--============================================================================
--============================================================================
--! Entity declaration for nanofip
--============================================================================
--============================================================================
entity nanofip is
port (
-------------------------------------------------------------------------------
-- WorldFIP settings
-------------------------------------------------------------------------------
--! Bit rate \n
--! 00: 31.25 kbit/s \n
--! 01: 1 Mbit/s \n
--! 10: 2.5 Mbit/s \n
--! 11: reserved, do not use
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
--! Subscriber number coding. Station address.
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Identification selection (see M_ID, C_ID)
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
--! Produced variable data length \n
--! 000: 2 Bytes \n
--! 001: 8 Bytes \n
--! 010: 16 Bytes \n
--! 011: 32 Bytes \n
--! 100: 64 Bytes \n
--! 101: 124 Bytes \n
--! 110: reserved, do not use \n
--! 111: reserved, do not use \n
--! Actual size: +1 NanoFIP Status byte +1 MPS Status byte (last transmitted)
--! Note: when SLONE=Vcc, p3_lgth_i should be set to 000.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-------------------------------------------------------------------------------
-- FIELDRIVE connections
-------------------------------------------------------------------------------
fd_rstn_o : out std_logic; --! Initialisation control, active low
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
-------------------------------------------------------------------------------
-- USER INTERFACE, General signals
-------------------------------------------------------------------------------
uclk_i : in std_logic; --! 40 MHz clock
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
rstin_i : in std_logic; --! Initialisation control, active low
--! Reset output, active low. Active when the reset variable is received
--! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_o: out std_logic; --! Variable 1 ready
--! Signals that the user logic is accessing variable 1. Only used to
--! generate a status that verifies that VAR1_RDY was high when
--! accessing. May be grounded.
var1_acc_i: in std_logic; --! Variable 1 access
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_o: out std_logic; --! Variable 2 ready
--! Signals that the user logic is accessing variable 2. Only used to
--! generate a status that verifies that VAR2_RDY was high when
--! accessing. May be grounded.
var2_acc_i: in std_logic; --! Variable 2 access
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o: out std_logic; --! Variable 3 ready
--! Signals that the user logic is accessing variable 3. Only used to
--! generate a status that verifies that VAR3_RDY was high when
--! accessing. May be grounded.
var3_acc_i: in std_logic; --! Variable 3 access
-- dummy_o : out std_logic;
-------------------------------------------------------------------------------
-- USER INTERFACE, WISHBONE SLAVE
-------------------------------------------------------------------------------
wclk_i : in std_logic; --! Wishbone clock. May be independent of UCLK.
--! Data in. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_i : in std_logic_vector (15 downto 0); --! Data in
--! Data out. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_o : out std_logic_vector (15 downto 0); --! Data out
-- dat_i : in std_logic_vector(15 downto 0);
adr_i : in std_logic_vector ( 9 downto 0); --! Address
rst_i : in std_logic; --! Wishbone reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
ack_o : out std_logic; --! Acknowledge
we_i : in std_logic --! Write enable
);
-- attribute syn_insert_buffer : string;
--attribute syn_insert_buffer of wclk_i : signal is "GL25";
end entity nanofip;
--============================================================================
-- end of entity declaration
--============================================================================
--============================================================================
--============================================================================
--! architecture declaration for nanofip
--============================================================================
--============================================================================
--! Architecture contains only connectivity
architecture struc of nanofip is
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of struc: architecture is "tmr";
component CLKBUF
port (PAD : in std_logic;
Y : out std_logic);
end component;
signal s_append_status_from_control : std_logic;
signal s_data_length_from_control : std_logic_vector(6 downto 0);
signal s_byte_to_tx : std_logic_vector(7 downto 0);
signal s_rst : std_logic;
signal s_start_send_p : std_logic;
signal s_request_byte_from_tx_p : std_logic;
signal s_byte_to_tx_ready_p : std_logic;
signal s_last_byte_to_tx_p, s_last_byte_from_rx_p : std_logic;
signal s_byte_from_rx_ready_p : std_logic;
signal s_byte_from_rx : std_logic_vector(7 downto 0);
signal s_cons_byte_we_from_control : std_logic;
signal s_var_from_control : t_var;
signal s_add_offset_from_control : std_logic_vector(6 downto 0);
signal addr_from_wb : std_logic_vector(9 downto 0);
signal s_crc_ok_from_rx : std_logic;
signal fss_decoded_p_from_rx : std_logic;
--signal frame_ok_from_rx : std_logic;
signal s_stat : std_logic_vector(7 downto 0);
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_stat_sent_p, s_sending_stat: std_logic;
signal s_mps_sent_p, s_sending_mps: std_logic;
signal s_code_violation_p : std_logic;
signal s_crc_bad_p : std_logic;
-- signal s_crc_ok_from_rx : std_logic;
signal s_var1_rdy : std_logic;
signal s_var2_rdy : std_logic;
signal s_var3_rdy : std_logic;
-- signal s_var1_access_wb_clk : std_logic;
-- signal s_var2_access_wb_clk : std_logic;
-- signal s_var3_access_wb_clk : std_logic;
-- signal s_reset_var1_access : std_logic;
-- signal s_reset_var2_access : std_logic;
-- signal s_reset_var3_access : std_logic;
--signal s_stat : std_logic_vector(7 downto 0);
signal s_mps : std_logic_vector(7 downto 0);
signal s_wb_d : std_logic_vector(15 downto 0);
signal s_long_dummy_reg : std_logic_vector(1000 downto 0);
-- signal s_wclk : std_logic;
begin
ureset_logic : reset_logic
port map(
uclk_i => uclk_i,
rstin_i => rstin_i,
rston_o => rston_o,
var_i => s_var_from_control,
rst_o => s_rst
);
uwf_tx_rx : wf_tx_rx
port map(
uclk_i => uclk_i,
rst_i => s_rst,
start_send_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p,
byte_i => s_byte_to_tx,
last_byte_p_i => s_last_byte_to_tx_p,
-- clk_fixed_carrier_p_o : out std_logic;
d_o => fx_txd_o,
d_e_o => fd_txena_o,
d_clk_o => fd_txck_o,
d_a_i => fx_rxd_i,
rate_i => rate_i,
byte_ready_p_o => s_byte_from_rx_ready_p,
byte_o => s_byte_from_rx,
fss_decoded_p_o => fss_decoded_p_from_rx, -- The frame decoder has detected the start of a frame
last_byte_p_o => s_last_byte_from_rx_p,
code_violation_p_o => s_code_violation_p,
crc_bad_p_o => s_crc_bad_p,
crc_ok_p_o => s_crc_ok_from_rx
);
uwf_engine_control : wf_engine_control
generic map( C_QUARTZ_PERIOD => 25.0)
port map(
uclk_i => uclk_i, --! User Clock
rst_i => s_rst,
-- Transmiter interface
start_send_p_o => s_start_send_p ,
request_byte_p_i => s_request_byte_from_tx_p,
byte_ready_p_o => s_byte_to_tx_ready_p,
-- byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o => s_last_byte_to_tx_p,
-- Receiver interface
fss_decoded_p_i => fss_decoded_p_from_rx, -- The frame decoder has detected the start of a frame
byte_ready_p_i => s_byte_from_rx_ready_p, -- The frame docoder ouputs a new byte on byte_i
byte_i => s_byte_from_rx, -- Decoded byte
frame_ok_p_i => s_crc_ok_from_rx,
-- Worldfip bit rate
rate_i => rate_i,
subs_i => subs_i, --! Subscriber number coding.
p3_lgth_i => p3_lgth_i, --! Produced variable data length
slone_i => slone_i, --! Stand-alone mode
nostat_i => nostat_i, --! No NanoFIP status transmission
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
var1_rdy_o => s_var1_rdy, --! Variable 1 ready
var2_rdy_o => s_var2_rdy, --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o => s_var3_rdy, --! Variable 3 ready
-- prod_byte_i : in std_logic_vector(7 downto 0);
var_o => s_var_from_control,
append_status_o => s_append_status_from_control,
add_offset_o => s_add_offset_from_control,
data_length_o => s_data_length_from_control,
cons_byte_we_p_o => s_cons_byte_we_from_control
);
var1_rdy_o <= s_var1_rdy; --! Variable 1 ready
var2_rdy_o <= s_var2_rdy; --! Variable 2 ready
var3_rdy_o <= s_var3_rdy; --! Variable 3 ready
uwf_consumed_vars : wf_consumed_vars
port map(
uclk_i => uclk_i, --! User Clock
rst_i => s_rst,
slone_i => slone_i, --! Stand-alone mode
byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control,
add_offset_i => s_add_offset_from_control,
byte_i => s_byte_from_rx,
-- var1_access_wb_clk_o => s_var1_access_wb_clk,
-- var2_access_wb_clk_o => s_var2_access_wb_clk,
-- reset_var1_access_i => s_reset_var1_access,
-- reset_var2_access_i => s_reset_var2_access,
wb_clk_i => wclk_i,
wb_dat_o => dat_o,
wb_adr_i => adr_i,
wb_stb_p_i => stb_i,
wb_ack_p_o => s_ack_consumed,
wb_we_p_i => we_i
);
uwf_produced_vars : wf_produced_vars
port map(
uclk_i => uclk_i, --! User Clock
rst_i => s_rst,
m_id_i => m_id_i, --! Model identification settings
c_id_i => c_id_i, --! Constructor identification settings
slone_i => slone_i, --! Stand-alone mode
nostat_i => nostat_i, --! No NanoFIP status transmission
subs_i => subs_i,
sending_stat_o => s_sending_stat, --! The status register is being adressed
sending_mps_o => s_sending_mps, --! The status register is being adressed
stat_i => s_stat, -- NanoFIP status
mps_i => s_mps,
-- var3_access_wb_clk_o => s_var3_access_wb_clk,
-- reset_var3_access_i => s_reset_var3_access,
var_i => s_var_from_control,
append_status_i => s_append_status_from_control,
add_offset_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
byte_o => s_byte_to_tx,
-------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i
-------------------------------------------------------------------------------
wb_dat_i => s_wb_d,
wb_clk_i => wclk_i,
wb_adr_i => adr_i,
wb_stb_p_i => stb_i,
wb_ack_p_o => s_ack_produced,
wb_we_p_i => we_i
);
ack_o <= (s_ack_produced or s_ack_consumed) and stb_i;
ustatus_gen : status_gen
port map(
uclk_i => uclk_i,
rst_i => s_rst,
fd_wdgn_i => fd_wdgn_i,
fd_txer_i => fd_txer_i,
code_violation_p_i => s_code_violation_p,
crc_bad_p_i => s_crc_bad_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
-- reset_var1_access_o => s_reset_var1_access,
-- reset_var2_access_o => s_reset_var2_access,
-- reset_var3_access_o => s_reset_var3_access,
stat_sent_p_i => s_stat_sent_p,
mps_sent_p_i => s_mps_sent_p,
stat_o => s_stat,
mps_o => s_mps
);
s_ack_o <= s_ack_produced or s_ack_consumed;
s_stat_sent_p <= s_sending_stat and s_byte_to_tx_ready_p; --! The status register is being adressed
s_mps_sent_p <= s_sending_stat and s_byte_to_tx_ready_p; --! The status register is being adressed
fd_rstn_o <= '1';
s_id_o <= "0" & fx_rxa_i; -- I connect fx_rxa_i to s_id_o just to test the pinout
--UCLKBUF : CLKBUF
-- port map(
-- PAD => wclk_i,
-- Y => s_wclk);
process(wclk_i)
begin
if rising_edge(wclk_i) then
if rst_i = '1' then
s_wb_d <= (others => '0');
s_long_dummy_reg <= (others => '0');
else
s_wb_d <= dat_i;
s_long_dummy_reg <= s_long_dummy_reg(s_long_dummy_reg'left - 1 downto 0) & fx_rxa_i;
end if;
end if;
end process;
--dummy_o <= s_long_dummy_reg(s_long_dummy_reg'left);
end architecture struc;
--============================================================================
--============================================================================
-- architecture end
--============================================================================
--============================================================================
-------------------------------------------------------------------------------
-- E N D O F F I L E
--===========================================================================
--! @file nanofip.vhd
--! @brief Top level design file of nanofip
--===========================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
use work.wf_package.all;
--syn_translate on
--library synplify;
--syn_translate off
-------------------------------------------------------------------------------
-- --
-- nanofip --
-- --
-- CERN, BE/CO/HT --
-- --
-------------------------------------------------------------------------------
--
-- unit name: nanofip (nanofip / nanofip)
--
--! @mainpage NanoFIP
--! <HR>
--! @section intro_sec Introduction
--! The NanoFIP is an FPGA component implementing the WorldFIP protocol that
--! can be used in field devices able to communicate at the three standard
--! speeds. The NanoFIP, that is developed as part of the WorldFIP insourcing
--! project, is designed to be radiation tolerant by using different single
--! event upset mitigation techniques such as triple module redundancy. \n\n
--! The NanoFIP design is to be implemented in an Actel ProASIC3 Flash family
--! FPGA that is supposedly to not loose its configuration or have serious
--! total dose effects or latchup problems. SEE still exists but should not
--! give any problems because of SEE mitigation techniques used in the NanoFIP
--! design. \n
--! \n
--! The device is used in conjunction with a FielDrive driver chip and FieldTR
--! insulating transformer, both available from the company ALSTOM.
--!
--! <HR>
--! @section more_sec More information
--! This design is based on the <em>NanoFIP functional specification v1.2</em>
--! http://www.ohwr.org/twiki/pub/OHR/CernFIP/WP3/cernfip_fspec1_2.pdf
--!
--! Complete information about this project at
--! http://www.ohwr.org/twiki/bin/view/OHR/CernFIP/ \n\n
--!
--! <HR>
--! @image html nanofip_image_1s.gif "Block diagram of the NanoFIP design"
--!
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--
--! @date 07/07/2009
--
--! @version v0.1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--!
--!
--! <b>References:</b>\n
--!
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 30/06/2009 v0.010 EB First version \n
--! 06/07/2009 v0.011 EB Dummy blocks \n
--! 07/07/2009 v0.011 EB Comments \n
--!
-------------------------------------------------------------------------------
--! @todo Create entity \n
--
-------------------------------------------------------------------------------
--! @brief Top level design file of nanofip
--============================================================================
--============================================================================
--! Entity declaration for nanofip
--============================================================================
--============================================================================
entity nanofip is
port (
-------------------------------------------------------------------------------
-- WorldFIP settings
-------------------------------------------------------------------------------
--! Bit rate \n
--! 00: 31.25 kbit/s \n
--! 01: 1 Mbit/s \n
--! 10: 2.5 Mbit/s \n
--! 11: reserved, do not use
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
--! Subscriber number coding. Station address.
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Identification selection (see M_ID, C_ID)
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
--! Produced variable data length \n
--! 000: 2 Bytes \n
--! 001: 8 Bytes \n
--! 010: 16 Bytes \n
--! 011: 32 Bytes \n
--! 100: 64 Bytes \n
--! 101: 124 Bytes \n
--! 110: reserved, do not use \n
--! 111: reserved, do not use \n
--! Actual size: +1 NanoFIP Status byte +1 MPS Status byte (last transmitted)
--! Note: when SLONE=Vcc, p3_lgth_i should be set to 000.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-------------------------------------------------------------------------------
-- FIELDRIVE connections
-------------------------------------------------------------------------------
fd_rstn_o : out std_logic; --! Initialisation control, active low
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
-------------------------------------------------------------------------------
-- USER INTERFACE, General signals
-------------------------------------------------------------------------------
uclk_i : in std_logic; --! 40 MHz clock
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
rstin_i : in std_logic; --! Initialisation control, active low
--! Reset output, active low. Active when the reset variable is received
--! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_o: out std_logic; --! Variable 1 ready
--! Signals that the user logic is accessing variable 1. Only used to
--! generate a status that verifies that VAR1_RDY was high when
--! accessing. May be grounded.
var1_acc_i: in std_logic; --! Variable 1 access
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_o: out std_logic; --! Variable 2 ready
--! Signals that the user logic is accessing variable 2. Only used to
--! generate a status that verifies that VAR2_RDY was high when
--! accessing. May be grounded.
var2_acc_i: in std_logic; --! Variable 2 access
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o: out std_logic; --! Variable 3 ready
--! Signals that the user logic is accessing variable 3. Only used to
--! generate a status that verifies that VAR3_RDY was high when
--! accessing. May be grounded.
var3_acc_i: in std_logic; --! Variable 3 access
-- dummy_o : out std_logic;
-------------------------------------------------------------------------------
-- USER INTERFACE, WISHBONE SLAVE
-------------------------------------------------------------------------------
wclk_i : in std_logic; --! Wishbone clock. May be independent of UCLK.
--! Data in. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_i : in std_logic_vector (15 downto 0); --! Data in
--! Data out. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_o : out std_logic_vector (15 downto 0); --! Data out
-- dat_i : in std_logic_vector(15 downto 0);
adr_i : in std_logic_vector ( 9 downto 0); --! Address
rst_i : in std_logic; --! Wishbone reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
ack_o : out std_logic; --! Acknowledge
cyc_i : in std_logic;
we_i : in std_logic --! Write enable
);
-- attribute syn_insert_buffer : string;
--attribute syn_insert_buffer of wclk_i : signal is "GL25";
end entity nanofip;
--============================================================================
-- end of entity declaration
--============================================================================
--============================================================================
--============================================================================
--! architecture declaration for nanofip
--============================================================================
--============================================================================
--! Architecture contains only connectivity
architecture struc of nanofip is
--syn_translate on
--attribute syn_radhardlevel : string;
--attribute syn_radhardlevel of struc: architecture is "tmr";
--syn_translate off
component CLKBUF
port (PAD : in std_logic;
Y : out std_logic);
end component;
signal s_append_status_from_control : std_logic;
signal s_data_length_from_control : std_logic_vector(6 downto 0);
signal s_byte_to_tx : std_logic_vector(7 downto 0);
signal s_rst : std_logic;
signal s_start_send_p : std_logic;
signal s_request_byte_from_tx_p : std_logic;
signal s_byte_to_tx_ready_p : std_logic;
signal s_last_byte_to_tx_p, s_last_byte_from_rx_p : std_logic;
signal s_byte_from_rx_ready_p : std_logic;
signal s_byte_from_rx : std_logic_vector(7 downto 0);
signal s_cons_byte_we_from_control : std_logic;
signal s_var_from_control : t_var;
signal s_add_offset_from_control : std_logic_vector(6 downto 0);
signal addr_from_wb : std_logic_vector(9 downto 0);
signal s_crc_ok_from_rx : std_logic;
signal fss_decoded_p_from_rx : std_logic;
--signal frame_ok_from_rx : std_logic;
signal s_stat : std_logic_vector(7 downto 0);
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_stat_sent_p, s_sending_stat: std_logic;
signal s_mps_sent_p, s_sending_mps: std_logic;
signal s_code_violation_p : std_logic;
signal s_crc_bad_p : std_logic;
-- signal s_crc_ok_from_rx : std_logic;
signal s_var1_rdy : std_logic;
signal s_var2_rdy : std_logic;
signal s_var3_rdy : std_logic;
-- signal s_var1_access_wb_clk : std_logic;
-- signal s_var2_access_wb_clk : std_logic;
-- signal s_var3_access_wb_clk : std_logic;
-- signal s_reset_var1_access : std_logic;
-- signal s_reset_var2_access : std_logic;
-- signal s_reset_var3_access : std_logic;
--signal s_stat : std_logic_vector(7 downto 0);
signal s_mps : std_logic_vector(7 downto 0);
signal s_wb_d_d : std_logic_vector(15 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector(7 downto 0);
signal s_stb_d, s_we_d : std_logic;
signal s_adr_d : std_logic_vector ( 9 downto 0); --! Address
begin
ureset_logic : reset_logic
port map(
uclk_i => uclk_i,
rstin_i => rstin_i,
rston_o => rston_o,
var_i => s_var_from_control,
rst_o => s_rst
);
uwf_tx_rx : wf_tx_rx
port map(
uclk_i => uclk_i,
rst_i => s_rst,
start_send_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p,
byte_i => s_byte_to_tx,
last_byte_p_i => s_last_byte_to_tx_p,
-- clk_fixed_carrier_p_o : out std_logic;
d_o => fx_txd_o,
d_e_o => fd_txena_o,
d_clk_o => fd_txck_o,
d_a_i => fx_rxd_i,
rate_i => rate_i,
byte_ready_p_o => s_byte_from_rx_ready_p,
byte_o => s_byte_from_rx,
fss_decoded_p_o => fss_decoded_p_from_rx, -- The frame decoder has detected the start of a frame
last_byte_p_o => s_last_byte_from_rx_p,
code_violation_p_o => s_code_violation_p,
crc_bad_p_o => s_crc_bad_p,
crc_ok_p_o => s_crc_ok_from_rx
);
uwf_engine_control : wf_engine_control
generic map( C_QUARTZ_PERIOD => 25.0)
port map(
uclk_i => uclk_i, --! User Clock
rst_i => s_rst,
-- Transmiter interface
start_send_p_o => s_start_send_p ,
request_byte_p_i => s_request_byte_from_tx_p,
byte_ready_p_o => s_byte_to_tx_ready_p,
-- byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o => s_last_byte_to_tx_p,
-- Receiver interface
fss_decoded_p_i => fss_decoded_p_from_rx, -- The frame decoder has detected the start of a frame
byte_ready_p_i => s_byte_from_rx_ready_p, -- The frame docoder ouputs a new byte on byte_i
byte_i => s_byte_from_rx, -- Decoded byte
frame_ok_p_i => s_crc_ok_from_rx,
-- Worldfip bit rate
rate_i => rate_i,
subs_i => subs_i, --! Subscriber number coding.
p3_lgth_i => p3_lgth_i, --! Produced variable data length
slone_i => slone_i, --! Stand-alone mode
nostat_i => nostat_i, --! No NanoFIP status transmission
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
var1_rdy_o => s_var1_rdy, --! Variable 1 ready
var2_rdy_o => s_var2_rdy, --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o => s_var3_rdy, --! Variable 3 ready
-- prod_byte_i : in std_logic_vector(7 downto 0);
var_o => s_var_from_control,
append_status_o => s_append_status_from_control,
add_offset_o => s_add_offset_from_control,
data_length_o => s_data_length_from_control,
cons_byte_we_p_o => s_cons_byte_we_from_control
);
var1_rdy_o <= s_var1_rdy; --! Variable 1 ready
var2_rdy_o <= s_var2_rdy; --! Variable 2 ready
var3_rdy_o <= s_var3_rdy; --! Variable 3 ready
uwf_consumed_vars : wf_consumed_vars
port map(
uclk_i => uclk_i, --! User Clock
rst_i => s_rst,
slone_i => slone_i, --! Stand-alone mode
byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control,
add_offset_i => s_add_offset_from_control,
byte_i => s_byte_from_rx,
-- var1_access_wb_clk_o => s_var1_access_wb_clk,
-- var2_access_wb_clk_o => s_var2_access_wb_clk,
-- reset_var1_access_i => s_reset_var1_access,
-- reset_var2_access_i => s_reset_var2_access,
wb_clk_i => wclk_i,
wb_dat_o => dat_o,
wb_adr_i => s_adr_d,
wb_stb_p_i => s_stb_d,
wb_ack_p_o => s_ack_consumed,
wb_we_p_i => s_we_d
);
uwf_produced_vars : wf_produced_vars
port map(
uclk_i => uclk_i, --! User Clock
rst_i => s_rst,
m_id_dec_i => s_m_id_dec_o, --! Model identification settings
c_id_dec_i => s_c_id_dec_o, --! Constructor identification settings
slone_i => slone_i, --! Stand-alone mode
nostat_i => nostat_i, --! No NanoFIP status transmission
subs_i => subs_i,
sending_stat_o => s_sending_stat, --! The status register is being adressed
sending_mps_o => s_sending_mps, --! The status register is being adressed
stat_i => s_stat, -- NanoFIP status
mps_i => s_mps,
-- var3_access_wb_clk_o => s_var3_access_wb_clk,
-- reset_var3_access_i => s_reset_var3_access,
var_i => s_var_from_control,
append_status_i => s_append_status_from_control,
add_offset_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
byte_o => s_byte_to_tx,
-------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i
-------------------------------------------------------------------------------
wb_dat_i => s_wb_d_d,
wb_clk_i => wclk_i,
wb_adr_i => s_adr_d,
wb_stb_p_i => s_stb_d,
wb_ack_p_o => s_ack_produced,
wb_we_p_i => s_we_d
);
ack_o <= (s_ack_produced or s_ack_consumed) and stb_i;
ustatus_gen : status_gen
port map(
uclk_i => uclk_i,
rst_i => s_rst,
fd_wdgn_i => fd_wdgn_i,
fd_txer_i => fd_txer_i,
code_violation_p_i => s_code_violation_p,
crc_bad_p_i => s_crc_bad_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
-- reset_var1_access_o => s_reset_var1_access,
-- reset_var2_access_o => s_reset_var2_access,
-- reset_var3_access_o => s_reset_var3_access,
stat_sent_p_i => s_stat_sent_p,
mps_sent_p_i => s_mps_sent_p,
stat_o => s_stat,
mps_o => s_mps
);
s_ack_o <= s_ack_produced or s_ack_consumed;
s_stat_sent_p <= s_sending_stat and s_byte_to_tx_ready_p; --! The status register is being adressed
s_mps_sent_p <= s_sending_stat and s_byte_to_tx_ready_p; --! The status register is being adressed
fd_rstn_o <= cyc_i and fx_rxa_i;
-- s_id_o <= "0" & fx_rxa_i; -- I connect fx_rxa_i to s_id_o just to test the pinout
Uwf_dec_m_ids : wf_dec_m_ids
port map(
uclk_i => uclk_i,
rst_i => s_rst,
s_id_o => s_id_o,
m_id_dec_o => s_m_id_dec_o,
c_id_dec_o => s_c_id_dec_o,
m_id_i => m_id_i,
c_id_i => c_id_i
);
--UCLKBUF : CLKBUF
-- port map(
-- PAD => wclk_i,
-- Y => s_wclk);
process(wclk_i)
begin
if rising_edge(wclk_i) then
if rst_i = '1' then
s_wb_d_d <= (others => '0');
s_stb_d <= '0';
s_we_d <= '0';
s_adr_d <= (others => '0');
else
s_wb_d_d <= dat_i;
s_stb_d <= stb_i;
s_we_d <= we_i;
s_adr_d <= adr_i;
end if;
end if;
end process;
end architecture struc;
--============================================================================
--============================================================================
-- architecture end
--============================================================================
--============================================================================
-------------------------------------------------------------------------------
-- E N D O F F I L E
-------------------------------------------------------------------------------
\ No newline at end of file
reset_logic.vhd
View file @ b35a6d7a
......@@ -43,7 +43,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--! Author:Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 EB First version \n
......
status_gen.vhd
View file @ b35a6d7a
......@@ -45,7 +45,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 EB First version \n
......
wf_consumed_vars.vhd
View file @ b35a6d7a
......@@ -45,7 +45,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author:
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 11/09/2009 v0.01 EB First version \n
......
wf_engine_control.vhd
View file @ b35a6d7a
......@@ -49,7 +49,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author:
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 11/09/2009 v0.01 EB First version \n
......
wf_package.vhd
View file @ b35a6d7a
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
package wf_package is
constant C_QUARTZ_PERIOD : real := 25.0;
type t_timeouts is
record
response : integer;
silence : integer;
end record;
constant c_31k25_rate_pos : integer := 0;
constant c_1M_rate_pos : integer := 1;
constant c_2M5_rate_pos : integer := 2;
constant c_11_rate_pos : integer := 3;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_timeouts_table : t_timeouts_table(0 to 3) := -- Time in ns
(c_31k25_rate_pos => (response => integer(640000.0/C_QUARTZ_PERIOD), silence => integer(5160000.0/C_QUARTZ_PERIOD)),
c_1M_rate_pos => (response => integer(10000.0/C_QUARTZ_PERIOD), silence => integer(150000.0/C_QUARTZ_PERIOD)),
c_2M5_rate_pos => (response => integer(16000.0/C_QUARTZ_PERIOD), silence => integer(100000.0/C_QUARTZ_PERIOD)),
c_11_rate_pos => (response => integer(640000.0/C_QUARTZ_PERIOD), silence => integer(5160000.0/C_QUARTZ_PERIOD))
);
type t_integer_array is array (natural range <>) of integer;
constant c_p3_var_length_table : t_integer_array(0 to 7) :=
(0 => 2, 1 => 8, 2 => 16, 3 => 32, 4 => 64, 5 => 124, others => 0);
constant c_id_dat : std_logic_vector(7 downto 0) := "00000011";
constant c_rp_dat : std_logic_vector(7 downto 0) := "00000010";
--constant c_var_presence : std_logic_vector(7 downto 0) := x"14";
--constant c_var_identification : std_logic_vector(7 downto 0) := x"10";
--constant c_var_1 : std_logic_vector(7 downto 0) := x"05";
--constant c_var_2 : std_logic_vector(7 downto 0) :=x"04";
--constant c_var_3 : std_logic_vector(7 downto 0) := x"06";
--constant c_var_reset : std_logic_vector(7 downto 0) := x"e0";
type t_var is (c_st_var_presence, c_st_var_identification, c_st_var_1, c_st_var_2, c_st_var_3, c_st_var_reset, c_st_var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
--constant c_pres_byte_array : t_byte_array(1 to 7) := (1 => x"50", 2 => x"05", 3 => x"80", 4 => x"03", 5 => x"00", 6 => x"f0", 7 => x"00");
--constant c_id_byte_array : t_byte_array(1 to 10) := (1 => x"52", 2 => x"08", 3 => x"01", 4 => x"00", 5 => x"00", 6 => x"f0", 7 => x"00", 8 => x"00", 9 => X"00", 10 => X"00");
--
type t_var_response is (produce, consume, reset);
type t_var_record is record
response : t_var_response;
hexvalue : std_logic_vector(7 downto 0);
var : t_var;
base_add : std_logic_vector(9 downto 0);
array_length : integer; --! -1 represents a variable length
byte_array : t_byte_array(0 to 15);
end record;
--
type t_var_array is array (natural range <>) of t_var_record;
constant c_var_length_add : integer := 3;
constant c_pdu_byte_add : integer := 2;
constant c_cons_byte_add : integer := 7;
constant c_model_byte_add : integer := 8;
constant c_var_presence_pos : integer := 0;
constant c_var_identification_pos : integer := 1;
constant c_var_var3_pos : integer := 2;
constant c_var_var1_pos : integer := 3;
constant c_var_var2_pos : integer := 4;
constant c_var_reset_pos : integer := 5;
constant c_byte_0_add : integer := 2;
constant c_byte_1_add : integer := 3;
constant c_var_array : t_var_array(0 to 5):=
(c_var_presence_pos => (var => c_st_var_presence,
hexvalue => x"14",
response => produce,
base_add => "----------",
array_length => 8,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"50", 3 => x"05", 4 => x"80", 5 => x"03", 6 => x"00",
7 => x"f0", 8 => x"00", others => x"ff")),
c_var_identification_pos => (var => c_st_var_identification,
hexvalue => x"10",
response => produce,
array_length => 11,
base_add => "----------",
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"52", 3 => x"08", 4 => x"01", 5 => x"00", 6 => x"00",
7 => x"f0", 8 => x"00", 9 => x"00", 10 => X"00", 11 => X"00",
others => x"ff")),
c_var_var3_pos => (var => c_st_var_3,
hexvalue => x"06",
response => produce,
base_add => "0000000000",
array_length => 3,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"40", others => x"ff")),
c_var_var1_pos => (var => c_st_var_1,
hexvalue => x"05",
response => consume,
base_add => "0000000000",
array_length => 8,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"50", 3 => x"05", 4 => x"80", 5 => x"03", 6 => x"00",
7 => x"f0", 8 => x"00", others => x"ff")),
c_var_var2_pos => (var => c_st_var_2,
hexvalue => x"04",
response => consume,
base_add => "0010000000",
array_length => 2,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"40", others => x"ff")),
c_var_reset_pos => (var => c_st_var_reset,
hexvalue => x"e0",
response => reset,
base_add => "0100000000",
array_length => 2,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"40", others => x"ff")));
--Status bit position
constant c_u_cacer_pos : integer := 2; --! Consumed variable access error
constant c_u_pacer_pos : integer := 3; --! Produced variable access error
constant c_r_bner_pos : integer := 4; --! Received bit number error. Replaced by code violation.
constant c_r_fcser_pos : integer := 5; --! Received FCS access error
constant c_t_txer_pos : integer := 6; --! Transmit error (FIELDDRIVE)
constant c_t_wder_pos : integer := 7; --! Watchdog error (FIELDDRIVE)
constant c_refreshment_pos : integer := 0; --! MPS refreshment bit
constant c_significance_pos : integer := 2; --! MPS significance bit
function calc_data_length(var : t_var;
p3_length : std_logic_vector(2 downto 0);
nostat : std_logic;
slone : std_logic) return std_logic_vector;
component wf_rx_osc
generic (C_OSC_LENGTH : integer := 20;
C_QUARTZ_PERIOD : real := 25.0;
C_CLKFCDLENTGTH : natural := 3
);
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
d_edge_i : in std_logic;
load_phase_i : in std_logic;
--! Bit rate \n
--! 00: 31.25 kbit/s => 62.5 KHz \n
--! 01: 1 Mbit/s => 2 MHz \n
--! 10: 2.5 Mbit/s => 5 MHz \n
--! 11: reserved, do not use
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
clk_fixed_carrier_p_o : out std_logic;
clk_fixed_carrier_p_d_o : out std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
clk_fixed_carrier_o : out std_logic;
clk_carrier_p_o : out std_logic;
clk_carrier_180_p_o : out std_logic;
clk_bit_p_o : out std_logic;
clk_bit_90_p_o : out std_logic;
clk_bit_180_p_o : out std_logic;
clk_bit_270_p_o : out std_logic;
edge_window_o : out std_logic;
edge_180_window_o : out std_logic;
phase_o : out std_logic_vector(C_OSC_LENGTH -1 downto 0)
);
end component wf_rx_osc;
component wf_crc
generic(
c_poly_length : natural := 16);
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
start_p_i : in std_logic;
d_i : in std_logic;
d_rdy_p_i : in std_logic;
data_fcs_sel_n : in std_logic;
crc_o : out std_logic_vector(c_poly_length - 1 downto 0);
crc_rdy_p_o : out std_logic;
crc_ok_p : out std_logic
);
end component wf_crc;
component deglitcher
Generic (C_ACULENGTH : integer := 10);
Port ( uclk_i : in STD_LOGIC;
d_i : in STD_LOGIC;
d_o : out STD_LOGIC;
carrier_p_i : in STD_LOGIC;
d_ready_p_o : out STD_LOGIC);
end component deglitcher;
component wf_rx
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic;
d_re_i : in std_logic;
d_fe_i : in std_logic;
d_filtered_i : in std_logic;
s_d_ready_p_i : in std_logic;
load_phase_o : out std_logic;
clk_bit_180_p_i : in std_logic;
edge_window_i : in std_logic;
edge_180_window_i : in std_logic
);
end component wf_rx;
component wf_tx
generic(
C_CLKFCDLENTGTH : natural := 3 );
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
start_send_p_i : in std_logic;
request_byte_p_o : out std_logic;
byte_ready_p_i : in std_logic; -- byte_ready_p_i is not used
byte_i : in std_logic_vector(7 downto 0);
last_byte_p_i : in std_logic;
-- clk_fixed_carrier_p_d_i(0) : in std_logic;
clk_fixed_carrier_p_d_i : in std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
d_o : out std_logic;
d_e_o : out std_logic
);
end component wf_tx;
component dpblockram_clka_rd_clkb_wr
generic (c_dl : integer := 42; -- Length of the data word
c_al : integer := 10); -- Number of words
-- 'nw' has to be coherent with 'c_al'
port (clka_i : in std_logic; -- Global Clock
aa_i : in std_logic_vector(c_al - 1 downto 0);
da_o : out std_logic_vector(c_dl -1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_al - 1 downto 0);
db_i : in std_logic_vector(c_dl - 1 downto 0);
web_i : in std_logic);
end component dpblockram_clka_rd_clkb_wr;
component wf_engine_control
generic( C_QUARTZ_PERIOD : real := 25.0);
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
-- Transmiter interface
start_send_p_o : out std_logic;
request_byte_p_i : in std_logic;
byte_ready_p_o : out std_logic;
-- byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
-- Receiver interface
fss_decoded_p_i : in std_logic; -- The frame decoder has detected the start of a frame
byte_ready_p_i : in std_logic; -- The frame docoder ouputs a new byte on byte_i
byte_i : in std_logic_vector(7 downto 0); -- Decoded byte
frame_ok_p_i : in std_logic;
-- Worldfip bit rate
rate_i : in std_logic_vector(1 downto 0);
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Produced variable data length \n
--! 000: 2 Bytes \n
--! 001: 8 Bytes \n
--! 010: 16 Bytes \n
--! 011: 32 Bytes \n
--! 100: 64 Bytes \n
--! 101: 124 Bytes \n
--! 110: reserved, do not use \n
--! 111: reserved, do not use \n
--! Actual size: +1 NanoFIP Status byte +1 MPS Status byte (last transmitted)
--! Note: when SLONE=Vcc, p3_lgth_i should be set to 000.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_o: out std_logic; --! Variable 1 ready
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_o: out std_logic; --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o: out std_logic; --! Variable 3 ready
-- prod_byte_i : in std_logic_vector(7 downto 0);
var_o : out t_var;
append_status_o : out std_logic;
add_offset_o : out std_logic_vector(6 downto 0);
data_length_o : out std_logic_vector(6 downto 0);
cons_byte_we_p_o : out std_logic
);
end component wf_engine_control;
component wf_consumed_vars
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
byte_ready_p_i : in std_logic;
var_i : in t_var;
-- append_status_i : in std_logic;
add_offset_i : in std_logic_vector(6 downto 0);
-- data_length_i : in std_logic_vector(6 downto 0);
byte_i : in std_logic_vector(7 downto 0);
-- var1_access_wb_clk_o: out std_logic; --! Variable 1 access flag
-- var2_access_wb_clk_o: out std_logic; --! Variable 2 access flag
-- reset_var1_access_i: in std_logic; --! Reset Variable 1 access flag
-- reset_var2_access_i: in std_logic; --! Reset Variable 2 access flag
-------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i
-------------------------------------------------------------------------------
-- dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
wb_dat_o : out std_logic_vector (15 downto 0); --!
wb_adr_i : in std_logic_vector (9 downto 0); --!
wb_stb_p_i : in std_logic; --! Strobe
wb_ack_p_o : out std_logic; --! Acknowledge
wb_we_p_i : in std_logic --! Write enable
);
end component wf_consumed_vars;
component wf_produced_vars is
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
--! Identification selection (see M_ID, C_ID)
-- s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
stat_i : in std_logic_vector(7 downto 0); --! NanoFIP status
mps_i : in std_logic_vector(7 downto 0);
sending_stat_o : out std_logic; --! The status register is being adressed
sending_mps_o : out std_logic; --! The status register is being adressed
-- var3_access_wb_clk_o: out std_logic; --! Variable 2 access flag
-- reset_var3_access_i: in std_logic; --! Reset Variable 1 access flag
-- prod_byte_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
append_status_i : in std_logic;
add_offset_i : in std_logic_vector(6 downto 0);
data_length_i : in std_logic_vector(6 downto 0);
byte_o : out std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i
-------------------------------------------------------------------------------
wb_dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
wb_dat_o : out std_logic_vector (15 downto 0); --!
wb_adr_i : in std_logic_vector (9 downto 0); --!
wb_stb_p_i : in std_logic; --! Strobe
wb_ack_p_o : out std_logic; --! Acknowledge
wb_we_p_i : in std_logic --! Write enable
);
end component wf_produced_vars;
component wf_tx_rx
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
start_send_p_i : in std_logic;
request_byte_p_o : out std_logic;
byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector(7 downto 0);
last_byte_p_i : in std_logic;
-- clk_fixed_carrier_p_o : out std_logic;
d_o : out std_logic;
d_e_o : out std_logic;
d_clk_o : out std_logic;
d_a_i : in std_logic;
rate_i : in std_logic_vector(1 downto 0);
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic
);
end component wf_tx_rx;
component status_gen
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_tx_rx (WorldFIP received data)
-------------------------------------------------------------------------------
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
code_violation_p_i : in std_logic;
crc_bad_p_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_engine
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_i: in std_logic; --! Variable 1 ready
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_i: in std_logic; --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_i: in std_logic; --! Variable 3 ready
var1_access_a_i: in std_logic; --! Variable 1 access
var2_access_a_i: in std_logic; --! Variable 2 access
var3_access_a_i: in std_logic; --! Variable 3 access
-- reset_var1_access_o : out std_logic; --! Reset Variable 1 access flag
-- reset_var2_access_o : out std_logic; --! Reset Variable 2 access flag
-- reset_var3_access_o : out std_logic; --! Reset Variable 2 access flag
stat_sent_p_i : in std_logic;
mps_sent_p_i : in std_logic;
stat_o : out std_logic_vector(7 downto 0);
mps_o : out std_logic_vector(7 downto 0)
-------------------------------------------------------------------------------
-- Connections to data_if
-------------------------------------------------------------------------------
);
end component status_gen;
component reset_logic
generic(c_reset_length : integer := 4); --! Reset counter length. 4==> 16 uclk_i ticks
port (
uclk_i : in std_logic; --! User Clock
rstin_i : in std_logic; --! Initialisation control, active low
--! Reset output, active low. Active when the reset variable is received
--! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
var_i : in t_var; --! Received variable
rst_o : out std_logic --! Reset ouput active high
);
end component reset_logic;
component nanofip
port (
-------------------------------------------------------------------------------
-- WorldFIP settings
-------------------------------------------------------------------------------
--! Bit rate \n
--! 00: 31.25 kbit/s \n
--! 01: 1 Mbit/s \n
--! 10: 2.5 Mbit/s \n
--! 11: reserved, do not use
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
--! Subscriber number coding. Station address.
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Identification selection (see M_ID, C_ID)
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
--! Produced variable data length \n
--! 000: 2 Bytes \n
--! 001: 8 Bytes \n
--! 010: 16 Bytes \n
--! 011: 32 Bytes \n
--! 100: 64 Bytes \n
--! 101: 124 Bytes \n
--! 110: reserved, do not use \n
--! 111: reserved, do not use \n
--! Actual size: +1 NanoFIP Status byte +1 MPS Status byte (last transmitted)
--! Note: when SLONE=Vcc, p3_lgth_i should be set to 000.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-------------------------------------------------------------------------------
-- FIELDRIVE connections
-------------------------------------------------------------------------------
fd_rstn_o : out std_logic; --! Initialisation control, active low
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
-------------------------------------------------------------------------------
-- USER INTERFACE, General signals
-------------------------------------------------------------------------------
uclk_i : in std_logic; --! 40 MHz clock
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
rstin_i : in std_logic; --! Initialisation control, active low
--! Reset output, active low. Active when the reset variable is received
--! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_o: out std_logic; --! Variable 1 ready
--! Signals that the user logic is accessing variable 1. Only used to
--! generate a status that verifies that VAR1_RDY was high when
--! accessing. May be grounded.
var1_acc_i: in std_logic; --! Variable 1 access
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_o: out std_logic; --! Variable 2 ready
--! Signals that the user logic is accessing variable 2. Only used to
--! generate a status that verifies that VAR2_RDY was high when
--! accessing. May be grounded.
var2_acc_i: in std_logic; --! Variable 2 access
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o: out std_logic; --! Variable 3 ready
--! Signals that the user logic is accessing variable 3. Only used to
--! generate a status that verifies that VAR3_RDY was high when
--! accessing. May be grounded.
var3_acc_i: in std_logic; --! Variable 3 access
-------------------------------------------------------------------------------
-- USER INTERFACE, WISHBONE SLAVE
-------------------------------------------------------------------------------
wclk_i : in std_logic; --! Wishbone clock. May be independent of UCLK.
--! Data in. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_i : in std_logic_vector (15 downto 0); --! Data in
--! Data out. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_o : out std_logic_vector (15 downto 0); --! Data out
-- dat_i : in std_logic_vector(15 downto 0);
adr_i : in std_logic_vector ( 9 downto 0); --! Address
rst_i : in std_logic; --! Wishbone reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
ack_o : out std_logic; --! Acknowledge
we_i : in std_logic --! Write enable
);
end component nanofip;
end wf_package;
package body wf_package is
function calc_data_length(var : t_var;
p3_length : std_logic_vector(2 downto 0);
nostat : std_logic;
slone : std_logic) return std_logic_vector is
variable v_nostat : std_logic_vector(1 downto 0);
variable v_p3_length_decoded, v_data_length: unsigned(7 downto 0);
begin
v_nostat := ('0'& ((not nostat) and (not slone)));
v_p3_length_decoded := to_unsigned(c_p3_var_length_table(to_integer(unsigned(p3_length))), v_p3_length_decoded'length);
v_data_length := to_unsigned(0,v_data_length'length);
case var is
when c_st_var_presence =>
v_data_length := to_unsigned(6,v_data_length'length);
when c_st_var_identification =>
v_data_length := to_unsigned(9,v_data_length'length);
when c_st_var_1 =>
when c_st_var_2 =>
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
package wf_package is
constant C_QUARTZ_PERIOD : real := 25.0;
type t_timeouts is
record
response : integer;
silence : integer;
end record;
constant c_31k25_rate_pos : integer := 0;
constant c_1M_rate_pos : integer := 1;
constant c_2M5_rate_pos : integer := 2;
constant c_11_rate_pos : integer := 3;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_timeouts_table : t_timeouts_table(0 to 3) := -- Time in ns
(c_31k25_rate_pos => (response => integer(640000.0/C_QUARTZ_PERIOD), silence => integer(5160000.0/C_QUARTZ_PERIOD)),
c_1M_rate_pos => (response => integer(10000.0/C_QUARTZ_PERIOD), silence => integer(150000.0/C_QUARTZ_PERIOD)),
c_2M5_rate_pos => (response => integer(16000.0/C_QUARTZ_PERIOD), silence => integer(100000.0/C_QUARTZ_PERIOD)),
c_11_rate_pos => (response => integer(640000.0/C_QUARTZ_PERIOD), silence => integer(5160000.0/C_QUARTZ_PERIOD))
);
type t_integer_array is array (natural range <>) of integer;
constant c_p3_var_length_table : t_integer_array(0 to 7) :=
(0 => 2, 1 => 8, 2 => 16, 3 => 32, 4 => 64, 5 => 124, others => 0);
constant c_id_dat : std_logic_vector(7 downto 0) := "00000011";
constant c_rp_dat : std_logic_vector(7 downto 0) := "00000010";
--constant c_var_presence : std_logic_vector(7 downto 0) := x"14";
--constant c_var_identification : std_logic_vector(7 downto 0) := x"10";
--constant c_var_1 : std_logic_vector(7 downto 0) := x"05";
--constant c_var_2 : std_logic_vector(7 downto 0) :=x"04";
--constant c_var_3 : std_logic_vector(7 downto 0) := x"06";
--constant c_var_reset : std_logic_vector(7 downto 0) := x"e0";
type t_var is (c_st_var_presence, c_st_var_identification, c_st_var_1, c_st_var_2, c_st_var_3, c_st_var_reset, c_st_var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
--constant c_pres_byte_array : t_byte_array(1 to 7) := (1 => x"50", 2 => x"05", 3 => x"80", 4 => x"03", 5 => x"00", 6 => x"f0", 7 => x"00");
--constant c_id_byte_array : t_byte_array(1 to 10) := (1 => x"52", 2 => x"08", 3 => x"01", 4 => x"00", 5 => x"00", 6 => x"f0", 7 => x"00", 8 => x"00", 9 => X"00", 10 => X"00");
--
type t_var_response is (produce, consume, reset);
type t_var_record is record
response : t_var_response;
hexvalue : std_logic_vector(7 downto 0);
var : t_var;
base_add : std_logic_vector(9 downto 0);
array_length : integer; --! -1 represents a variable length
byte_array : t_byte_array(0 to 15);
end record;
--
type t_var_array is array (natural range <>) of t_var_record;
constant c_var_length_add : integer := 3;
constant c_pdu_byte_add : integer := 2;
constant c_cons_byte_add : integer := 7;
constant c_model_byte_add : integer := 8;
constant c_var_presence_pos : integer := 0;
constant c_var_identification_pos : integer := 1;
constant c_var_var3_pos : integer := 2;
constant c_var_var1_pos : integer := 3;
constant c_var_var2_pos : integer := 4;
constant c_var_reset_pos : integer := 5;
constant c_byte_0_add : integer := 2;
constant c_byte_1_add : integer := 3;
constant c_var_array : t_var_array(0 to 5):=
(c_var_presence_pos => (var => c_st_var_presence,
hexvalue => x"14",
response => produce,
base_add => "----------",
array_length => 8,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"50", 3 => x"05", 4 => x"80", 5 => x"03", 6 => x"00",
7 => x"f0", 8 => x"00", others => x"ff")),
c_var_identification_pos => (var => c_st_var_identification,
hexvalue => x"10",
response => produce,
array_length => 11,
base_add => "----------",
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"52", 3 => x"08", 4 => x"01", 5 => x"00", 6 => x"00",
7 => x"f0", 8 => x"00", 9 => x"00", 10 => X"00", 11 => X"00",
others => x"ff")),
c_var_var3_pos => (var => c_st_var_3,
hexvalue => x"06",
response => produce,
base_add => "0000000000",
array_length => 3,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"40", others => x"ff")),
c_var_var1_pos => (var => c_st_var_1,
hexvalue => x"05",
response => consume,
base_add => "0000000000",
array_length => 8,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"50", 3 => x"05", 4 => x"80", 5 => x"03", 6 => x"00",
7 => x"f0", 8 => x"00", others => x"ff")),
c_var_var2_pos => (var => c_st_var_2,
hexvalue => x"04",
response => consume,
base_add => "0010000000",
array_length => 2,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"40", others => x"ff")),
c_var_reset_pos => (var => c_st_var_reset,
hexvalue => x"e0",
response => reset,
base_add => "0100000000",
array_length => 2,
byte_array => (0 => c_rp_dat, 1 => x"ff", 2 => x"40", others => x"ff")));
--Status bit position
constant c_u_cacer_pos : integer := 2; --! Consumed variable access error
constant c_u_pacer_pos : integer := 3; --! Produced variable access error
constant c_r_bner_pos : integer := 4; --! Received bit number error. Replaced by code violation.
constant c_r_fcser_pos : integer := 5; --! Received FCS access error
constant c_t_txer_pos : integer := 6; --! Transmit error (FIELDDRIVE)
constant c_t_wder_pos : integer := 7; --! Watchdog error (FIELDDRIVE)
constant c_refreshment_pos : integer := 0; --! MPS refreshment bit
constant c_significance_pos : integer := 2; --! MPS significance bit
function calc_data_length(var : t_var;
p3_length : std_logic_vector(2 downto 0);
nostat : std_logic;
slone : std_logic) return std_logic_vector;
component wf_rx_osc
generic (C_OSC_LENGTH : integer := 20;
C_QUARTZ_PERIOD : real := 25.0;
C_CLKFCDLENTGTH : natural := 3
);
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
d_edge_i : in std_logic;
load_phase_i : in std_logic;
--! Bit rate \n
--! 00: 31.25 kbit/s => 62.5 KHz \n
--! 01: 1 Mbit/s => 2 MHz \n
--! 10: 2.5 Mbit/s => 5 MHz \n
--! 11: reserved, do not use
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
clk_fixed_carrier_p_o : out std_logic;
clk_fixed_carrier_p_d_o : out std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
clk_fixed_carrier_o : out std_logic;
clk_carrier_p_o : out std_logic;
clk_carrier_180_p_o : out std_logic;
clk_bit_p_o : out std_logic;
clk_bit_90_p_o : out std_logic;
clk_bit_180_p_o : out std_logic;
clk_bit_270_p_o : out std_logic;
edge_window_o : out std_logic;
edge_180_window_o : out std_logic;
phase_o : out std_logic_vector(C_OSC_LENGTH -1 downto 0)
);
end component wf_rx_osc;
component wf_crc
generic(
c_poly_length : natural := 16);
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
start_p_i : in std_logic;
d_i : in std_logic;
d_rdy_p_i : in std_logic;
data_fcs_sel_n : in std_logic;
crc_o : out std_logic_vector(c_poly_length - 1 downto 0);
crc_rdy_p_o : out std_logic;
crc_ok_p : out std_logic
);
end component wf_crc;
component deglitcher
Generic (C_ACULENGTH : integer := 10);
Port ( uclk_i : in STD_LOGIC;
d_i : in STD_LOGIC;
d_o : out STD_LOGIC;
carrier_p_i : in STD_LOGIC;
d_ready_p_o : out STD_LOGIC);
end component deglitcher;
component wf_rx
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic;
d_re_i : in std_logic;
d_fe_i : in std_logic;
d_filtered_i : in std_logic;
s_d_ready_p_i : in std_logic;
load_phase_o : out std_logic;
clk_bit_180_p_i : in std_logic;
edge_window_i : in std_logic;
edge_180_window_i : in std_logic
);
end component wf_rx;
component wf_tx
generic(
C_CLKFCDLENTGTH : natural := 3 );
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
start_send_p_i : in std_logic;
request_byte_p_o : out std_logic;
byte_ready_p_i : in std_logic; -- byte_ready_p_i is not used
byte_i : in std_logic_vector(7 downto 0);
last_byte_p_i : in std_logic;
-- clk_fixed_carrier_p_d_i(0) : in std_logic;
clk_fixed_carrier_p_d_i : in std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
d_o : out std_logic;
d_e_o : out std_logic
);
end component wf_tx;
component dpblockram_clka_rd_clkb_wr
generic (c_dl : integer := 42; -- Length of the data word
c_al : integer := 10); -- Number of words
-- 'nw' has to be coherent with 'c_al'
port (clka_i : in std_logic; -- Global Clock
aa_i : in std_logic_vector(c_al - 1 downto 0);
da_o : out std_logic_vector(c_dl -1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_al - 1 downto 0);
db_i : in std_logic_vector(c_dl - 1 downto 0);
web_i : in std_logic);
end component dpblockram_clka_rd_clkb_wr;
component wf_engine_control
generic( C_QUARTZ_PERIOD : real := 25.0);
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
-- Transmiter interface
start_send_p_o : out std_logic;
request_byte_p_i : in std_logic;
byte_ready_p_o : out std_logic;
-- byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
-- Receiver interface
fss_decoded_p_i : in std_logic; -- The frame decoder has detected the start of a frame
byte_ready_p_i : in std_logic; -- The frame docoder ouputs a new byte on byte_i
byte_i : in std_logic_vector(7 downto 0); -- Decoded byte
frame_ok_p_i : in std_logic;
-- Worldfip bit rate
rate_i : in std_logic_vector(1 downto 0);
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Produced variable data length \n
--! 000: 2 Bytes \n
--! 001: 8 Bytes \n
--! 010: 16 Bytes \n
--! 011: 32 Bytes \n
--! 100: 64 Bytes \n
--! 101: 124 Bytes \n
--! 110: reserved, do not use \n
--! 111: reserved, do not use \n
--! Actual size: +1 NanoFIP Status byte +1 MPS Status byte (last transmitted)
--! Note: when SLONE=Vcc, p3_lgth_i should be set to 000.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_o: out std_logic; --! Variable 1 ready
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_o: out std_logic; --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o: out std_logic; --! Variable 3 ready
-- prod_byte_i : in std_logic_vector(7 downto 0);
var_o : out t_var;
append_status_o : out std_logic;
add_offset_o : out std_logic_vector(6 downto 0);
data_length_o : out std_logic_vector(6 downto 0);
cons_byte_we_p_o : out std_logic
);
end component wf_engine_control;
component wf_consumed_vars
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
byte_ready_p_i : in std_logic;
var_i : in t_var;
-- append_status_i : in std_logic;
add_offset_i : in std_logic_vector(6 downto 0);
-- data_length_i : in std_logic_vector(6 downto 0);
byte_i : in std_logic_vector(7 downto 0);
-- var1_access_wb_clk_o: out std_logic; --! Variable 1 access flag
-- var2_access_wb_clk_o: out std_logic; --! Variable 2 access flag
-- reset_var1_access_i: in std_logic; --! Reset Variable 1 access flag
-- reset_var2_access_i: in std_logic; --! Reset Variable 2 access flag
-------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i
-------------------------------------------------------------------------------
-- dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
wb_dat_o : out std_logic_vector (15 downto 0); --!
wb_adr_i : in std_logic_vector (9 downto 0); --!
wb_stb_p_i : in std_logic; --! Strobe
wb_ack_p_o : out std_logic; --! Acknowledge
wb_we_p_i : in std_logic --! Write enable
);
end component wf_consumed_vars;
component wf_produced_vars is
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
--! Identification selection (see M_ID, C_ID)
-- s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_dec_i : in std_logic_vector (7 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_dec_i : in std_logic_vector (7 downto 0); --! Constructor identification settings
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
stat_i : in std_logic_vector(7 downto 0); --! NanoFIP status
mps_i : in std_logic_vector(7 downto 0);
sending_stat_o : out std_logic; --! The status register is being adressed
sending_mps_o : out std_logic; --! The status register is being adressed
-- var3_access_wb_clk_o: out std_logic; --! Variable 2 access flag
-- reset_var3_access_i: in std_logic; --! Reset Variable 1 access flag
-- prod_byte_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
append_status_i : in std_logic;
add_offset_i : in std_logic_vector(6 downto 0);
data_length_i : in std_logic_vector(6 downto 0);
byte_o : out std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i
-------------------------------------------------------------------------------
wb_dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
wb_dat_o : out std_logic_vector (15 downto 0); --!
wb_adr_i : in std_logic_vector (9 downto 0); --!
wb_stb_p_i : in std_logic; --! Strobe
wb_ack_p_o : out std_logic; --! Acknowledge
wb_we_p_i : in std_logic --! Write enable
);
end component wf_produced_vars;
component wf_tx_rx
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
start_send_p_i : in std_logic;
request_byte_p_o : out std_logic;
byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector(7 downto 0);
last_byte_p_i : in std_logic;
-- clk_fixed_carrier_p_o : out std_logic;
d_o : out std_logic;
d_e_o : out std_logic;
d_clk_o : out std_logic;
d_a_i : in std_logic;
rate_i : in std_logic_vector(1 downto 0);
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic
);
end component wf_tx_rx;
component status_gen
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_tx_rx (WorldFIP received data)
-------------------------------------------------------------------------------
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
code_violation_p_i : in std_logic;
crc_bad_p_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_engine
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_i: in std_logic; --! Variable 1 ready
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_i: in std_logic; --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_i: in std_logic; --! Variable 3 ready
var1_access_a_i: in std_logic; --! Variable 1 access
var2_access_a_i: in std_logic; --! Variable 2 access
var3_access_a_i: in std_logic; --! Variable 3 access
-- reset_var1_access_o : out std_logic; --! Reset Variable 1 access flag
-- reset_var2_access_o : out std_logic; --! Reset Variable 2 access flag
-- reset_var3_access_o : out std_logic; --! Reset Variable 2 access flag
stat_sent_p_i : in std_logic;
mps_sent_p_i : in std_logic;
stat_o : out std_logic_vector(7 downto 0);
mps_o : out std_logic_vector(7 downto 0)
-------------------------------------------------------------------------------
-- Connections to data_if
-------------------------------------------------------------------------------
);
end component status_gen;
component reset_logic
generic(c_reset_length : integer := 4); --! Reset counter length. 4==> 16 uclk_i ticks
port (
uclk_i : in std_logic; --! User Clock
rstin_i : in std_logic; --! Initialisation control, active low
--! Reset output, active low. Active when the reset variable is received
--! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
var_i : in t_var; --! Received variable
rst_o : out std_logic --! Reset ouput active high
);
end component reset_logic;
component nanofip
port (
-------------------------------------------------------------------------------
-- WorldFIP settings
-------------------------------------------------------------------------------
--! Bit rate \n
--! 00: 31.25 kbit/s \n
--! 01: 1 Mbit/s \n
--! 10: 2.5 Mbit/s \n
--! 11: reserved, do not use
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
--! Subscriber number coding. Station address.
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
--! Identification selection (see M_ID, C_ID)
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
--! Produced variable data length \n
--! 000: 2 Bytes \n
--! 001: 8 Bytes \n
--! 010: 16 Bytes \n
--! 011: 32 Bytes \n
--! 100: 64 Bytes \n
--! 101: 124 Bytes \n
--! 110: reserved, do not use \n
--! 111: reserved, do not use \n
--! Actual size: +1 NanoFIP Status byte +1 MPS Status byte (last transmitted)
--! Note: when SLONE=Vcc, p3_lgth_i should be set to 000.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-------------------------------------------------------------------------------
-- FIELDRIVE connections
-------------------------------------------------------------------------------
fd_rstn_o : out std_logic; --! Initialisation control, active low
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
-------------------------------------------------------------------------------
-- USER INTERFACE, General signals
-------------------------------------------------------------------------------
uclk_i : in std_logic; --! 40 MHz clock
--! Stand-alone mode
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
slone_i : in std_logic; --! Stand-alone mode
--! No NanoFIP status transmission
--! If connected to Vcc, disables sending of NanoFIP status together with
--! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission
rstin_i : in std_logic; --! Initialisation control, active low
--! Reset output, active low. Active when the reset variable is received
--! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
-------------------------------------------------------------------------------
-- USER INTERFACE, non WISHBONE
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_o: out std_logic; --! Variable 1 ready
--! Signals that the user logic is accessing variable 1. Only used to
--! generate a status that verifies that VAR1_RDY was high when
--! accessing. May be grounded.
var1_acc_i: in std_logic; --! Variable 1 access
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_o: out std_logic; --! Variable 2 ready
--! Signals that the user logic is accessing variable 2. Only used to
--! generate a status that verifies that VAR2_RDY was high when
--! accessing. May be grounded.
var2_acc_i: in std_logic; --! Variable 2 access
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_o: out std_logic; --! Variable 3 ready
--! Signals that the user logic is accessing variable 3. Only used to
--! generate a status that verifies that VAR3_RDY was high when
--! accessing. May be grounded.
var3_acc_i: in std_logic; --! Variable 3 access
-------------------------------------------------------------------------------
-- USER INTERFACE, WISHBONE SLAVE
-------------------------------------------------------------------------------
wclk_i : in std_logic; --! Wishbone clock. May be independent of UCLK.
--! Data in. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_i : in std_logic_vector (15 downto 0); --! Data in
--! Data out. Wishbone access only on bits 7-0. Bits 15-8 only used
--! in stand-alone mode.
dat_o : out std_logic_vector (15 downto 0); --! Data out
-- dat_i : in std_logic_vector(15 downto 0);
adr_i : in std_logic_vector ( 9 downto 0); --! Address
rst_i : in std_logic; --! Wishbone reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
ack_o : out std_logic; --! Acknowledge
we_i : in std_logic; --! Write enable;
cyc_i : in std_logic
);
end component nanofip;
component wf_dec_m_ids
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
s_id_o : out std_logic_vector(1 downto 0);
--! Identification variable settings.
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification settings
--! Constructor identification settings.
c_id_dec_o : out std_logic_vector (7 downto 0); --! Constructor identification settings
--! Identification variable settings.
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
--! Constructor identification settings.
c_id_i : in std_logic_vector (3 downto 0) --! Constructor identification settings
);
end component wf_dec_m_ids;
end wf_package;
package body wf_package is
function calc_data_length(var : t_var;
p3_length : std_logic_vector(2 downto 0);
nostat : std_logic;
slone : std_logic) return std_logic_vector is
variable v_nostat : std_logic_vector(1 downto 0);
variable v_p3_length_decoded, v_data_length: unsigned(7 downto 0);
begin
v_nostat := ('0'& ((not nostat) and (not slone)));
v_p3_length_decoded := to_unsigned(c_p3_var_length_table(to_integer(unsigned(p3_length))), v_p3_length_decoded'length);
v_data_length := to_unsigned(0,v_data_length'length);
case var is
when c_st_var_presence =>
v_data_length := to_unsigned(6,v_data_length'length);
when c_st_var_identification =>
v_data_length := to_unsigned(9,v_data_length'length);
when c_st_var_1 =>
when c_st_var_2 =>
when c_st_var_3 =>
if nostat = '1' then
v_data_length := to_unsigned(3,v_data_length'length);
else
v_data_length := v_p3_length_decoded + unsigned(v_nostat) ;
end if;
when c_st_var_reset =>
when others =>
end case;
return std_logic_vector(v_data_length);
end;
end wf_package;
if nostat = '1' then
v_data_length := to_unsigned(3,v_data_length'length);
else
v_data_length := v_p3_length_decoded + unsigned(v_nostat) ;
end if;
when c_st_var_reset =>
when others =>
end case;
return std_logic_vector(v_data_length);
end;
end wf_package;
\ No newline at end of file
wf_produced_vars.vhd
View file @ b35a6d7a
......@@ -66,25 +66,11 @@ entity wf_produced_vars is
--! Identification selection (see M_ID, C_ID)
-- s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
m_id_dec_i : in std_logic_vector (7 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
c_id_dec_i : in std_logic_vector (7 downto 0); --! Constructor identification settings
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
......@@ -206,7 +192,7 @@ s_add_to_ram <= std_logic_vector(unsigned(add(s_add_to_ram'range)) - 2);
add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add));
process(s_mem_byte, subs_i, mps_i, var_i, add_offset_i, s_io_byte, data_length_i, append_status_i, stat_i, slone_i, c_id_i, m_id_i)
process(s_mem_byte, subs_i, mps_i, var_i, add_offset_i, s_io_byte, data_length_i, append_status_i, stat_i, slone_i, c_id_dec_i, m_id_dec_i)
begin
s_byte <= s_mem_byte;
base_add <= (others => '0');
......@@ -233,10 +219,10 @@ s_add_to_ram <= std_logic_vector(unsigned(add(s_add_to_ram'range)) - 2);
--! identification or presence
if c_var_array(I).var = c_st_var_identification then
if unsigned(add_offset_i) = c_cons_byte_add then
s_byte(c_id_i'range) <= c_id_i;
s_byte(c_id_dec_i'range) <= c_id_dec_i;
exit;
elsif unsigned(add_offset_i) = c_model_byte_add then
s_byte(m_id_i'range) <= m_id_i;
s_byte(m_id_dec_i'range) <= m_id_dec_i;
exit;
else
s_byte <= c_var_array(I).byte_array(to_integer(unsigned(add_offset_i(3 downto 0))));
......
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