Skip to content

N
nanoFIP - Gateware
Commit b35a6d7a authored by palvarez's avatar palvarez
Browse files
Options

Wishbone seems ok... 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@30 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 4edc9f27
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1427 additions and 1340 deletions
DualClkRAM.vhd
View file @ b35a6d7a
-- Version: 8.6 SP1 8.6.1.3
-------------------------------------------------------------------------------
--! @file DualClkRAM.vhd
-------------------------------------------------------------------------------
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- --
-- CERN, BE --
-- --
-------------------------------------------------------------------------------
--
-- unit name: dpblockram.vhd
--
--! @brief The DualClkRAM instantiates a template for a true dual port ram clocked on both ports by different clocks. The architecture RAM4K9 instantiates the same Proasic3 component.
--!
--!
--! @author <Pablo Alvarez(pablo.alvarez.sanchez@cern.ch)>
--
--! @date 24\01\2009
--
--! @version 1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--!
--!
--! <b>References:</b>\n
--! <reference one> \n
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 24\01\2009 paas header included\n
--! <extended description>
-------------------------------------------------------------------------------
--! @todo Adapt vhdl sintax to ohr standard\n
--! <another thing to do> \n
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -15,7 +62,7 @@ entity DualClkRAM is
end DualClkRAM;
architecture DEF_ARCH of DualClkRAM is
architecture RAM4K9 of DualClkRAM is
component RAM4K9
generic (MEMORYFILE:string := "");
......@@ -75,4 +122,4 @@ architecture DEF_ARCH of DualClkRAM is
DOUTB(6), DOUTB5 => DOUTB(5), DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3), DOUTB2 => DOUTB(2), DOUTB1 =>
DOUTB(1), DOUTB0 => DOUTB(0));
end DEF_ARCH;
\ No newline at end of file
end RAM4K9;
\ No newline at end of file
NanoFip.pdc
View file @ b35a6d7a
......@@ -3,7 +3,7 @@
# Version: 8.6 SP1 8.6.1.3
# Family: ProASIC3 , Die: A3P400 , Package: 144 FBGA
# Date generated: Fri Feb 19 17:54:33 2010
# Date generated: Thu Apr 08 16:39:17 2010
#
......@@ -105,6 +105,12 @@ set_io {c_id_i[3]} \
-DIRECTION Input
set_io cyc_i \
-pinname C2 \
-fixed yes \
-DIRECTION Input
set_io {dat_i[0]} \
-pinname H2 \
-fixed yes \
......@@ -574,6 +580,7 @@ set_io we_i \
# set_io {c_id_i[1]} -pinname D8 -fixed yes -DIRECTION Input
# set_io {c_id_i[2]} -pinname D9 -fixed yes -DIRECTION Input
# set_io {c_id_i[3]} -pinname G9 -fixed yes -DIRECTION Input
# set_io cyc_i -pinname C2 -fixed yes -DIRECTION Input
# set_io {dat_i[0]} -pinname H2 -fixed yes -DIRECTION Input
# set_io {dat_i[1]} -pinname H3 -fixed yes -DIRECTION Input
# set_io {dat_i[2]} -pinname H4 -fixed yes -DIRECTION Input
......@@ -600,7 +607,7 @@ set_io we_i \
# set_io {dat_o[7]} -pinname J6 -fixed yes -DIRECTION Output
# set_io {dat_o[8]} -pinname H6 -fixed yes -DIRECTION Output
# set_io {dat_o[9]} -pinname G1 -fixed yes -DIRECTION Output
# set_io {dat_o[10]} -pinname G4 -fixed yes -DIRECTION Output
# set_io {dat_o[10]} -pinname K8 -fixed yes -DIRECTION Output
# set_io {dat_o[11]} -pinname F1 -fixed yes -DIRECTION Output
# set_io {dat_o[12]} -pinname F3 -fixed yes -DIRECTION Output
# set_io {dat_o[13]} -pinname F4 -fixed yes -DIRECTION Output
......@@ -611,7 +618,7 @@ set_io we_i \
# set_io fd_txena_o -pinname E11 -fixed yes -DIRECTION Output
# set_io fd_txer_i -pinname G11 -fixed yes -DIRECTION Input
# set_io fd_wdgn_i -pinname F11 -fixed yes -DIRECTION Input
# set_io fx_rxa_i -pinname F12 -fixed yes -DIRECTION Input
# set_io fx_rxa_i -pinname K12 -fixed yes -DIRECTION Input
# set_io fx_rxd_i -pinname E12 -fixed yes -DIRECTION Input
# set_io fx_txd_o -pinname G12 -fixed yes -DIRECTION Output
# set_io {m_id_i[0]} -pinname C9 -fixed yes -DIRECTION Input
......@@ -639,12 +646,12 @@ set_io we_i \
# set_io {subs_i[5]} -pinname B10 -fixed yes -DIRECTION Input
# set_io {subs_i[6]} -pinname A10 -fixed yes -DIRECTION Input
# set_io {subs_i[7]} -pinname A11 -fixed yes -DIRECTION Input
# set_io uclk_i -pinname C2 -fixed yes -DIRECTION Input
# set_io uclk_i -pinname F12 -fixed yes -DIRECTION Input
# set_io var1_acc_i -pinname C1 -fixed yes -DIRECTION Input
# set_io var1_rdy_o -pinname D5 -fixed yes -DIRECTION Output
# set_io var2_acc_i -pinname D1 -fixed yes -DIRECTION Input
# set_io var2_rdy_o -pinname D3 -fixed yes -DIRECTION Output
# set_io var3_acc_i -pinname D4 -fixed yes -DIRECTION Input
# set_io var3_rdy_o -pinname D2 -fixed yes -DIRECTION Output
# set_io wclk_i -pinname L3 -fixed yes -DIRECTION Input
# set_io wclk_i -pinname G4 -fixed yes -DIRECTION Input
# set_io we_i -pinname L7 -fixed yes -DIRECTION Input
deglitcher.vhd
View file @ b35a6d7a
......@@ -46,8 +46,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--! Pablo Alvarez Sanchez
--! Author: Pablo Alvarez Sanchez
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/08/2009 v0.02 PAAS Entity Ports added, start of architecture content
......
dpblockram_clka_rd_clkb_wr_syn.vhd
View file @ b35a6d7a
......@@ -35,7 +35,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: <name>
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 24\01\2009 paas header included\n
......@@ -77,10 +77,14 @@ end component DualClkRam;
signal s_zeros_da : std_logic_vector(7 downto 0);
signal zero : std_logic;
signal one : std_logic;
signal s_rw : std_logic;
begin
s_zeros_da <= (others => '0');
zero <= '0';
one <= '1';
s_rw <= not web_i;
UDualClkRam : DualClkRam
port map ( DINA => s_zeros_da,
DOUTA => da_o,
......@@ -88,13 +92,13 @@ UDualClkRam : DualClkRam
DOUTB => open,
ADDRA => aa_i,
ADDRB => ab_i,
RWA => zero,
RWB => web_i,
RWA => one,
RWB => s_rw,
BLKA => zero,
BLKB => zero,
CLKA => clka_i,
CLKB => clkb_i,
RESET => zero) ;
RESET => one) ;
end syn;
\ No newline at end of file
nanofip.vhd
View file @ b35a6d7a
This diff is collapsed.
reset_logic.vhd
View file @ b35a6d7a
......@@ -43,7 +43,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--! Author:Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 EB First version \n
......
status_gen.vhd
View file @ b35a6d7a
......@@ -45,7 +45,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 EB First version \n
......
wf_consumed_vars.vhd
View file @ b35a6d7a
......@@ -45,7 +45,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author:
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 11/09/2009 v0.01 EB First version \n
......
wf_engine_control.vhd
View file @ b35a6d7a
......@@ -49,7 +49,7 @@ use work.wf_package.all;
--!
--!
--! <b>Modified by:</b>\n
--! Author:
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 11/09/2009 v0.01 EB First version \n
......
wf_package.vhd
View file @ b35a6d7a
This diff is collapsed.
wf_produced_vars.vhd
View file @ b35a6d7a
......@@ -66,25 +66,11 @@ entity wf_produced_vars is
--! Identification selection (see M_ID, C_ID)
-- s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
--! Identification variable settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Model [2*i] 0 1 0 1 \n
--! Model [2*i+1] 0 0 1 1
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
m_id_dec_i : in std_logic_vector (7 downto 0); --! Model identification settings
--! Constructor identification settings.
--! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to
--! obtain different values for the Model data (i=0,1,2,3).\n
--! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc \n
--! Constructor[2*i] 0 1 0 1 \n
--! Constructor[2*i+1] 0 0 1 1
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
c_id_dec_i : in std_logic_vector (7 downto 0); --! Constructor identification settings
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
......@@ -206,7 +192,7 @@ s_add_to_ram <= std_logic_vector(unsigned(add(s_add_to_ram'range)) - 2);
add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add));
process(s_mem_byte, subs_i, mps_i, var_i, add_offset_i, s_io_byte, data_length_i, append_status_i, stat_i, slone_i, c_id_i, m_id_i)
process(s_mem_byte, subs_i, mps_i, var_i, add_offset_i, s_io_byte, data_length_i, append_status_i, stat_i, slone_i, c_id_dec_i, m_id_dec_i)
begin
s_byte <= s_mem_byte;
base_add <= (others => '0');
......@@ -233,10 +219,10 @@ s_add_to_ram <= std_logic_vector(unsigned(add(s_add_to_ram'range)) - 2);
--! identification or presence
if c_var_array(I).var = c_st_var_identification then
if unsigned(add_offset_i) = c_cons_byte_add then
s_byte(c_id_i'range) <= c_id_i;
s_byte(c_id_dec_i'range) <= c_id_dec_i;
exit;
elsif unsigned(add_offset_i) = c_model_byte_add then
s_byte(m_id_i'range) <= m_id_i;
s_byte(m_id_dec_i'range) <= m_id_dec_i;
exit;
else
s_byte <= c_var_array(I).byte_array(to_integer(unsigned(add_offset_i(3 downto 0))));
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment