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nanoFIP - Gateware
Commit fb9e6d87 authored by pabloalvarez's avatar pabloalvarez
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status and reset added. 

Some details to fix, such as field drive special pins and reset width
Not simulated!

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@14 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 0666e279
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Showing with 643 additions and 298 deletions
deglitcher.vhd
View file @ fb9e6d87
--=========================================================================== --===========================================================================
--! @file deglitcher.vhd --! @file deglitcher.vhd
--! @brief Deserialises the WorldFIP data --! @brief Glitch filter. 1 pulse adapted filter.
--=========================================================================== --===========================================================================
--! Standard library --! Standard library
library IEEE; library IEEE;
...@@ -19,10 +19,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -19,10 +19,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
-- unit name: deglitcher -- unit name: deglitcher
-- --
--! @brief 1 microsecond pulse adapted filter --! @brief Glitch filter. 1 pulse adapted filter.
--!
--!
--! --!
--! Used in the NanoFIP design. \n
--! This unit serializes the data.
--! --!
--! --!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
...@@ -63,11 +63,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -63,11 +63,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! Entity declaration for deglitcher --! Entity declaration for deglitcher
--============================================================================ --============================================================================
entity deglitcher is entity deglitcher is
Generic (C_ACULENGTH : integer := 10); Generic (C_ACULENGTH : integer := 10);
Port ( uclk_i : in STD_LOGIC; Port ( uclk_i : in STD_LOGIC;
d_i : in STD_LOGIC; d_i : in STD_LOGIC;
d_o : out STD_LOGIC; d_o : out STD_LOGIC;
carrier_p_i : in STD_LOGIC; carrier_p_i : in STD_LOGIC;
d_ready_p_o : out STD_LOGIC); d_ready_p_o : out STD_LOGIC);
end deglitcher; end deglitcher;
...@@ -94,7 +94,7 @@ process(uclk_i) ...@@ -94,7 +94,7 @@ process(uclk_i)
begin if rising_edge(uclk_i) then begin if rising_edge(uclk_i) then
if carrier_p_i = '1' then if carrier_p_i = '1' then
d_o <= s_onesc(s_onesc'left); d_o <= s_onesc(s_onesc'left);
end if; end if;
d_ready_p_o <= carrier_p_i; d_ready_p_o <= carrier_p_i;
end if; end if;
end process; end process;
......
nanofip.vhd
View file @ fb9e6d87
...@@ -257,13 +257,26 @@ signal s_crc_ok_from_rx : std_logic; ...@@ -257,13 +257,26 @@ signal s_crc_ok_from_rx : std_logic;
signal fss_decoded_p_from_rx : std_logic; signal fss_decoded_p_from_rx : std_logic;
signal frame_ok_from_rx : std_logic; signal frame_ok_from_rx : std_logic;
signal s_stat : std_logic_vector(7 downto 0); signal s_stat : std_logic_vector(7 downto 0);
--signal signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_stat_sent_p, s_sending_stat: std_logic;
signal s_mps_sent_p, s_sending_mps: std_logic;
signal s_code_violation_p : std_logic;
signal s_crc_bad_p : std_logic;
signal s_var1_rdy : std_logic;
signal s_var2_rdy : std_logic;
signal s_var3_rdy : std_logic;
signal s_var1_access_wb_clk : std_logic;
signal s_var2_access_wb_clk : std_logic;
signal s_var3_access_wb_clk : std_logic;
signal s_reset_var1_access : std_logic;
signal s_reset_var2_access : std_logic;
signal s_reset_var3_access : std_logic;
--signal s_stat : std_logic_vector(7 downto 0);
signal s_mps : std_logic_vector(7 downto 0);
begin begin
s_rst <= rst_i; s_rst <= rst_i;
----! Placeholder for WorldFIP transmitter/receiver
uwf_tx_rx : wf_tx_rx uwf_tx_rx : wf_tx_rx
port map( port map(
...@@ -290,6 +303,9 @@ port map( ...@@ -290,6 +303,9 @@ port map(
fss_decoded_p_o => fss_decoded_p_from_rx, -- The frame decoder has detected the start of a frame fss_decoded_p_o => fss_decoded_p_from_rx, -- The frame decoder has detected the start of a frame
last_byte_p_o => s_last_byte_from_rx_p, last_byte_p_o => s_last_byte_from_rx_p,
code_violation_p_o => s_code_violation_p,
crc_bad_p_o => s_crc_bad_p,
crc_ok_p_o => s_crc_ok_from_rx crc_ok_p_o => s_crc_ok_from_rx
); );
...@@ -355,12 +371,22 @@ port map( ...@@ -355,12 +371,22 @@ port map(
var_i => s_var_from_control, var_i => s_var_from_control,
add_offset_i => s_add_offset_from_control, add_offset_i => s_add_offset_from_control,
byte_i => s_byte_from_rx, byte_i => s_byte_from_rx,
dat_o => open, --!
adr_i => addr_from_wb --! var1_access_wb_clk_o => s_var1_access_wb_clk,
var2_access_wb_clk_o => s_var2_access_wb_clk,
reset_var1_access_i => s_reset_var1_access,
reset_var2_access_i => s_reset_var2_access,
wb_clk_i => wclk_i,
wb_dat_o => dat_o,
wb_adr_i => adr_i,
wb_stb_p_i => stb_i,
wb_ack_p_o => s_ack_consumed,
wb_we_p_i => we_i
); );
addr_from_wb <= (others => '0');
uwf_produced_vars : wf_produced_vars uwf_produced_vars : wf_produced_vars
...@@ -371,18 +397,65 @@ port map( ...@@ -371,18 +397,65 @@ port map(
c_id_i => c_id_i, --! Constructor identification settings c_id_i => c_id_i, --! Constructor identification settings
slone_i => slone_i, --! Stand-alone mode slone_i => slone_i, --! Stand-alone mode
nostat_i => nostat_i, --! No NanoFIP status transmission nostat_i => nostat_i, --! No NanoFIP status transmission
stat_i => s_stat, -- NanoFIP status
sending_stat_o => s_sending_stat, --! The status register is being adressed
sending_mps_o => s_sending_mps, --! The status register is being adressed
stat_i => s_stat, -- NanoFIP status
mps_i => s_mps,
var3_access_wb_clk_o => s_var3_access_wb_clk,
reset_var3_access_i => s_reset_var3_access,
var_i => s_var_from_control, var_i => s_var_from_control,
append_status_i => s_append_status_from_control, append_status_i => s_append_status_from_control,
add_offset_i => s_add_offset_from_control, add_offset_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control, data_length_i => s_data_length_from_control,
byte_o => s_byte_to_tx, byte_o => s_byte_to_tx,
dat_i => dat_i, --! -------------------------------------------------------------------------------
adr_i => adr_i, --! --! USER INTERFACE. Data and address lines synchronized with uclk_i
we_p_i => we_i --! Write enable -------------------------------------------------------------------------------
wb_dat_i => dat_i,
wb_clk_i => wclk_i,
wb_adr_i => adr_i,
wb_stb_p_i => stb_i,
wb_ack_p_o => s_ack_produced,
wb_we_p_i => we_i
);
ustatus_gen : status_gen
port map(
uclk_i => uclk_i,
rst_i => rst_i,
); fd_wdgn_i => fd_wdgn_i,
s_stat <= (others => '0'); fd_txer_i => fd_txer_i,
code_violation_p_i => s_code_violation_p,
crc_bad_p_i => s_crc_bad_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy,
var1_access_a_i => s_var1_access_wb_clk,
var2_access_a_i => s_var2_access_wb_clk,
var3_access_a_i => s_var3_access_wb_clk,
reset_var1_access_o => s_reset_var1_access,
reset_var2_access_o => s_reset_var2_access,
reset_var3_access_o => s_reset_var3_access,
stat_sent_p_i => s_stat_sent_p,
mps_sent_p_i => s_mps_sent_p,
stat_o => s_stat,
mps_o => s_mps
);
s_ack_o <= s_ack_produced or s_ack_consumed;
s_stat_sent_p <= s_sending_stat and s_byte_to_tx_ready_p; --! The status register is being adressed
s_mps_sent_p <= s_sending_stat and s_byte_to_tx_ready_p; --! The status register is being adressed
end architecture struc; end architecture struc;
--============================================================================ --============================================================================
--============================================================================ --============================================================================
......
reset_logic.vhd
View file @ fb9e6d87
--=========================================================================== --===========================================================================
--! @file reset_logic.vhd --! @file reset_logic.vhd
--! @brief Reset logic --! @brief Reset logic
--=========================================================================== --===========================================================================
--! Standard library --! Standard library
library IEEE; library IEEE;
--! Standard packages --! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions use IEEE.NUMERIC_STD.all; --! conversion functions
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- -- -- --
-- reset_logic -- -- reset_logic --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- unit name: reset_logic -- unit name: reset_logic
-- --
--! @brief Reset logic. --! @brief Reset logic.
--! --!
--! Used in the NanoFIP design. \n --! Used in the NanoFIP design. \n
--! The reset_logic implements the power-on reset and other resets (consumption --! The reset_logic implements the power-on reset and other resets (consumption
--! of the reset variable). --! of the reset variable).
--! --!
--! --!
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch) --! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
-- --
--! @date 07/07/2009 --! @date 07/07/2009
-- --
--! @version v0.01 --! @version v0.01
-- --
--! @details --! @details
--! --!
--! <b>Dependencies:</b>\n --! <b>Dependencies:</b>\n
--! wf_engine \n --! wf_engine \n
--! --!
--! <b>References:</b>\n --! <b>References:</b>\n
--! --!
--! --!
--! --!
--! <b>Modified by:</b>\n --! <b>Modified by:</b>\n
--! Author: Erik van der Bij --! Author: Erik van der Bij
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 EB First version \n --! 07/07/2009 v0.01 EB First version \n
--! --!
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--! @todo Define I/O signals \n --! @todo Define I/O signals \n
--! --!
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--============================================================================ --============================================================================
--! Entity declaration for reset_logic --! Entity declaration for reset_logic
--============================================================================ --============================================================================
entity reset_logic is entity reset_logic is
port ( port (
------------------------------------------------------------------------------- uclk_i : in std_logic; --! User Clock
-- Connections to wf_engine
------------------------------------------------------------------------------- rstin_i : in std_logic; --! Initialisation control, active low
du1_i : in std_logic; --! Strobe
du2_o : out std_logic; --! Acknowledge --! Reset output, active low. Active when the reset variable is received
du3_i : in std_logic --! Write enable --! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
); var_i : in t_var;
rst_o : out std_logic; --! Reset ouput active high
end entity reset_logic;
);
------------------------------------------------------------------------------- end entity reset_logic;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- COMPONENT DECLARATIONS -------------------------------------------------------------------------------
------------------------------------------------------------------------------- --! ARCHITECTURE OF reset_logic
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture rtl of reset_logic is
signal s_rstin_d : std_logic_vector(1 downto 0);
begin
------------------------------------------------------------------------------- process(uclk_i)
-------------------------------------------------------------------------------
--! ARCHITECTURE OF reset_logic
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture rtl of reset_logic is
begin begin
if rising_edge(uclk_i) then
s_rstin_d <= s_rstin_d(0) & (not rstin_i);
if var_i = c_var_array(c_var_reset_pos).c_st_var_reset then
rst_o <= '1';
else
rst_o <= s_rstin_d(1);
end if;
end if;
end process;
end architecture rtl; rston_o <= not rst_o;
-------------------------------------------------------------------------------
-- E N D O F F I L E end architecture rtl;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- E N D O F F I L E
-------------------------------------------------------------------------------
status_gen.vhd
View file @ fb9e6d87
This diff is collapsed.
wf_consumed_vars.vhd
View file @ fb9e6d87
...@@ -78,17 +78,22 @@ port ( ...@@ -78,17 +78,22 @@ port (
-- data_length_i : in std_logic_vector(6 downto 0); -- data_length_i : in std_logic_vector(6 downto 0);
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector(7 downto 0);
var1_access_wb_clk_o: out std_logic; --! Variable 1 access flag
var2_access_wb_clk_o: out std_logic; --! Variable 2 access flag
reset_var1_access_i: in std_logic; --! Reset Variable 1 access flag
reset_var2_access_i: in std_logic; --! Reset Variable 2 access flag
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i --! USER INTERFACE. Data and address lines synchronized with uclk_i
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- dat_i : in std_logic_vector (15 downto 0); --! -- dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
dat_o : out std_logic_vector (15 downto 0); --! wb_dat_o : out std_logic_vector (15 downto 0); --!
adr_i : in std_logic_vector ( 9 downto 0) --! wb_adr_i : in std_logic_vector (9 downto 0); --!
-- stb_p_i : in std_logic; --! Strobe wb_stb_p_i : in std_logic; --! Strobe
-- ack_p_o : out std_logic; --! Acknowledge wb_ack_p_o : out std_logic; --! Acknowledge
-- we_p_i : in std_logic --! Write enable wb_we_p_i : in std_logic --! Write enable
); );
...@@ -114,21 +119,52 @@ signal s_dat_ram : std_logic_vector(7 downto 0); ...@@ -114,21 +119,52 @@ signal s_dat_ram : std_logic_vector(7 downto 0);
signal we_ram_p : std_logic; signal we_ram_p : std_logic;
signal we_byte_p : std_logic_vector(1 downto 0); signal we_byte_p : std_logic_vector(1 downto 0);
signal s_dat : std_logic_vector(15 downto 0); signal s_dat : std_logic_vector(15 downto 0);
signal s_reset_var2_access_clkb, s_var2_access_clkb : std_logic;
signal s_reset_var1_access_clkb, s_var1_access_clkb : std_logic;
begin begin
production_dpram : dpblockram
generic map(dl => 8, -- Length of the data word
al => 7, -- Size of the addr map (10 = 1024 words)
nw => 2**7) -- Number of words
-- 'nw' has to be coherent with 'al'
port map(clk => uclk_i, -- Global Clock consumtion_dpram: dpblockram_clka_rd_clkb_wr
we => we_ram_p, -- Write Enable generic map(c_dl => 8, -- Length of the data word
aw => add(6 downto 0), -- Write Address c_al => 8) -- Number of words
ar => adr_i(6 downto 0), -- Read Address -- 'nw' has to be coherent with 'c_al'
di => byte_i, -- Data input
dw => open, -- Data write, normaly open port map(clka_i => wb_clk_i, -- Global Clock
do => s_dat_ram); -- Data output aa_i => wb_adr_i(7 downto 0),
da_o => s_dat_ram,
clkb_i => uclk_i,
ab_i => add(7 downto 0),
db_i => byte_i,
web_i => we_ram_p);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if unsigned(wb_adr_i(9 downto 8)) = to_unsigned(0, 2) then
wb_ack_p_o <= wb_stb_p_i ;
else
wb_ack_p_o <= '0';
end if;
if unsigned(wb_adr_i(9 downto 7)) = to_unsigned(0, 2) then
s_var1_access_clkb <= wb_stb_p_i ;
elsif s_reset_var1_access_clkb = '1' then
s_var1_access_clkb <= '0' ;
end if;
if unsigned(wb_adr_i(9 downto 7)) = to_unsigned(1, 2) then
s_var2_access_clkb <= wb_stb_p_i ;
elsif s_reset_var2_access_clkb = '1' then
s_var2_access_clkb <= '0' ;
end if;
s_reset_var1_access_clkb <= reset_var1_access_i;
s_reset_var2_access_clkb <= reset_var2_access_i;
end if;
end process;
var1_access_wb_clk_o <= s_var1_access_clkb;
var2_access_wb_clk_o <= s_var2_access_clkb;
add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add)); add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add));
...@@ -174,11 +210,11 @@ begin ...@@ -174,11 +210,11 @@ begin
end process; end process;
process(s_dat, s_dat_ram, slone_i) process(s_dat, s_dat_ram, slone_i)
begin begin
dat_o <= (others => '0'); wb_dat_o <= (others => '0');
if slone_i = '1' then if slone_i = '1' then
dat_o <= s_dat; wb_dat_o <= s_dat;
else else
dat_o(7 downto 0) <= s_dat_ram; wb_dat_o(7 downto 0) <= s_dat_ram;
end if; end if;
end process; end process;
......
wf_package.vhd
View file @ fb9e6d87
...@@ -138,6 +138,20 @@ constant c_var_array : t_var_array(0 to 5):= ...@@ -138,6 +138,20 @@ constant c_var_array : t_var_array(0 to 5):=
array_length => 1, array_length => 1,
byte_array => (0 => x"40", others => x"ff"))); byte_array => (0 => x"40", others => x"ff")));
--Status bit position
constant c_u_cacer_pos : integer := 2; --! Consumed variable access error
constant c_u_pacer_pos : integer := 3; --! Produced variable access error
constant c_r_bner_pos : integer := 4; --! Received bit number error. Replaced by code violation.
constant c_r_fcser_pos : integer := 5; --! Received FCS access error
constant c_t_txer_pos : integer := 6; --! Transmit error (FIELDDRIVE)
constant c_t_wder_pos : integer := 7; --! Watchdog error (FIELDDRIVE)
constant c_refreshment_pos : integer := 0; --! MPS refreshment bit
constant c_significance_pos : integer := 2; --! MPS significance bit
function calc_data_length(var : t_var; function calc_data_length(var : t_var;
p3_length : std_logic_vector(2 downto 0); p3_length : std_logic_vector(2 downto 0);
...@@ -223,6 +237,8 @@ port ( ...@@ -223,6 +237,8 @@ port (
byte_o : out std_logic_vector(7 downto 0); byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic; last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic; fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic; crc_ok_p_o : out std_logic;
d_re_i : in std_logic; d_re_i : in std_logic;
...@@ -263,20 +279,20 @@ end component wf_tx; ...@@ -263,20 +279,20 @@ end component wf_tx;
component dpblockram component dpblockram_clka_rd_clkb_wr
generic (dl : integer := 42; -- Length of the data word generic (c_dl : integer := 42; -- Length of the data word
al : integer := 10; -- Size of the addr map (10 = 1024 words) c_al : integer := 10); -- Number of words
nw : integer := 1024); -- Number of words -- 'nw' has to be coherent with 'c_al'
-- 'nw' has to be coherent with 'al'
port (clk : in std_logic; -- Global Clock port (clka_i : in std_logic; -- Global Clock
we : in std_logic; -- Write Enable aa_i : in std_logic_vector(c_al - 1 downto 0);
aw : in std_logic_vector(al - 1 downto 0); -- Write Address da_o : out std_logic_vector(c_dl -1 downto 0);
ar : in std_logic_vector(al - 1 downto 0); -- Read Address
di : in std_logic_vector(dl - 1 downto 0); -- Data input clkb_i : in std_logic;
dw : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open ab_i : in std_logic_vector(c_al - 1 downto 0);
do : out std_logic_vector(dl - 1 downto 0)); -- Data output db_i : in std_logic_vector(c_dl - 1 downto 0);
end component dpblockram; web_i : in std_logic);
end component dpblockram_clka_rd_clkb_wr;
component wf_engine_control component wf_engine_control
generic( C_QUARTZ_PERIOD : real := 25.0); generic( C_QUARTZ_PERIOD : real := 25.0);
...@@ -380,27 +396,32 @@ port ( ...@@ -380,27 +396,32 @@ port (
-- data_length_i : in std_logic_vector(6 downto 0); -- data_length_i : in std_logic_vector(6 downto 0);
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector(7 downto 0);
var1_access_wb_clk_o: out std_logic; --! Variable 1 access flag
var2_access_wb_clk_o: out std_logic; --! Variable 2 access flag
reset_var1_access_i: in std_logic; --! Reset Variable 1 access flag
reset_var2_access_i: in std_logic; --! Reset Variable 2 access flag
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--! USER INTERFACE. Data and address lines synchronized with uclk_i --! USER INTERFACE. Data and address lines synchronized with uclk_i
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- dat_i : in std_logic_vector (15 downto 0); --! -- dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
dat_o : out std_logic_vector (15 downto 0); --! wb_dat_o : out std_logic_vector (15 downto 0); --!
adr_i : in std_logic_vector ( 9 downto 0) --! wb_adr_i : in std_logic_vector (9 downto 0); --!
-- stb_p_i : in std_logic; --! Strobe wb_stb_p_i : in std_logic; --! Strobe
-- ack_p_o : out std_logic; --! Acknowledge wb_ack_p_o : out std_logic; --! Acknowledge
-- we_p_i : in std_logic --! Write enable wb_we_p_i : in std_logic --! Write enable
); );
end component wf_consumed_vars; end component wf_consumed_vars;
component wf_produced_vars is component wf_produced_vars is
port ( port (
uclk_i : in std_logic; --! User Clock uclk_i : in std_logic; --! User Clock
rst_i : in std_logic; rst_i : in std_logic;
--! Identification selection (see M_ID, C_ID) --! Identification selection (see M_ID, C_ID)
-- s_id_o : out std_logic_vector (1 downto 0); --! Identification selection -- s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
...@@ -431,8 +452,15 @@ port ( ...@@ -431,8 +452,15 @@ port (
--! the produced data. --! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission nostat_i : in std_logic; --! No NanoFIP status transmission
stat_i : in std_logic_vector(7 downto 0); -- NanoFIP status stat_i : in std_logic_vector(7 downto 0); --! NanoFIP status
mps_i : in std_logic_vector(7 downto 0);
sending_stat_o : out std_logic; --! The status register is being adressed
sending_mps_o : out std_logic; --! The status register is being adressed
var3_access_wb_clk_o: out std_logic; --! Variable 2 access flag
reset_var3_access_i: in std_logic; --! Reset Variable 1 access flag
-- prod_byte_i : in std_logic_vector(7 downto 0); -- prod_byte_i : in std_logic_vector(7 downto 0);
var_i : in t_var; var_i : in t_var;
append_status_i : in std_logic; append_status_i : in std_logic;
...@@ -444,16 +472,16 @@ port ( ...@@ -444,16 +472,16 @@ port (
--! USER INTERFACE. Data and address lines synchronized with uclk_i --! USER INTERFACE. Data and address lines synchronized with uclk_i
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
dat_i : in std_logic_vector (15 downto 0); --! wb_dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
-- dat_o : out std_logic_vector (15 downto 0); --! wb_dat_o : out std_logic_vector (15 downto 0); --!
adr_i : in std_logic_vector ( 9 downto 0); --! wb_adr_i : in std_logic_vector (9 downto 0); --!
-- stb_p_i : in std_logic; --! Strobe wb_stb_p_i : in std_logic; --! Strobe
-- ack_p_o : out std_logic; --! Acknowledge wb_ack_p_o : out std_logic; --! Acknowledge
we_p_i : in std_logic --! Write enable wb_we_p_i : in std_logic --! Write enable
); );
end component wf_produced_vars; end component wf_produced_vars;
component wf_tx_rx component wf_tx_rx
...@@ -481,11 +509,71 @@ port ( ...@@ -481,11 +509,71 @@ port (
byte_o : out std_logic_vector(7 downto 0); byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic; last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic; fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic crc_ok_p_o : out std_logic
); );
end component wf_tx_rx; end component wf_tx_rx;
component status_gen
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_tx_rx (WorldFIP received data)
-------------------------------------------------------------------------------
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
code_violation_p_i : in std_logic;
crc_bad_p_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_engine
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_i: in std_logic; --! Variable 1 ready
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_i: in std_logic; --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_i: in std_logic; --! Variable 3 ready
var1_access_a_i: in std_logic; --! Variable 1 access
var2_access_a_i: in std_logic; --! Variable 2 access
var3_access_a_i: in std_logic; --! Variable 3 access
reset_var1_access_o : out std_logic; --! Reset Variable 1 access flag
reset_var2_access_o : out std_logic; --! Reset Variable 2 access flag
reset_var3_access_o : out std_logic; --! Reset Variable 2 access flag
stat_sent_p_i : in std_logic;
mps_sent_p_i : in std_logic;
stat_o : out std_logic_vector(7 downto 0);
mps_o : out std_logic_vector(7 downto 0)
-------------------------------------------------------------------------------
-- Connections to data_if
-------------------------------------------------------------------------------
);
end component status_gen;
component nanofip component nanofip
......
wf_produced_vars.vhd
View file @ fb9e6d87
...@@ -95,8 +95,15 @@ port ( ...@@ -95,8 +95,15 @@ port (
--! the produced data. --! the produced data.
nostat_i : in std_logic; --! No NanoFIP status transmission nostat_i : in std_logic; --! No NanoFIP status transmission
stat_i : in std_logic_vector(7 downto 0); -- NanoFIP status stat_i : in std_logic_vector(7 downto 0); --! NanoFIP status
mps_i : in std_logic_vector(7 downto 0);
sending_stat_o : out std_logic; --! The status register is being adressed
sending_mps_o : out std_logic; --! The status register is being adressed
var3_access_wb_clk_o: out std_logic; --! Variable 2 access flag
reset_var3_access_i: in std_logic; --! Reset Variable 1 access flag
-- prod_byte_i : in std_logic_vector(7 downto 0); -- prod_byte_i : in std_logic_vector(7 downto 0);
var_i : in t_var; var_i : in t_var;
append_status_i : in std_logic; append_status_i : in std_logic;
...@@ -108,13 +115,15 @@ port ( ...@@ -108,13 +115,15 @@ port (
--! USER INTERFACE. Data and address lines synchronized with uclk_i --! USER INTERFACE. Data and address lines synchronized with uclk_i
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
dat_i : in std_logic_vector (15 downto 0); --! wb_dat_i : in std_logic_vector (15 downto 0); --!
wb_clk_i : in std_logic;
wb_dat_o : out std_logic_vector (15 downto 0); --!
wb_adr_i : in std_logic_vector (9 downto 0); --!
wb_stb_p_i : in std_logic; --! Strobe
wb_ack_p_o : out std_logic; --! Acknowledge
wb_we_p_i : in std_logic --! Write enable
-- dat_o : out std_logic_vector (15 downto 0); --!
adr_i : in std_logic_vector ( 9 downto 0); --!
-- stb_p_i : in std_logic; --! Strobe
-- ack_p_o : out std_logic; --! Acknowledge
we_p_i : in std_logic --! Write enable
); );
...@@ -139,22 +148,62 @@ signal s_byte: std_logic_vector(7 downto 0); ...@@ -139,22 +148,62 @@ signal s_byte: std_logic_vector(7 downto 0);
signal s_mem_byte : std_logic_vector(7 downto 0); signal s_mem_byte : std_logic_vector(7 downto 0);
signal s_io_byte : std_logic_vector(7 downto 0); signal s_io_byte : std_logic_vector(7 downto 0);
signal base_add, add: std_logic_vector(9 downto 0); signal base_add, add: std_logic_vector(9 downto 0);
signal s_wb_we : std_logic;
signal s_reset_var3_access_clkb, s_var3_access_clkb : std_logic;
begin begin
production_dpram : dpblockram
generic map(dl => 8, -- Length of the data word
al => 7, -- Size of the addr map (10 = 1024 words)
nw => 2**7) -- Number of words
-- 'nw' has to be coherent with 'al'
port map(clk => uclk_i, -- Global Clock
we => we_p_i, -- Write Enable production_dpram: dpblockram_clka_rd_clkb_wr
aw => adr_i(6 downto 0), -- Write Address generic map(c_dl => 8, -- Length of the data word
ar => add(6 downto 0), -- Read Address c_al => 7) -- Number of words
di => dat_i(7 downto 0), -- Data input -- 'nw' has to be coherent with 'c_al'
dw => open, -- Data write, normaly open
do => s_mem_byte); -- Data output port map(clka_i => uclk_i, -- Global Clock
aa_i => add(6 downto 0),
da_o => s_mem_byte,
clkb_i => wb_clk_i,
ab_i => wb_adr_i(6 downto 0),
db_i => wb_dat_i(7 downto 0),
web_i => wb_we_p_i);
s_wb_we <= wb_stb_p_i and wb_we_p_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_adr_i(9 downto 7) = "010" then
wb_ack_p_o <= s_wb_we and wb_stb_p_i;
else
wb_ack_p_o <= '0';
end if;
if unsigned(wb_adr_i(9 downto 7)) = to_unsigned(2, 2) then
s_var3_access_clkb <= s_wb_we and wb_stb_p_i;
elsif s_reset_var3_access_clkb = '1' then
s_var3_access_clkb <= '0' ;
end if;
s_reset_var3_access_clkb <= reset_var3_access_i;
end if;
end process;
var3_access_wb_clk_o <= s_var3_access_clkb;
-- production_dpram : dpblockram
-- generic map(dl => 8, -- Length of the data word
-- al => 7, -- Size of the addr map (10 = 1024 words)
-- nw => 2**7) -- Number of words
-- -- 'nw' has to be coherent with 'al'
--
-- port map(clk => uclk_i, -- Global Clock
-- we => we_p_i, -- Write Enable
-- aw => adr_i(6 downto 0), -- Write Address
-- ar => add(6 downto 0), -- Read Address
-- di => dat_i(7 downto 0), -- Data input
-- dw => open, -- Data write, normaly open
-- do => s_mem_byte); -- Data output
-- For the moment there is only one variable produced, but I think it is nice to have -- For the moment there is only one variable produced, but I think it is nice to have
-- defined an offset for every variable in case we produce more variables in the future -- defined an offset for every variable in case we produce more variables in the future
...@@ -164,7 +213,9 @@ add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add)); ...@@ -164,7 +213,9 @@ add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add));
process(s_mem_byte, var_i, add_offset_i, s_io_byte, data_length_i, append_status_i, stat_i, slone_i, c_id_i, m_id_i) process(s_mem_byte, var_i, add_offset_i, s_io_byte, data_length_i, append_status_i, stat_i, slone_i, c_id_i, m_id_i)
begin begin
s_byte <= (others => '0'); s_byte <= (others => '0');
base_add <= (others => '0'); base_add <= (others => '0');
sending_stat_o <= '0';
sending_mps_o <= '0';
for I in c_var_array'range loop for I in c_var_array'range loop
if (c_var_array(I).response = produce) then if (c_var_array(I).response = produce) then
if c_var_array(I).var = var_i then if c_var_array(I).var = var_i then
...@@ -182,8 +233,12 @@ begin ...@@ -182,8 +233,12 @@ begin
s_byte <= c_var_array(I).byte_array(to_integer(unsigned(add_offset_i(3 downto 0)))); s_byte <= c_var_array(I).byte_array(to_integer(unsigned(add_offset_i(3 downto 0))));
elsif unsigned(add_offset_i) = c_var_length_add then elsif unsigned(add_offset_i) = c_var_length_add then
s_byte(data_length_i'range) <= data_length_i; s_byte(data_length_i'range) <= data_length_i;
elsif (unsigned(add_offset_i) = unsigned(data_length_i)) and append_status_i = '1' then elsif (unsigned(add_offset_i) = (unsigned(data_length_i) - 1)) and append_status_i = '1' then
s_byte <= stat_i; s_byte <= stat_i;
sending_stat_o <= '1';
elsif (unsigned(add_offset_i) = unsigned(data_length_i)) then
s_byte <= mps_i;
sending_mps_o <= '1';
elsif unsigned(add_offset_i) < c_var_array(I).array_length then elsif unsigned(add_offset_i) < c_var_array(I).array_length then
s_byte <= s_mem_byte; s_byte <= s_mem_byte;
elsif slone_i = '1' then elsif slone_i = '1' then
...@@ -197,7 +252,7 @@ begin ...@@ -197,7 +252,7 @@ begin
end loop; end loop;
end process; end process;
s_io_byte <= dat_i(15 downto 8) when add_offset_i(0) = '1' else dat_i(7 downto 0); s_io_byte <= wb_dat_i(15 downto 8) when add_offset_i(0) = '1' else wb_dat_i(7 downto 0);
byte_o <= s_byte; byte_o <= s_byte;
end architecture rtl; end architecture rtl;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
wf_rx.vhd
View file @ fb9e6d87
...@@ -74,7 +74,9 @@ port ( ...@@ -74,7 +74,9 @@ port (
byte_ready_p_o : out std_logic; byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0); byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic; last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic; fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic; crc_ok_p_o : out std_logic;
d_re_i : in std_logic; d_re_i : in std_logic;
d_fe_i : in std_logic; d_fe_i : in std_logic;
...@@ -252,7 +254,7 @@ begin ...@@ -252,7 +254,7 @@ begin
s_start_pointer <= to_unsigned(0,s_start_pointer'length); s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_start_crc_p <= '0'; s_start_crc_p <= '0';
fss_decoded_p_o <= '0'; fss_decoded_p_o <= '0';
code_violation_p_o <= '0';
case rx_st is case rx_st is
when w_1 => when w_1 =>
load_phase_o <= '1'; load_phase_o <= '1';
...@@ -270,7 +272,9 @@ case rx_st is ...@@ -270,7 +272,9 @@ case rx_st is
s_start_pointer <= to_unsigned(QUEUE'left,s_start_pointer'length); s_start_pointer <= to_unsigned(QUEUE'left,s_start_pointer'length);
s_load_pointer <= s_pointer_is_zero and s_clk_bit_180_p_d; s_load_pointer <= s_pointer_is_zero and s_clk_bit_180_p_d;
s_start_crc_p <= '1'; s_start_crc_p <= '1';
fss_decoded_p_o <= s_last_frame_start_bit; fss_decoded_p_o <= s_last_frame_start_bit;
code_violation_p_o <= s_bad_queue_bit and s_code_violation;
when w_byte => when w_byte =>
load_phase_o <= edge_window_i; load_phase_o <= edge_window_i;
s_inc_pointer <= s_d_ready_p_i; s_inc_pointer <= s_d_ready_p_i;
...@@ -344,8 +348,8 @@ end process; ...@@ -344,8 +348,8 @@ end process;
process(uclk_i) process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if rst_i = '1' then
s_crc_ok <= '0'; s_crc_ok <= '0';
elsif s_byte_ok = '1' then elsif s_byte_ok = '1' then
s_crc_ok <= '0'; s_crc_ok <= '0';
...@@ -370,7 +374,7 @@ end process; ...@@ -370,7 +374,7 @@ end process;
byte_o <= s_byte; byte_o <= s_byte;
last_byte_p_o <= s_good_queue_detected_p; last_byte_p_o <= s_good_queue_detected_p;
crc_ok_p_o <= s_good_queue_detected_p and s_crc_ok; crc_ok_p_o <= s_good_queue_detected_p and s_crc_ok;
crc_bad_p_o <= s_good_queue_detected_p and (not s_crc_ok);
end architecture rtl; end architecture rtl;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
wf_tx_rx.vhd
View file @ fb9e6d87
...@@ -87,8 +87,10 @@ port ( ...@@ -87,8 +87,10 @@ port (
byte_ready_p_o : out std_logic; byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0); byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic; last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic; fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic;
crc_bad_p_o : out std_logic;
crc_ok_p_o : out std_logic crc_ok_p_o : out std_logic
); );
...@@ -156,7 +158,7 @@ s_d_edge <= s_d_fe or s_d_re; ...@@ -156,7 +158,7 @@ s_d_edge <= s_d_fe or s_d_re;
rst_i => rst_i, rst_i => rst_i,
byte_ready_p_o => byte_ready_p_o, byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o, byte_o => byte_o,
last_byte_p_o => last_byte_p_o, last_byte_p_o => last_byte_p_o,
fss_decoded_p_o => fss_decoded_p_o, fss_decoded_p_o => fss_decoded_p_o,
crc_ok_p_o => crc_ok_p_o, crc_ok_p_o => crc_ok_p_o,
......
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