OpenDSO - Open Digital Storage Oscilloscope
Project description
The OpenDSO is an open hardware bench top oscilloscope, built on top of an extensible Zynq-based platform.
Features:
- 2x100 MS/s (basic frontend), extendable to 4x1GS/s or 2x2GS/s
- Zynq 7000 FPGA, 512 MB RAM
- 8'' multitouch display with Qt GUI
Below is only a template. Please update using the recommended setup and usage guide
Main Features
-
2x100 MS/s (basic frontend)
- extendable to 4x1GS/s or 2x2GS/s
-
FPGA: Zynq 7000
-
Memory: 512 MB RAM
-
8" multitouch display with Qt GUI
- 4-lane PCIe (Gennum GN4124) obsolete component, not available anymore
- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C) (PCI Device ID: 0x18D)
- special versions with XC6SLX100T and XC6SLX150T available
- FMC slot with low pin count (LPC) connector
- Vadj fixed to 2.5V
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
- No dedicated clock signals from Carrier to FMC (only available on HPC pins)
- Stand-alone features
- External 12V power supply connector
- mini USB connector
- 4 LEDs
- 2 buttons
- Power consumption: 5-12 Watt, depending on application
- Optimised for cost
- 6-layer PCB
- Optional cooling fan for the mezzanine.
Project information
- Official production documentation: EDMS EDA-02189
- Users
- Software
- Fan design
- Frequently Asked Questions
Releases
- Hardware
Contacts
Commercial producers
- None yet
General questions about project
- Tomasz Wlostowski - CERN
Status
Date | Event |
---|---|
25-06-2019 | Start working on project. Collecting main specifications. |
25 June 2019