pci_target: fix invalid UTF-8 character in comment

b9a237ef · Michael Reese · c374da19 · b9a237ef
Commit b9a237ef authored Jan 07, 2021 by Michael Reese
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pci_target32_sm.v src/hdl/verilog/pci_target32_sm.v +1 -1

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--- a/src/hdl/verilog/pci_target32_sm.v
+++ b/src/hdl/verilog/pci_target32_sm.v
@@ -246,7 +246,7 @@ input			disconect_w_data_in ;		// Indicates disconnect with data termination
 input           pciw_fifo_full_in ;         // Indicates that write PCIW_FIFO is full
 input           pcir_fifo_data_err_in ;     // Indicates data error on current data read from PCIR_FIFO
 input           wbw_fifo_empty_in ;         // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
-input			wbu_del_read_comp_pending_in ; // Indicates that WB SÈAVE UNIT has a delayed read pending
+input			wbu_del_read_comp_pending_in ; // Indicates that WB SLAVE UNIT has a delayed read pending
 input           wbu_frame_en_in ;           // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if
                                            //   address on PCI bus is also claimed by decoder in this PCI TARGET UNIT
 output          target_abort_set_out ;      // Signal used to be set in configuration space registers