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Commit 4ec34a29 authored by li hongming's avatar li hongming
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split the ptp mode for dualports. 

    Todo:
	1. Reconsider the clock class status.
	2. Reconsider the ptp role of dualports.
parent f13b2ae9
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Showing with 59 additions and 95 deletions
arch-wrpc/wrc_ptp_ppsi.c
View file @ 4ec34a29
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
extern int32_t cal_phase_transition[wr_num_ports]; extern int32_t cal_phase_transition[wr_num_ports];
int ptp_mode = WRC_MODE_UNKNOWN; int ptp_mode[2];
static int ptp_enabled[wr_num_ports]; static int ptp_enabled[wr_num_ports];
static struct wr_operations wrpc_wr_operations = { static struct wr_operations wrpc_wr_operations = {
...@@ -125,6 +125,7 @@ int wrc_ptp_init() ...@@ -125,6 +125,7 @@ int wrc_ptp_init()
for (port = 0; port < wr_num_ports; ++port) for (port = 0; port < wr_num_ports; ++port)
{ {
ptp_mode[port] = WRC_MODE_UNKNOWN;
ppg->pp_instances[port] = ppi_static[port]; ppg->pp_instances[port] = ppi_static[port];
ptp_enabled[port] = 0; ptp_enabled[port] = 0;
} }
...@@ -136,18 +137,15 @@ int wrc_ptp_init() ...@@ -136,18 +137,15 @@ int wrc_ptp_init()
#define LOCK_TIMEOUT_FM (4 * TICS_PER_SECOND) #define LOCK_TIMEOUT_FM (4 * TICS_PER_SECOND)
#define LOCK_TIMEOUT_GM (60 * TICS_PER_SECOND) #define LOCK_TIMEOUT_GM (60 * TICS_PER_SECOND)
int wrc_ptp_set_mode(int mode) int wrc_ptp_set_mode(int mode, int port)
{ {
uint32_t start_tics, lock_timeout = 0; uint32_t start_tics, lock_timeout = 0;
struct pp_globals *ppg = &ppg_static; struct pp_globals *ppg = &ppg_static;
struct pp_instance *ppi[wr_num_ports]; struct pp_instance *ppi;
struct wr_dsport *wrp[wr_num_ports]; struct wr_dsport *wrp;
int port;
for (port = 0; port < wr_num_ports; ++port) ppi = INST(ppg, port);
{ wrp = WR_DSPOR(ppi);
ppi[port] = INST(ppg, port);
wrp[port] = WR_DSPOR(ppi[port]);
}
typeof(ppg->rt_opts->clock_quality.clockClass) *class_ptr; typeof(ppg->rt_opts->clock_quality.clockClass) *class_ptr;
int error = 0; int error = 0;
...@@ -157,54 +155,40 @@ int wrc_ptp_set_mode(int mode) ...@@ -157,54 +155,40 @@ int wrc_ptp_set_mode(int mode)
*/ */
class_ptr = &__pp_default_rt_opts.clock_quality.clockClass; class_ptr = &__pp_default_rt_opts.clock_quality.clockClass;
ptp_mode = 0; ptp_mode[port] = WRC_MODE_UNKNOWN;
for (port = 0; port < wr_num_ports; ++port) { wrc_ptp_stop(port);
wrc_ptp_stop(port); ppi->cfg.ext = PPSI_EXT_WR; // Enable WR mode
ppi[port]->cfg.ext = PPSI_EXT_WR; // Enable WR mode
}
switch (mode) { switch (mode) {
case WRC_MODE_GM: case WRC_MODE_GM:
case WRC_MODE_ABSCAL: /* absolute calibration, gm-lookalike */ case WRC_MODE_ABSCAL: /* absolute calibration, gm-lookalike */
for (port = 0; port < wr_num_ports; ++port) { wrp->wrConfig = WR_M_ONLY;
wrp[port]->wrConfig = WR_M_ONLY; ppi->role = PPSI_ROLE_MASTER;
ppi[port]->role = PPSI_ROLE_MASTER;
}
*class_ptr = PP_CLASS_WR_GM_LOCKED; *class_ptr = PP_CLASS_WR_GM_LOCKED;
spll_init(SPLL_MODE_GRAND_MASTER, 0, 1); spll_init(SPLL_MODE_GRAND_MASTER, 0, 1);
shw_pps_gen_unmask_output(1); shw_pps_gen_unmask_output(1);
lock_timeout = LOCK_TIMEOUT_GM; lock_timeout = LOCK_TIMEOUT_GM;
for (port = 0; port < wr_num_ports; ++port) { DSDEF(ppi)->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED; m1(ppi); // port0 and por1 share one pp_global
}
m1(ppi[0]); // port0 and por1 share one pp_global
break; break;
case WRC_MODE_MASTER: case WRC_MODE_MASTER:
for (port = 0; port < wr_num_ports; ++port) { wrp->wrConfig = WR_M_ONLY;
wrp[port]->wrConfig = WR_M_ONLY; ppi->role = PPSI_ROLE_MASTER;
ppi[port]->role = PPSI_ROLE_MASTER;
}
*class_ptr = PP_CLASS_DEFAULT; *class_ptr = PP_CLASS_DEFAULT;
spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1); spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1);
shw_pps_gen_unmask_output(1); shw_pps_gen_unmask_output(1);
lock_timeout = LOCK_TIMEOUT_FM; lock_timeout = LOCK_TIMEOUT_FM;
for (port = 0; port < wr_num_ports; ++port) { DSDEF(ppi)->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED; m1(ppi);
}
m1(ppi[0]);
break; break;
case WRC_MODE_SLAVE: case WRC_MODE_SLAVE:
wrp[0]->wrConfig = WR_S_ONLY; wrp->wrConfig = WR_S_ONLY;
ppi[0]->role = PPSI_ROLE_SLAVE; ppi->role = PPSI_ROLE_SLAVE;
if (wr_num_ports>1)
{
wrp[1]->wrConfig = WR_M_ONLY;
ppi[1]->role = PPSI_ROLE_MASTER;
}
// *class_ptr = PP_CLASS_SLAVE_ONLY; // *class_ptr = PP_CLASS_SLAVE_ONLY;
*class_ptr = PP_CLASS_DEFAULT; *class_ptr = PP_CLASS_DEFAULT;
spll_init(SPLL_MODE_SLAVE, 0, 1); spll_init(SPLL_MODE_SLAVE, 0, 1);
...@@ -215,7 +199,7 @@ int wrc_ptp_set_mode(int mode) ...@@ -215,7 +199,7 @@ int wrc_ptp_set_mode(int mode)
start_tics = timer_get_tics(); start_tics = timer_get_tics();
pp_printf("Locking PLL"); pp_printf("Locking PLL");
wrp[0]->ops->enable_timing_output(ppi[0], 0); /* later, wr_init chooses */ wrp->ops->enable_timing_output(ppi, 0); /* later, wr_init chooses */
while (!spll_check_lock(0) && lock_timeout) { while (!spll_check_lock(0) && lock_timeout) {
spll_update(); spll_update();
...@@ -233,18 +217,18 @@ int wrc_ptp_set_mode(int mode) ...@@ -233,18 +217,18 @@ int wrc_ptp_set_mode(int mode)
if (error && mode == WRC_MODE_GM) if (error && mode == WRC_MODE_GM)
*class_ptr = PP_CLASS_WR_GM_UNLOCKED; *class_ptr = PP_CLASS_WR_GM_UNLOCKED;
ptp_mode = mode; ptp_mode[port] = mode;
return error; return error;
} }
int wrc_ptp_get_mode() int wrc_ptp_get_mode(int port)
{ {
return ptp_mode; return ptp_mode[port];
} }
int wrc_ptp_sync_mech(int e2e_p2p_qry) int wrc_ptp_sync_mech(int e2e_p2p_qry, int port)
{ {
struct pp_instance *ppi = &ppi_static[0]; struct pp_instance *ppi = &ppi_static[port];
int running; int running;
if (!CONFIG_HAS_P2P) if (!CONFIG_HAS_P2P)
...@@ -253,10 +237,10 @@ int wrc_ptp_sync_mech(int e2e_p2p_qry) ...@@ -253,10 +237,10 @@ int wrc_ptp_sync_mech(int e2e_p2p_qry)
switch(e2e_p2p_qry) { switch(e2e_p2p_qry) {
case PP_E2E_MECH: case PP_E2E_MECH:
case PP_P2P_MECH: case PP_P2P_MECH:
running = wrc_ptp_run(-1); running = wrc_ptp_run(-1, port);
wrc_ptp_run(0); wrc_ptp_run(0, port);
ppi->mech = e2e_p2p_qry; ppi->mech = e2e_p2p_qry;
wrc_ptp_run(running); wrc_ptp_run(running, port);
return 0; return 0;
default: default:
return ppi->mech; return ppi->mech;
...@@ -277,11 +261,7 @@ int wrc_ptp_start(int port) ...@@ -277,11 +261,7 @@ int wrc_ptp_start(int port)
start_tics[port] = timer_get_tics(); start_tics[port] = timer_get_tics();
WR_DSPOR(ppi)->linkUP = FALSE; WR_DSPOR(ppi)->linkUP = FALSE;
wr_servo_reset(ppi); wr_servo_reset(ppi);
switch(port) { ptp_enabled[port] = 1;
case 0: ptp_enabled[port] = 1; break;
case 1: ptp_enabled[port] = 2; break;
default:ptp_enabled[port] = 1;
}
return 0; return 0;
} }
...@@ -306,34 +286,17 @@ int wrc_ptp_stop(int port) ...@@ -306,34 +286,17 @@ int wrc_ptp_stop(int port)
return 0; return 0;
} }
int wrc_ptp_run(int start_stop_query) int wrc_ptp_run(int start_stop_query, int port)
{ {
int port;
int ptp_enabled_sum=0;
switch(start_stop_query) { switch(start_stop_query) {
case 0: case 0:
for (port = 0; port < wr_num_ports; ++port){ wrc_ptp_stop(port);
wrc_ptp_stop(port);
}
return 0; return 0;
case 1: case 1:
wrc_ptp_start(0); wrc_ptp_start(port);
if(wr_num_ports>1)wrc_ptp_stop(1);
return 0;
case 2:
wrc_ptp_stop(0);
if(wr_num_ports>1)wrc_ptp_start(1);
return 0;
case 3:
for (port = 0; port < wr_num_ports; ++port){
wrc_ptp_start(port);
}
return 0; return 0;
default: default:
for (port = 0; port < wr_num_ports; ++port){ return ptp_enabled[port];
ptp_enabled_sum += ptp_enabled[port];
}
return ptp_enabled_sum;
} }
} }
......
arch-wrpc/wrpc.h
View file @ 4ec34a29
...@@ -19,15 +19,15 @@ ...@@ -19,15 +19,15 @@
#define WRC_MODE_MASTER 2 #define WRC_MODE_MASTER 2
#define WRC_MODE_SLAVE 3 #define WRC_MODE_SLAVE 3
#define WRC_MODE_ABSCAL 4 #define WRC_MODE_ABSCAL 4
extern int ptp_mode; extern int ptp_mode[2];
int wrc_ptp_init(void); int wrc_ptp_init(void);
int wrc_ptp_set_mode(int mode); int wrc_ptp_set_mode(int mode, int port);
int wrc_ptp_get_mode(void); int wrc_ptp_get_mode(int port);
int wrc_ptp_sync_mech(int e2e_p2p_qry); int wrc_ptp_sync_mech(int e2e_p2p_qry, int port);
int wrc_ptp_start(int port); int wrc_ptp_start(int port);
int wrc_ptp_stop(int port); int wrc_ptp_stop(int port);
int wrc_ptp_run(int start_stop_qry); int wrc_ptp_run(int start_stop_qry, int port);
int wrc_ptp_update(void); int wrc_ptp_update(void);
/* End of wrc-ptp.h */ /* End of wrc-ptp.h */
......
proto-ext-whiterabbit/state-wr-link-on.c
View file @ 4ec34a29
...@@ -39,10 +39,10 @@ int wr_link_on(struct pp_instance *ppi, unsigned char *pkt, int plen) ...@@ -39,10 +39,10 @@ int wr_link_on(struct pp_instance *ppi, unsigned char *pkt, int plen)
* absolute calibration only exists in arch-wrpc, so far, but * absolute calibration only exists in arch-wrpc, so far, but
* we can't include wrpc headers, not available in wrs builds * we can't include wrpc headers, not available in wrs builds
*/ */
extern int ptp_mode; extern int ptp_mode[2];
extern int ep_get_bitslide(int port); extern int ep_get_bitslide(int port);
if (ptp_mode == 4 /* WRC_MODE_ABSCAL */) { if (ptp_mode[port] == 4 /* WRC_MODE_ABSCAL */) {
ppi->next_state = WRS_ABSCAL; ppi->next_state = WRS_ABSCAL;
/* print header for the serial port stream of stamps */ /* print header for the serial port stream of stamps */
pp_printf("### t4.phase is already corrected for bitslide\n"); pp_printf("### t4.phase is already corrected for bitslide\n");
......
proto-standard/state-initializing.c
View file @ 4ec34a29
...@@ -39,9 +39,10 @@ static void init_parent_ds(struct pp_instance *ppi) ...@@ -39,9 +39,10 @@ static void init_parent_ds(struct pp_instance *ppi)
int pp_initializing(struct pp_instance *ppi, unsigned char *pkt, int plen) int pp_initializing(struct pp_instance *ppi, unsigned char *pkt, int plen)
{ {
unsigned char *id, *mac; unsigned char *id, *mac;
struct DSPort *port = DSPOR(ppi); struct DSPort *dsport = DSPOR(ppi);
struct pp_runtime_opts *opt = OPTS(ppi); struct pp_runtime_opts *opt = OPTS(ppi);
int ret = 0; int ret = 0;
int port = atoi(&ppi->iface_name[2]);
if (ppi->n_ops->init(ppi) < 0) /* it must handle being called twice */ if (ppi->n_ops->init(ppi) < 0) /* it must handle being called twice */
goto failure; goto failure;
...@@ -66,17 +67,17 @@ int pp_initializing(struct pp_instance *ppi, unsigned char *pkt, int plen) ...@@ -66,17 +67,17 @@ int pp_initializing(struct pp_instance *ppi, unsigned char *pkt, int plen)
init_parent_ds(ppi); init_parent_ds(ppi);
/* /*
* Initialize port data set * Initialize dsport data set
*/ */
memcpy(&port->portIdentity.clockIdentity, memcpy(&dsport->portIdentity.clockIdentity,
&DSDEF(ppi)->clockIdentity, PP_CLOCK_IDENTITY_LENGTH); &DSDEF(ppi)->clockIdentity, PP_CLOCK_IDENTITY_LENGTH);
/* 1-based port number = index of this ppi in the global array */ /* 1-based dsport number = index of this ppi in the global array */
port->portIdentity.portNumber = 1 + ppi - ppi->glbs->pp_instances; dsport->portIdentity.portNumber = 1 + ppi - ppi->glbs->pp_instances;
port->logMinDelayReqInterval = PP_DEFAULT_DELAYREQ_INTERVAL; dsport->logMinDelayReqInterval = PP_DEFAULT_DELAYREQ_INTERVAL;
port->logAnnounceInterval = opt->announce_intvl; dsport->logAnnounceInterval = opt->announce_intvl;
port->announceReceiptTimeout = PP_DEFAULT_ANNOUNCE_RECEIPT_TIMEOUT; dsport->announceReceiptTimeout = PP_DEFAULT_ANNOUNCE_RECEIPT_TIMEOUT;
port->logSyncInterval = opt->sync_intvl; dsport->logSyncInterval = opt->sync_intvl;
port->versionNumber = PP_VERSION_PTP; dsport->versionNumber = PP_VERSION_PTP;
pp_timeout_init(ppi); pp_timeout_init(ppi);
if (pp_hooks.init) if (pp_hooks.init)
...@@ -100,8 +101,8 @@ int pp_initializing(struct pp_instance *ppi, unsigned char *pkt, int plen) ...@@ -100,8 +101,8 @@ int pp_initializing(struct pp_instance *ppi, unsigned char *pkt, int plen)
#ifdef CONFIG_ABSCAL #ifdef CONFIG_ABSCAL
/* absolute calibration only exists in arch-wrpc, so far */ /* absolute calibration only exists in arch-wrpc, so far */
extern int ptp_mode; extern int ptp_mode[2];
if (ptp_mode == 4 /* WRC_MODE_ABSCAL */) if (ptp_mode[port] == 4 /* WRC_MODE_ABSCAL */)
ppi->next_state = WRS_WR_LINK_ON; ppi->next_state = WRS_WR_LINK_ON;
#endif #endif
......
time-wrpc/wrpc-socket.c
View file @ 4ec34a29
...@@ -80,7 +80,7 @@ static int wrpc_net_recv(struct pp_instance *ppi, void *pkt, int len, ...@@ -80,7 +80,7 @@ static int wrpc_net_recv(struct pp_instance *ppi, void *pkt, int len,
t->scaled_nsecs += wr_ts.phase * (1 << 16) / 1000; t->scaled_nsecs += wr_ts.phase * (1 << 16) / 1000;
/* avoid "incorrect" stamps when abscal is running */ /* avoid "incorrect" stamps when abscal is running */
if (!wr_ts.correct if (!wr_ts.correct
&& (!HAS_ABSCAL || ptp_mode != WRC_MODE_ABSCAL)) && (!HAS_ABSCAL || ptp_mode[port] != WRC_MODE_ABSCAL))
mark_incorrect(t); mark_incorrect(t);
} }
...@@ -90,7 +90,7 @@ static int wrpc_net_recv(struct pp_instance *ppi, void *pkt, int len, ...@@ -90,7 +90,7 @@ static int wrpc_net_recv(struct pp_instance *ppi, void *pkt, int len,
if (pp_diag_allow(ppi, frames, 2)) if (pp_diag_allow(ppi, frames, 2))
dump_payloadpkt("recv: ", pkt, got, t); dump_payloadpkt("recv: ", pkt, got, t);
#endif #endif
if (HAS_ABSCAL && ptp_mode == WRC_MODE_ABSCAL) { if (HAS_ABSCAL && ptp_mode[port] == WRC_MODE_ABSCAL) {
struct pp_time t4, t_bts; struct pp_time t4, t_bts;
int bitslide; int bitslide;
...@@ -163,7 +163,7 @@ static int wrpc_net_send(struct pp_instance *ppi, void *pkt, int len, ...@@ -163,7 +163,7 @@ static int wrpc_net_send(struct pp_instance *ppi, void *pkt, int len,
__func__, snt, (long)t->secs, __func__, snt, (long)t->secs,
(long)(t->scaled_nsecs >> 16)); (long)(t->scaled_nsecs >> 16));
} }
if (HAS_ABSCAL && ptp_mode == WRC_MODE_ABSCAL) if (HAS_ABSCAL && ptp_mode[port] == WRC_MODE_ABSCAL)
pp_printf("%09d %09d %03d ", /* first half of a line */ pp_printf("%09d %09d %03d ", /* first half of a line */
(int)t->secs, (int)(t->scaled_nsecs >> 16), (int)t->secs, (int)(t->scaled_nsecs >> 16),
((int)(t->scaled_nsecs & 0xffff) * 1000) >> 16); ((int)(t->scaled_nsecs & 0xffff) * 1000) >> 16);
......
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