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PPSi
Commit e3a99db4 authored by li hongming's avatar li hongming
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Add a new mode "cascaded" for dualport. 

    Separate the PPS_out with time_valid.
parent 4e567b8e
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Showing with 95 additions and 53 deletions
arch-wrpc/wrc_ptp_ppsi.c
View file @ e3a99db4
...@@ -141,11 +141,13 @@ int wrc_ptp_set_mode(int mode, int port) ...@@ -141,11 +141,13 @@ int wrc_ptp_set_mode(int mode, int port)
{ {
uint32_t start_tics, lock_timeout = 0; uint32_t start_tics, lock_timeout = 0;
struct pp_globals *ppg = &ppg_static; struct pp_globals *ppg = &ppg_static;
struct pp_instance *ppi; struct pp_instance *ppi[wr_num_ports];
struct wr_dsport *wrp; struct wr_dsport *wrp[wr_num_ports];
ppi = INST(ppg, port); for (port=0; port<wr_num_ports;port++) {
wrp = WR_DSPOR(ppi); ppi[port] = INST(ppg, port);
wrp[port] = WR_DSPOR(ppi[port]);
}
typeof(ppg->rt_opts->clock_quality.clockClass) *class_ptr; typeof(ppg->rt_opts->clock_quality.clockClass) *class_ptr;
int error = 0; int error = 0;
...@@ -155,57 +157,75 @@ int wrc_ptp_set_mode(int mode, int port) ...@@ -155,57 +157,75 @@ int wrc_ptp_set_mode(int mode, int port)
*/ */
class_ptr = &__pp_default_rt_opts.clock_quality.clockClass; class_ptr = &__pp_default_rt_opts.clock_quality.clockClass;
ptp_mode[port] = WRC_MODE_UNKNOWN; for (port=0; port<wr_num_ports;port++) {
ptp_mode[port] = WRC_MODE_UNKNOWN;
wrc_ptp_stop(port); ptp_enabled[port] = 0;
ppi->cfg.ext = PPSI_EXT_WR; // Enable WR mode wr_servo_reset(ppi[port]);
ppi[port]->cfg.ext = PPSI_EXT_WR; // Enable WR mode
}
switch (mode) { switch (mode) {
case WRC_MODE_GM: case WRC_MODE_GM:
case WRC_MODE_ABSCAL: /* absolute calibration, gm-lookalike */ case WRC_MODE_ABSCAL: /* absolute calibration, gm-lookalike */
wrp->wrConfig = WR_M_ONLY; for (port=0; port<wr_num_ports;port++) {
ppi->role = PPSI_ROLE_MASTER; wrp[port]->wrConfig = WR_M_ONLY;
ppi[port]->role = PPSI_ROLE_MASTER;
DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
m1(ppi[port]); // port0 and por1 share one pp_global
}
*class_ptr = PP_CLASS_WR_GM_LOCKED; *class_ptr = PP_CLASS_WR_GM_LOCKED;
spll_init(SPLL_MODE_GRAND_MASTER, 0, 1);
shw_pps_gen_unmask_output(1); shw_pps_gen_unmask_output(1);
spll_init(SPLL_MODE_GRAND_MASTER, 0, 1);
lock_timeout = LOCK_TIMEOUT_GM; lock_timeout = LOCK_TIMEOUT_GM;
DSDEF(ppi)->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
m1(ppi); // port0 and por1 share one pp_global
break; break;
case WRC_MODE_MASTER: case WRC_MODE_MASTER:
ppi->role = PPSI_ROLE_MASTER; for (port=0; port<wr_num_ports;port++) {
if (port==0) { ppi[port]->role = PPSI_ROLE_MASTER;
*class_ptr = PP_CLASS_WR_GM_LOCKED; wrp[port]->wrConfig = WR_M_ONLY;
wrp->wrConfig = WR_M_ONLY; DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_DEFAULT;
spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1); m1(ppi[port]);
lock_timeout = LOCK_TIMEOUT_FM;
shw_pps_gen_unmask_output(1);
DSDEF(ppi)->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
m1(ppi);
} else {
*class_ptr = PP_CLASS_DEFAULT;
wrp->wrConfig = WR_M_AND_S;
DSDEF(ppi)->clockQuality.clockClass = PP_CLASS_DEFAULT;
} }
*class_ptr = PP_CLASS_DEFAULT;
shw_pps_gen_unmask_output(1);
spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1);
lock_timeout = LOCK_TIMEOUT_FM;
break; break;
case WRC_MODE_CASCADED:
for (port=1; port<wr_num_ports;port++) {
ppi[port]->role = PPSI_ROLE_MASTER;
wrp[port]->wrConfig = WR_M_AND_S;
DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_DEFAULT;
m1(ppi[port]);
}
ppi[0]->role = PPSI_ROLE_SLAVE;
wrp[0]->wrConfig = WR_M_AND_S;
DSDEF(ppi[0])->clockQuality.clockClass = PP_CLASS_DEFAULT;
case WRC_MODE_SLAVE:
wrp->wrConfig = WR_M_AND_S;
ppi->role = PPSI_ROLE_SLAVE;
// *class_ptr = PP_CLASS_SLAVE_ONLY;
*class_ptr = PP_CLASS_DEFAULT; *class_ptr = PP_CLASS_DEFAULT;
shw_pps_gen_unmask_output(1);
spll_init(SPLL_MODE_SLAVE, 0, 1);
break;
case WRC_MODE_SLAVE:
for (port=0; port<wr_num_ports;port++) {
ppi[port]->role = PPSI_ROLE_SLAVE;
wrp[port]->wrConfig = WR_S_ONLY;
DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_DEFAULT;
m1(ppi[port]);
}
*class_ptr = PP_CLASS_SLAVE_ONLY;
spll_init(SPLL_MODE_SLAVE, 0, 1); spll_init(SPLL_MODE_SLAVE, 0, 1);
shw_pps_gen_unmask_output(0);
break; break;
} }
start_tics = timer_get_tics(); start_tics = timer_get_tics();
pp_printf("Locking PLL"); pp_printf("Locking PLL");
wrp->ops->enable_timing_output(ppi, 0); /* later, wr_init chooses */ for (port=0; port<wr_num_ports;port++) {
wrp[port]->ops->enable_timing_output(ppi[port], 0); /* later, wr_init chooses */
}
while (!spll_check_lock(0) && lock_timeout) { while (!spll_check_lock(0) && lock_timeout) {
spll_update(); spll_update();
...@@ -218,12 +238,27 @@ int wrc_ptp_set_mode(int mode, int port) ...@@ -218,12 +238,27 @@ int wrc_ptp_set_mode(int mode, int port)
pp_printf("."); pp_printf(".");
} }
pp_printf("\n"); pp_printf("\n");
shw_pps_gen_enable_output(1);
/* If we can't lock to the atomic/gps, we say it in the class */ /* If we can't lock to the atomic/gps, we say it in the class */
if (error && mode == WRC_MODE_GM) if (error && (mode == WRC_MODE_GM))
*class_ptr = PP_CLASS_WR_GM_UNLOCKED; *class_ptr = PP_CLASS_WR_GM_UNLOCKED;
ptp_mode[port] = mode; switch (mode) {
case WRC_MODE_GM:
case WRC_MODE_ABSCAL: /* absolute calibration, gm-lookalike */
case WRC_MODE_MASTER:
case WRC_MODE_SLAVE:
for (port=0; port<wr_num_ports;port++)
ptp_mode[port] = mode;
break;
case WRC_MODE_CASCADED:
ptp_mode[0] = WRC_MODE_SLAVE;
for (port=1; port<wr_num_ports;port++)
ptp_mode[port] = WRC_MODE_MASTER;
break;
}
return error; return error;
} }
...@@ -288,13 +323,14 @@ int wrc_ptp_stop(int port) ...@@ -288,13 +323,14 @@ int wrc_ptp_stop(int port)
wrp = WR_DSPOR(ppi); wrp = WR_DSPOR(ppi);
pp_printf("Port %d PTP stop\n",port); pp_printf("Port %d PTP stop\n",port);
/* Moving fiber: forget about this parent (FIXME: shouldn't be here) */ /* Moving fiber: forget about this parent (FIXME: shouldn't be here) */
wrp->parentWrConfig = wrp->parentWrModeOn = 0; if(port==0) {
memset(ppi->frgn_master, 0, sizeof(ppi->frgn_master)); wrp->parentWrConfig = wrp->parentWrModeOn = 0;
ppi->frgn_rec_num = 0; /* no known master */ memset(ppi->frgn_master, 0, sizeof(ppi->frgn_master));
ppi->frgn_rec_num = 0; /* no known master */
}
ptp_enabled[port] = 0; ptp_enabled[port] = 0;
wr_servo_reset(ppi); wr_servo_reset(ppi);
pp_close_globals(&ppg_static); // pp_close_globals(&ppg_static); -- this function does nothing
return 0; return 0;
} }
......
arch-wrpc/wrpc-spll.c
View file @ e3a99db4
...@@ -69,6 +69,7 @@ int wrpc_enable_timing_output(struct pp_instance *ppi, int enable) ...@@ -69,6 +69,7 @@ int wrpc_enable_timing_output(struct pp_instance *ppi, int enable)
WR_DSPOR(ppi)->ppsOutputOn = enable; WR_DSPOR(ppi)->ppsOutputOn = enable;
shw_pps_gen_enable_output(enable); shw_pps_gen_enable_output(enable);
shw_pps_gen_time_valid(enable);
return WR_SPLL_OK; return WR_SPLL_OK;
} }
......
arch-wrpc/wrpc.h
View file @ e3a99db4
...@@ -19,6 +19,8 @@ ...@@ -19,6 +19,8 @@
#define WRC_MODE_MASTER 2 #define WRC_MODE_MASTER 2
#define WRC_MODE_SLAVE 3 #define WRC_MODE_SLAVE 3
#define WRC_MODE_ABSCAL 4 #define WRC_MODE_ABSCAL 4
#define WRC_MODE_CASCADED 5
extern int ptp_mode[2]; extern int ptp_mode[2];
int wrc_ptp_init(void); int wrc_ptp_init(void);
......
proto-ext-whiterabbit/hooks.c
View file @ e3a99db4
...@@ -16,10 +16,10 @@ static int wr_init(struct pp_instance *ppi, unsigned char *pkt, int plen) ...@@ -16,10 +16,10 @@ static int wr_init(struct pp_instance *ppi, unsigned char *pkt, int plen)
wrp->parentWrModeOn = 0; wrp->parentWrModeOn = 0;
wrp->calibrated = !WR_DEFAULT_PHY_CALIBRATION_REQUIRED; wrp->calibrated = !WR_DEFAULT_PHY_CALIBRATION_REQUIRED;
if ((wrp->wrConfig & WR_M_AND_S) == WR_M_ONLY) // if ((wrp->wrConfig & WR_M_AND_S) == WR_M_ONLY)
wrp->ops->enable_timing_output(ppi, 1); // wrp->ops->enable_timing_output(ppi, 1);
else // else
wrp->ops->enable_timing_output(ppi, 0); // wrp->ops->enable_timing_output(ppi, 0);
return 0; return 0;
} }
...@@ -141,10 +141,10 @@ static int wr_handle_resp(struct pp_instance *ppi) ...@@ -141,10 +141,10 @@ static int wr_handle_resp(struct pp_instance *ppi)
/* /*
* pps always on if offset less than 1 second, * pps always on if offset less than 1 second,
* until ve have a configurable threshold */ * until ve have a configurable threshold */
if (ofm->secs) // if (ofm->secs)
wrp->ops->enable_timing_output(ppi, 0); // wrp->ops->enable_timing_output(ppi, 0);
else // else
wrp->ops->enable_timing_output(ppi, 1); // wrp->ops->enable_timing_output(ppi, 1);
} }
wr_servo_got_delay(ppi); wr_servo_got_delay(ppi);
...@@ -230,10 +230,10 @@ static __attribute__((used)) int wr_handle_presp(struct pp_instance *ppi) ...@@ -230,10 +230,10 @@ static __attribute__((used)) int wr_handle_presp(struct pp_instance *ppi)
/* /*
* pps always on if offset less than 1 second, * pps always on if offset less than 1 second,
* until ve have a configurable threshold */ * until ve have a configurable threshold */
if (ofm->secs) // if (ofm->secs)
wrp->ops->enable_timing_output(ppi, 0); // wrp->ops->enable_timing_output(ppi, 0);
else // else
wrp->ops->enable_timing_output(ppi, 1); // wrp->ops->enable_timing_output(ppi, 1);
return 0; return 0;
} }
......
time-wrpc/wrpc-socket.c
View file @ e3a99db4
...@@ -139,6 +139,9 @@ static int wrpc_net_send(struct pp_instance *ppi, void *pkt, int len, ...@@ -139,6 +139,9 @@ static int wrpc_net_send(struct pp_instance *ppi, void *pkt, int len,
* to transmit it for real, if we want to get back our * to transmit it for real, if we want to get back our
* hardware stamp. Thus, remember if we drop, and use this info. * hardware stamp. Thus, remember if we drop, and use this info.
*/ */
if(link_status[port]!=LINK_UP)
return PP_SEND_DROP;
if (CONFIG_HAS_WRPC_FAULTS) if (CONFIG_HAS_WRPC_FAULTS)
drop = ppsi_drop_tx(); drop = ppsi_drop_tx();
......
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