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PTP noposix stack
Commit 30c366fe authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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softpll: merged WRPC changes (mainly aux clock support)

parent 530698d0
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Showing with 212 additions and 66 deletions
softpll/softpll_ng.c
View file @ 30c366fe
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softpll/softpll_ng.h
View file @ 30c366fe
......@@ -10,6 +10,10 @@
#define SPLL_MODE_SLAVE 3
#define SPLL_MODE_DISABLED 4
#define SPLL_ALL_CHANNELS 0xffff
#define SPLL_AUX_ENABLED (1<<0)
#define SPLL_AUX_LOCKED (1<<1)
void spll_init(int mode, int slave_ref_channel, int align_pps);
void spll_shutdown();
......@@ -22,6 +26,12 @@ int spll_read_ptracker(int channel, int32_t *phase_ps, int *enabled);
void spll_get_num_channels(int *n_ref, int *n_out);
int spll_shifter_busy(int channel);
int spll_get_delock_count();
int spll_update_aux_clocks();
int spll_get_aux_status(int channel);
void spll_set_dac(int index, int value);
int spll_get_dac(int index);
#endif
softpll/spll_common.h
View file @ 30c366fe
......@@ -166,7 +166,7 @@ static void spll_enable_tagger(int channel, int enable)
SPLL->RCER &= ~ (1<<channel);
}
TRACE("%s: ch %d, OCER 0x%x, RCER 0x%x\n", __FUNCTION__, channel, SPLL->OCER, SPLL->RCER);
// TRACE("%s: ch %d, OCER 0x%x, RCER 0x%x\n", __FUNCTION__, channel, SPLL->OCER, SPLL->RCER);
}
static void spll_resync_dmtd_counter(int channel)
......
softpll/spll_defs.h
View file @ 30c366fe
......@@ -15,6 +15,11 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
/* Reference clock period, in picoseconds */
#define CLOCK_PERIOD_PICOSECONDS 16000
/* optional DMTD clock division to improve FPGA timing closure by avoiding
clock nets directly driving FD inputs. Must be consistent with the
g_divide_inputs_by_2 generic. */
#define DIVIDE_DMTD_CLOCKS_BY_2 0
/* Number of bits in phase tags generated by the DMTDs. Used to sign-extend the tags.
Corresponding VHDL generic: g_tag_bits. */
#define TAG_BITS 22
......
softpll/spll_main.h
View file @ 30c366fe
......@@ -6,7 +6,6 @@
#define MATCH_WAIT_OUT 2
#undef WITH_SEQUENCING
//#define WITH_SEQUENCING
/* State of the Main PLL */
struct spll_main_state {
......@@ -16,8 +15,7 @@ struct spll_main_state {
spll_lock_det_t ld;
int adder_ref, adder_out, tag_ref, tag_out, tag_ref_d, tag_out_d;
int err_d0, err_d1;
// tag sequencing stuff
uint32_t seq_ref, seq_out;
int match_state;
......@@ -28,6 +26,7 @@ struct spll_main_state {
int id_ref, id_out; /* IDs of the reference and the output channel */
int sample_n;
int delock_count;
int dac_index;
};
......@@ -48,7 +47,8 @@ static void mpll_init(struct spll_main_state *s, int id_ref, int id_out)
s->ld.delock_samples = 100;
s->id_ref = id_ref;
s->id_out = id_out;
s->dac_index = id_out - n_chan_ref;
pi_init(&s->pi);
ld_init(&s->ld);
}
......@@ -63,7 +63,7 @@ static void mpll_start(struct spll_main_state *s)
s->seq_ref = 0;
s->seq_out = 0;
s->match_state = MATCH_NEXT_TAG;
s->err_d0 = s->err_d1 = 0;
s->phase_shift_target = 0;
s->phase_shift_current = 0;
s->sample_n= 0;
......@@ -155,15 +155,6 @@ static int mpll_update(struct spll_main_state *s, int tag, int source)
#ifndef WITH_SEQUENCING
/* if(s->err_d0 - s->err_d1 > -(1<<HPLL_N)/2 && err - s->err_d0 < -(1<<HPLL_N)/2 )
err += (1<<HPLL_N);
if(s->err_d0 - s->err_d1 < (1<<HPLL_N)/2 && err - s->err_d0 > (1<<HPLL_N)/2 )
err -= (1<<HPLL_N);
s->err_d1 = s->err_d0;
s->err_d0 = err;*/
/* Hack: the PLL is locked, so the tags are close to each other. But when we start phase shifting, after reaching
full clock period, one of the reference tags will flip before the other, causing a suddent 2**HPLL_N jump in the error.
So, once the PLL is locked, we just mask out everything above 2**HPLL_N.
......@@ -179,19 +170,19 @@ static int mpll_update(struct spll_main_state *s, int tag, int source)
#endif
y = pi_update(&s->pi, err);
SPLL->DAC_MAIN = SPLL_DAC_MAIN_VALUE_W(y) | SPLL_DAC_MAIN_DAC_SEL_W(s->id_out);
y = pi_update(&s->pi, err);
SPLL->DAC_MAIN = SPLL_DAC_MAIN_VALUE_W(y) | SPLL_DAC_MAIN_DAC_SEL_W(s->dac_index);
spll_debug(DBG_MAIN | DBG_REF, s->tag_ref + s->adder_ref, 0);
spll_debug(DBG_MAIN | DBG_TAG, s->tag_out + s->adder_out, 0);
spll_debug(DBG_MAIN | DBG_ERR, err, 0);
spll_debug(DBG_MAIN | DBG_SAMPLE_ID, s->sample_n++, 1);
// spll_debug(DBG_MAIN | DBG_Y, y, 1);
spll_debug(DBG_MAIN | DBG_SAMPLE_ID, s->sample_n++, 0);
spll_debug(DBG_MAIN | DBG_Y, y, 1);
s->tag_out = -1;
s->tag_ref = -1;
if(s->adder_ref > 2*MPLL_TAG_WRAPAROUND && s->adder_out > 2*MPLL_TAG_WRAPAROUND)
if(s->adder_ref > 2*MPLL_TAG_WRAPAROUND && s->adder_out > 2*MPLL_TAG_WRAPAROUND)
{
s->adder_ref -= MPLL_TAG_WRAPAROUND;
s->adder_out -= MPLL_TAG_WRAPAROUND;
......
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