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Production Test Suite - base
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5978688f
Commit
5978688f
authored
May 03, 2012
by
Matthieu Cattin
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Add function to access all the register fields in ltc217x module.
Exception based error handeling.
parent
bff52e5c
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1 changed file
with
49 additions
and
5 deletions
+49
-5
ltc217x.py
common/ltc217x.py
+49
-5
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common/ltc217x.py
View file @
5978688f
...
...
@@ -39,6 +39,7 @@ class CLTC217x:
FMT_CH1_NAP
=
(
1
<<
0
)
OUTMODE_ILVDS_MASK
=
0xE0
OUTMODE_ILVDS_SHIFT
=
5
OUTMODE_TERMON
=
(
1
<<
4
)
OUTMODE_OUTOFF
=
(
1
<<
3
)
OUTMODE_MASK
=
0x07
...
...
@@ -69,7 +70,7 @@ class CLTC217x:
self
.
slave
=
slave
self
.
wr_reg
(
self
.
R_RST
,
self
.
RST
)
self
.
wr_reg
(
self
.
R_FMT
,
self
.
FMT_TWOSCOMP
)
self
.
wr_reg
(
self
.
R_OUTMODE
,
(
self
.
OUTMODE_ILVDS_4M5
|
self
.
OUTMODE_2L_16B
))
self
.
wr_reg
(
self
.
R_OUTMODE
,
(
(
self
.
ILVDS
[
'4.5mA'
]
<<
self
.
OUTMODE_ILVDS_SHIFT
)
|
(
self
.
OUTMODE
[
'2lanes16bit'
])
))
#self.wr_reg(self.R_FMT, 0)
#self.wr_reg(self.R_OUTMODE, (self.OUTMODE_ILVDS_4M5 | self.OUTMODE_2L_16B | self.OUTMODE_TERMON))
#self.wr_reg(self.R_OUTMODE, (self.OUTMODE_ILVDS_2M5 | self.OUTMODE_2L_16B | self.OUTMODE_TERMON))
...
...
@@ -104,13 +105,13 @@ class CLTC217x:
reg
=
self
.
rd_reg
(
self
.
R_FMT
)
if
(
en
):
# enable tow's complement data output format
reg
|=
self
.
FMT_T
OW
SCOMP
reg
|=
self
.
FMT_T
WO
SCOMP
else
:
# binary offset data output format
reg
&=
~
(
self
.
FMT_T
OW
SCOMP
)
reg
&=
~
(
self
.
FMT_T
WO
SCOMP
)
self
.
wr_reg
(
self
.
R_FMT
,
reg
)
def
random
(
self
,
en
):
def
random
_out
(
self
,
en
):
reg
=
self
.
rd_reg
(
self
.
R_FMT
)
if
(
en
):
# Enable random data output
...
...
@@ -136,7 +137,50 @@ class CLTC217x:
return
self
.
rd_reg
(
self
.
R_OUTMODE
)
def
set_i_lvds
(
self
,
current
):
if
current
in
self
.
ILVDS
:
#print "[LTC217x] LVDS settting: %s -> 0x%02X" %(current, self.ILVDS[current])
reg
=
self
.
rd_reg
(
self
.
R_OUTMODE
)
# Read register
#print "[LTC217x] Output mode reg: 0x%02X" %(reg)
reg
&=
~
(
self
.
OUTMODE_ILVDS_MASK
)
# Reset ILVDS bits
#print "[LTC217x] Output mode reg: 0x%02X" %(reg)
reg
|=
(
self
.
OUTMODE_ILVDS_MASK
&
(
self
.
ILVDS
[
current
]
<<
self
.
OUTMODE_ILVDS_SHIFT
))
#print "[LTC217x] Output mode reg: 0x%02X" %(reg)
self
.
wr_reg
(
self
.
R_OUTMODE
,
reg
)
# Write new value to register
else
:
raise
spi
.
SPIDeviceOperationError
(
"Requiered LVDS current setting doesn't exist for LPC217x!"
)
def
set_outmode
(
self
,
mode
):
if
mode
in
self
.
OUTMODE
:
#print "[LTC217x] Output mode settting: %s" %(mode)
reg
=
self
.
rd_reg
(
self
.
R_OUTMODE
)
# Read register
#print "[LTC217x] Ouput mode reg: 0x%02X" %(reg)
reg
&=
~
(
self
.
OUTMODE_MASK
)
# Reset ILVDS bits
#print "[LTC217x] Ouput mode reg: 0x%02X" %(reg)
reg
|=
self
.
OUTMODE_MASK
&
(
self
.
OUTMODE
[
mode
])
#print "[LTC217x] Output mode reg: 0x%02X" %(reg)
self
.
wr_reg
(
self
.
R_OUTMODE
,
reg
)
# Write new value to register
else
:
raise
spi
.
SPIDeviceOperationError
(
"Requiered output mode setting doesn't exist for LPC217x!"
)
def
set_lvds_termination
(
self
,
en
):
reg
=
self
.
rd_reg
(
self
.
R_OUTMODE
)
if
(
en
):
# Enable LVDS serial terminations
reg
|=
self
.
OUTMODE_TERMON
else
:
# Disable LVDS serial terminations
reg
&=
~
(
self
.
OUTMODE_TERMON
)
self
.
wr_reg
(
self
.
R_OUTMODE
,
reg
)
def
output_dis
(
self
,
dis
):
reg
=
self
.
rd_reg
(
self
.
R_OUTMODE
)
if
(
dis
):
# Disable LVDS outputs
reg
|=
self
.
OUTMODE_OUTOFF
else
:
# Enable LVDS outputs
reg
&=
~
(
self
.
OUTMODE_OUTOFF
)
self
.
wr_reg
(
self
.
R_OUTMODE
,
reg
)
def
get_testpat
(
self
):
return
(((
self
.
rd_reg
(
self
.
R_TESTPAT_MSB
)
&
self
.
TESTPAT_MSB_MASK
)
<<
8
)
...
...
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