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019be8e1
Commit
019be8e1
authored
Mar 28, 2014
by
Matthieu Cattin
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test40: Improve internal trigger test (add multiple acq -> sort of persistancy).
parent
47a507ab
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1 changed file
with
80 additions
and
21 deletions
+80
-21
test40.py
test/fmcadc100m14b4cha/python/test40.py
+80
-21
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test/fmcadc100m14b4cha/python/test40.py
View file @
019be8e1
...
...
@@ -26,6 +26,7 @@ from fmc_adc_spec import *
from
fmc_adc
import
*
from
numpy
import
*
from
pylab
import
*
import
matplotlib.colors
as
colors
from
calibr_box
import
*
import
find_usb_tty
from
PAGE.Agilent33250A
import
*
...
...
@@ -46,7 +47,7 @@ BOX_SET_SLEEP = 0.01
ACQ_TIMEOUT
=
10
# Acquisition parameters
NB_ACQ
=
1
NB_ACQ
=
20
ACQ_PAUSE
=
0.1
# pause between acq. stop and start, start and trigger
IN_RANGE
=
'100mV'
IN_TERM
=
'OFF'
...
...
@@ -58,7 +59,10 @@ POST_TRIG_SAMPLES = 5000
NB_SHOTS
=
1
BYTES_PER_SAMPLE
=
2
TRIG_THRES_VOLT
=
0.0
TRIG_THRES_VOLT
=
0.007
TRIG_THRES_FILT
=
20
INT_TRIG_TEST_MODE
=
True
TRIG_DEL
=
0
# in samples
TRIG_TIMETAG_BYTES
=
16
...
...
@@ -154,20 +158,47 @@ def acq_channels(fmc, carrier, adc_fs, pause):
channels_data
=
[
digital2volt
(
item
,
adc_fs
,
16
)
for
item
in
channels_data
]
return
channels_data
,
trig_timetag
def
plot_channel
(
ch_data
,
trig_thres
,
trig_pos
,
ylimit
):
def
plot_channel
(
ch_data
,
trig_thres
,
trig_pos
,
ylimit
,
col
):
#cmap = cm.get_cmap('YlOrRd')
cmap
=
cm
.
get_cmap
(
'autumn'
)
cnorm
=
colors
.
Normalize
(
vmin
=
0
,
vmax
=
NB_ACQ
)
mapcol
=
cm
.
ScalarMappable
(
norm
=
cnorm
,
cmap
=
cmap
)
sample
=
arange
(
len
(
ch_data
))
plot
(
sample
,
ch_data
,
'g-'
)
plot
(
sample
,
ch_data
,
linestyle
=
'-'
,
color
=
mapcol
.
to_rgba
(
col
)
)
plot
(
sample
,
[
trig_thres
]
*
len
(
sample
),
'r--'
)
ylim_min
=
-
ylimit
-
(
ylimit
/
10.0
)
ylim_max
=
ylimit
+
(
ylimit
/
10.0
)
ylim
(
ylim_min
,
ylim_max
)
grid
(
color
=
'k'
,
linestyle
=
':'
,
linewidth
=
1
)
vlines
(
trig_pos
,
ylim_min
,
ylim_max
,
color
=
'#AA0000'
,
linestyles
=
'solid'
)
xlabel
(
'Samples'
)
ylabel
(
'Voltage [V]'
)
title
(
'Internal hardware trigger, threshold filter:
%
d'
%
TRIG_THRES_FILT
)
#legend(loc='upper left')
#draw()
#show()
return
0
def
plot_all_channels
(
ch_data
,
trig_thres
,
trig_pos
,
ylimit
):
sample
=
arange
(
len
(
ch_data
)
/
4
)
plot
(
sample
,
ch_data
[
0
::
4
],
'g-'
,
label
=
'Channel
%
s'
%
CHANNEL
)
plot
(
sample
,
ch_data
[
1
::
4
],
'm-'
,
label
=
'Over threshold'
)
plot
(
sample
,
ch_data
[
2
::
4
],
'b-'
,
label
=
'Over thershold filtered'
)
plot
(
sample
,
ch_data
[
3
::
4
],
'c-'
,
label
=
'Trigger (internal)'
)
plot
(
sample
,
[
trig_thres
]
*
len
(
sample
),
'r--'
,
label
=
'Threshold'
)
ylim_min
=
-
ylimit
-
(
ylimit
/
10.0
)
ylim_max
=
ylimit
+
(
ylimit
/
10.0
)
ylim
(
ylim_min
,
ylim_max
)
grid
(
color
=
'k'
,
linestyle
=
':'
,
linewidth
=
1
)
vlines
(
trig_pos
,
ylim_min
,
ylim_max
,
color
=
'#AA0000'
,
linestyles
=
'solid'
,
label
=
'Trigger (valid)'
)
legend
(
loc
=
'upper left'
)
xlabel
(
'Samples'
)
ylabel
(
'Voltage [V]'
)
title
(
'Internal hardware trigger, threshold filter:
%
d'
%
TRIG_THRES_FILT
)
#draw()
show
()
return
0
def
main
(
default_directory
=
'.'
):
...
...
@@ -219,6 +250,10 @@ def main (default_directory='.'):
try
:
if
CHANNEL
!=
1
and
INT_TRIG_TEST_MODE
==
True
:
print
(
"[ERROR] When internale trigger test mode is enabled, channel 1 must be selected!"
)
sys
.
exit
()
# Others objects declaration
usb_tty
=
find_usb_tty
.
CttyUSB
()
awg_tty
=
usb_tty
.
find_usb_tty
(
AWG_USB_VENDOR_ID
,
AWG_USB_PRODUCT_ID
)
...
...
@@ -245,12 +280,13 @@ def main (default_directory='.'):
fmc
.
set_utc_coarse_cnt
(
utc_coarse
)
#print "UTC core coarse counter initialised to : %d" % fmc.get_utc_coarse_cnt()
# Print configuration
#fmc.print_adc_core_config()
# Print ADC config
#fmc.print_adc_config()
# Internal trigger test mode
if
INT_TRIG_TEST_MODE
==
True
:
fmc
.
int_trig_tst_en
()
##################################################
# Configure trigger
##################################################
...
...
@@ -260,18 +296,20 @@ def main (default_directory='.'):
trig_sw_en
=
0
trig_channel
=
CHANNEL
trig_thres
=
volt2digital_without_offset
(
TRIG_THRES_VOLT
,
ADC_FS
[
IN_RANGE
],
16
)
fmc
.
set_trig_config
(
trig_hw_sel
,
trig_hw_pol
,
trig_hw_en
,
trig_sw_en
,
trig_channel
,
trig_thres
,
TRIG_DEL
)
fmc
.
set_trig_config
(
trig_hw_sel
,
trig_hw_pol
,
trig_hw_en
,
trig_sw_en
,
trig_channel
,
trig_thres
,
TRIG_DEL
,
TRIG_THRES_FILT
)
print
(
"=================================================="
)
print
(
"Channel:
%
d
\n
Input range:
%
s
\n
Input term:
%
s
\n
Trigger threshold:
%1.1
fV
\n
Trigger
delay:
%
d"
%
(
CHANNEL
,
IN_RANGE
,
IN_TERM
,
TRIG_THRES_VO
LT
,
TRIG_DEL
))
print
(
"Channel:
%
d
\n
Input range:
%
s
\n
Input term:
%
s
\n
Trigger threshold:
%1.1
fV
\n
Trigger
threshold filter:
%
d
\n
Trigger delay:
%
d"
%
(
CHANNEL
,
IN_RANGE
,
IN_TERM
,
TRIG_THRES_VOLT
,
TRIG_THRES_FI
LT
,
TRIG_DEL
))
print
(
"=================================================="
)
# Print configuration
fmc
.
print_adc_core_config
()
##################################################
# Set awg sine params
##################################################
sine
.
frequency
=
1
E6
sine
.
amplitude
=
0.
8
*
ADC_FS
[
IN_RANGE
]
sine
.
frequency
=
1
0E3
sine
.
amplitude
=
0.
4
*
ADC_FS
[
IN_RANGE
]
sine
.
dc
=
0
print
"
\n
Sine frequency:
%3.3
fMHz amplitude:
%2.3
fVp offset:
%2.3
fV"
%
(
sine
.
frequency
/
1E6
,
sine
.
amplitude
,
sine
.
dc
)
...
...
@@ -390,8 +428,8 @@ def main (default_directory='.'):
#print "\nApply DAC correction\n"
fmc
.
set_dac_corr
(
dac_corr_data
)
g
=
adc_corr_data
[
IN_RANGE
][
'gain'
][
0
]
o
=
adc_corr_data
[
IN_RANGE
][
'offset'
][
0
]
g
=
adc_corr_data
[
IN_RANGE
][
'gain'
][
CHANNEL
-
1
]
o
=
adc_corr_data
[
IN_RANGE
][
'offset'
][
CHANNEL
-
1
]
#print "\nApply ADC offset correction: gain=0x%04X, offset=0x%04X" %(g, o)
fmc
.
set_adc_gain_offset_corr
(
CHANNEL
,
g
,
o
)
...
...
@@ -403,20 +441,41 @@ def main (default_directory='.'):
##################################################
print
"
\n
Acquiring channel
%
d"
%
CHANNEL
# Perform an acquisition
for
acq_nb
in
range
(
NB_ACQ
):
print
(
"Acqisition:
%
d"
%
acq_nb
)
if
INT_TRIG_TEST_MODE
==
True
:
acq_nb
=
1
else
:
acq_nb
=
NB_ACQ
for
nb
in
range
(
acq_nb
):
acq_data
,
trig_timetag
=
acq_channels
(
fmc
,
carrier
,
ADC_FS
[
IN_RANGE
],
ACQ_PAUSE
)
channel_data
=
acq_data
[
CHANNEL
-
1
::
4
]
#print("Number of samples: %d"%(len(channel_data)))
cal_ch_data
=
channel_data
ch_data
=
acq_data
[
CHANNEL
-
1
::
4
]
#print("Number of samples: %d"%(len(ch_data)))
##################################################
# Plot channel
##################################################
ch_data
=
cal_ch_data
trig_pos
=
PRE_TRIG_SAMPLES
plot_channel
(
ch_data
,
TRIG_THRES_VOLT
,
trig_pos
,
(
ADC_FS
[
IN_RANGE
]
/
2
))
show
()
if
INT_TRIG_TEST_MODE
==
False
:
#col = float(nb)/float(acq_nb-1)
col
=
nb
print
(
"Acqisition:
%3
d, color:
%1.4
f"
%
(
nb
,
col
))
plot_channel
(
ch_data
,
TRIG_THRES_VOLT
,
trig_pos
,
(
ADC_FS
[
IN_RANGE
]
/
2
),
col
)
if
INT_TRIG_TEST_MODE
==
False
:
show
()
else
:
# shift over_thres signal to align them with data
for
i
in
range
(
3
):
over_thres
=
acq_data
[
1
::
4
]
over_thres
.
pop
(
-
1
)
over_thres
.
insert
(
0
,
0
)
acq_data
[
1
::
4
]
=
over_thres
for
i
in
range
(
2
):
over_thres_filt
=
acq_data
[
2
::
4
]
over_thres_filt
.
pop
(
-
1
)
over_thres_filt
.
insert
(
0
,
0
)
acq_data
[
2
::
4
]
=
over_thres_filt
plot_all_channels
(
acq_data
,
TRIG_THRES_VOLT
,
trig_pos
,
(
ADC_FS
[
IN_RANGE
]
/
2
))
# Make sure all switches are OFF
open_all_channels
(
fmc
)
...
...
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