test/spec: first commit of the already working tests

NOTE: it is needed to change paths and some minor work on the python files. Signed-off-by: Samuel Iglesias Gonsalvez <samuel.iglesias.gonsalvez@cern.ch>

test/spec: first commit of the already working tests
NOTE: it is needed to change paths and some minor work on the python files. Signed-off-by: Samuel Iglesias Gonsalvez <samuel.iglesias.gonsalvez@cern.ch>
0470946c · Samuel Iglesias Gonsalvez · 33591dd6 · 0470946c · 0470946c · 0470946c
Commit 0470946c authored May 27, 2011 by Samuel Iglesias Gonsalvez
18 changed files
--- a/test/spec/firmwares/fpga_loader
+++ b/test/spec/firmwares/fpga_loader
--- a/test/spec/firmwares/test00.bin
+++ b/test/spec/firmwares/test00.bin
--- a/test/spec/firmwares/test_clk.bin
+++ b/test/spec/firmwares/test_clk.bin
--- a/test/spec/hdl/test00/README
+++ b/test/spec/hdl/test00/README
+-------------------------------------------------------------------------------
+--------------------------------    TEST 1    ---------------------------------
+-------------------------------------------------------------------------------
+
+1.- WHAT IS INCLUDED
+
+  A.- A top VHDL in which 3 wishbone slaves can be addressed. Only the first
+      two are used. This two wishbone slaves correspond to the I2C master that
+      connect to i2c devices in fmc-carrier-tester: I2C_A, I2C_B.
+      Its wishbone mappings are
+        - I2C_A: 0x40000
+        - I2C_B: 0x80000
+  B.- "test00.bin" which is the bitstream for programming spec FPGA with the
+      aforementioned configuration.
+  C.- "test00.py" that it's a python test which is an aggregate of the rest
+      of python code.
+
+This test checks the voltage values of the power supply pins on the FMC.
--- a/test/spec/hdl/test00/spec_ddr_test_top.vhd
+++ b/test/spec/hdl/test00/spec_ddr_test_top.vhd
--- a/test/spec/hdl/test00/spec_top.ucf
+++ b/test/spec/hdl/test00/spec_top.ucf
--- a/test/spec/python/csr.py
+++ b/test/spec/python/csr.py
+#!/usr/bin/python
+
+import sys
+import rr
+import time
+
+
+class CCSR:
+
+	def __init__(self, bus, base_addr):
+		self.base_addr = base_addr;
+		self.bus = bus;
+
+	def wr_reg(self, addr, val):
+		#print("                wr:%.8X reg:%.8X")%(val,(self.base_addr+addr))
+		self.bus.iwrite(0, self.base_addr +  addr, 4, val)
+
+	def rd_reg(self, addr):
+		reg = self.bus.iread(0, self.base_addr + addr, 4)
+		#print("                reg:%.8X value:%.8X")%((self.base_addr+addr), reg)
+		return reg
+
+	def wr_bit(self, addr, bit, value):
+		reg = self.rd_reg(addr)
+		if(0==value):
+			reg &= ~(1<<bit)
+		else:
+			reg |= (1<<bit)
+		self.wr_reg(addr, reg)
+
+
+	def rd_bit(self, addr, bit):
+		if(self.rd_reg(addr) & (1<<bit)):
+			return 1
+		else:
+			return 0
--- a/test/spec/python/eeprom_test_A.dat
+++ b/test/spec/python/eeprom_test_A.dat
+AAAA AAAAAAAA
+AAAA AAAAAAAA
+AAAA AAAAAAAA
+AAAA AAAAAAAA
+AAAA AAAAAAAA
+AAAA AAAAAAAA
--- a/test/spec/python/gn4124.py
+++ b/test/spec/python/gn4124.py
+#!/usr/bin/python
+
+import sys
+import rr
+import time
+import csr
+
+class CGN4124:
+
+    # Host registers (BAR12), for DMA items storage
+    HOST_BAR = 0xC
+    HOST_DMA_CARRIER_START_ADDR = 0x00
+    HOST_DMA_HOST_START_ADDR_L = 0x04
+    HOST_DMA_HOST_START_ADDR_H = 0x08
+    HOST_DMA_LENGTH = 0x0C
+    HOST_DMA_NEXT_ITEM_ADDR_L = 0x10
+    HOST_DMA_NEXT_ITEM_ADDR_H = 0x14
+    HOST_DMA_ATTRIB = 0x18
+
+    # GN4124 chip registers (BAR4)
+    GN4124_BAR = 0x4
+    R_CLK_CSR = 0x808
+    R_INT_CFG0 = 0x820
+    R_GPIO_DIR_MODE = 0xA04
+    R_GPIO_INT_MASK_CLR = 0xA18
+    R_GPIO_INT_MASK_SET = 0xA1C
+    R_GPIO_INT_STATUS = 0xA20
+    R_GPIO_INT_VALUE = 0xA28
+
+    CLK_CSR_DIVOT_MASK = 0x3F0
+    INT_CFG0_GPIO = 15
+    GPIO_INT_SRC = 8
+
+    # GN4124 core registers (BAR0)
+    R_DMA_CTL = 0x00
+    R_DMA_STA = 0x04
+    R_DMA_CARRIER_START_ADDR = 0x08
+    R_DMA_HOST_START_ADDR_L = 0x0C
+    R_DMA_HOST_START_ADDR_H = 0x10
+    R_DMA_LENGTH = 0x14
+    R_DMA_NEXT_ITEM_ADDR_L = 0x18
+    R_DMA_NEXT_ITEM_ADDR_H = 0x1C
+    R_DMA_ATTRIB = 0x20
+
+    DMA_CTL_START = 0
+    DMA_CTL_ABORT = 1
+    DMA_CTL_SWAP = 2
+    DMA_STA = ['Idle','Done','Busy','Error','Aborted']
+    DMA_ATTRIB_LAST = 0
+    DMA_ATTRIB_DIR = 1
+
+    def rd_reg(self, bar, addr):
+        return self.bus.iread(bar, addr, 4)
+
+    def wr_reg(self, bar, addr, value):
+        self.bus.iwrite(bar, addr, 4, value)
+
+    def __init__(self, bus, csr_addr):
+        self.bus = bus
+        self.dma_csr = csr.CCSR(bus, csr_addr)
+        self.dma_item_cnt = 0
+        # Get page list
+        self.pages = self.bus.getplist()
+        # Shift by 12 to get the 32-bit physical addresses
+        self.pages = [addr << 12 for addr in self.pages]
+        self.set_interrupt_config()
+        # Enable interrupt from gn4124
+        self.bus.irqena()
+
+    # Set local bus frequency
+    def set_local_bus_freq(self, freq):
+        # freq in MHz
+        # LCLK = (25MHz*(DIVFB+1))/(DIVOT+1)
+        # DIVFB = 31
+        # DIVOT = (800/LCLK)-1
+        divot = int(round((800/freq)-1,0))
+        #print '%d' % divot
+        data = 0xe001f00c + (divot << 4)
+        #print '%.8X' % data
+        #print 'Set local bus freq to %dMHz' % int(round(800/(divot+1),0))
+        self.wr_reg(self.GN4124_BAR, self.R_CLK_CSR, data)
+
+    # Get local bus frequency
+    #   return: frequency in MHz
+    def get_local_bus_freq(self):
+        reg = self.rd_reg(self.GN4124_BAR, self.R_CLK_CSR)
+        divot = ((reg & self.CLK_CSR_DIVOT_MASK)>>4)
+        return (800/(divot + 1))
+
+    # Get physical addresses of the pages allocated to GN4124
+    def get_physical_addr(self):
+        return self.pages
+
+    # Wait for interrupt
+    def wait_irq(self):
+        # Add here reading of the interrupt source (once the irq core will be present)
+        return self.bus.irqwait()
+
+    # GN4124 interrupt configuration
+    def set_interrupt_config(self):
+        # Set interrupt line from FPGA (GPIO8) as input
+        self.wr_reg(self.GN4124_BAR, self.R_GPIO_DIR_MODE, (1<<self.GPIO_INT_SRC))
+        # Set interrupt mask for all GPIO except for GPIO8
+        self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_MASK_SET, ~(1<<self.GPIO_INT_SRC))
+        # Make sure the interrupt mask is cleared for GPIO8
+        self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_MASK_CLR, (1<<self.GPIO_INT_SRC))
+        # Interrupt on rising edge of GPIO8
+        self.wr_reg(self.GN4124_BAR, self.R_GPIO_INT_VALUE, (1<<self.GPIO_INT_SRC))
+        # GPIO as interrupt 0 source
+        self.wr_reg(self.GN4124_BAR, self.R_INT_CFG0, (1<<self.INT_CFG0_GPIO))
+
+    # Get DMA controller status
+    def get_dma_status(self):
+        reg = self.dma_csr.rd_reg(self.R_DMA_STA)
+        if(reg > len(self.DMA_STA)):
+            print("DMA status register : %.8X") % reg
+            raise Exception('Invalid DMA status')
+        else:
+            return self.DMA_STA[reg]
+
+    # Configure DMA byte swapping
+    #   0 = A1 B2 C3 D4 (straight)
+    #   1 = B2 A1 D4 C3 (swap bytes in words)
+    #   2 = C3 D4 A1 B2 (swap words)
+    #   3 = D4 C3 B2 A1 (invert bytes)
+    def set_dma_swap(self, swap):
+        if(swap > 3):
+            raise Exception('Invalid swapping configuration : %d') % swap
+        else:
+            self.dma_csr.wr_reg(self.R_CTL, (swap << self.DMA_CTL_SWAP))
+
+    # Add DMA item (first item is on the board, the following in the host memory)
+    #   carrier_addr, host_addr, length and next_item_addr are in bytes
+    #   dma_dir  = 1 -> PCIe to carrier
+    #   dma_dir  = 0 -> carrier to PCIe
+    #   dma_last = 0 -> last item in the transfer
+    #   dma_last = 1 -> more item in the transfer
+    #   Only supports 32-bit host address
+    def add_dma_item(self, carrier_addr, host_addr, length, dma_dir, last_item):
+        if(0 == self.dma_item_cnt):
+            # write the first DMA item in the carrier
+            self.dma_csr.wr_reg(self.R_DMA_CARRIER_START_ADDR, carrier_addr)
+            self.dma_csr.wr_reg(self.R_DMA_HOST_START_ADDR_L, (host_addr & 0xFFFFFFFF))
+            self.dma_csr.wr_reg(self.R_DMA_HOST_START_ADDR_H, (host_addr >> 32))
+            self.dma_csr.wr_reg(self.R_DMA_LENGTH, length)
+            self.dma_csr.wr_reg(self.R_DMA_NEXT_ITEM_ADDR_L, (self.pages[0] & 0xFFFFFFFF))
+            self.dma_csr.wr_reg(self.R_DMA_NEXT_ITEM_ADDR_H, 0x0)
+            attrib = (dma_dir << self.DMA_ATTRIB_DIR) + (last_item << self.DMA_ATTRIB_LAST)
+            self.dma_csr.wr_reg(self.R_DMA_ATTRIB, attrib)
+        else:
+            # write nexy DMA item(s) in host memory
+            # uses page 0 to store DMA items
+            # current and next item addresses are automatically set
+            current_item_addr = (self.dma_item_cnt-1)*0x20
+            next_item_addr = (self.dma_item_cnt)*0x20
+            self.wr_reg(self.HOST_BAR, self.HOST_DMA_CARRIER_START_ADDR + current_item_addr, carrier_addr)
+            self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_L + current_item_addr, host_addr)
+            self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_H + current_item_addr, 0x0)
+            self.wr_reg(self.HOST_BAR, self.HOST_DMA_LENGTH + current_item_addr, length)
+            self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_L + current_item_addr,
+                                self.pages[0] + next_item_addr)
+            self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_H + current_item_addr, 0x0)
+            attrib = (dma_dir << self.DMA_ATTRIB_DIR) + (last_item << self.DMA_ATTRIB_LAST)
+            self.wr_reg(self.HOST_BAR, self.HOST_DMA_ATTRIB + current_item_addr, attrib)
+        self.dma_item_cnt += 1
+
+    # Start DMA transfer
+    def start_dma(self):
+        self.dma_item_cnt = 0
+        self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 1)
+        # The following two lines should be removed
+        # when the GN4124 vhdl core will implement auto clear of start bit
+        #while(('Idle' == self.get_dma_status()) or
+        #      ('Busy' == self.get_dma_status())):
+        #    pass
+        self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 0)
+
+    # Abort DMA transfer
+    def abort_dma(self):
+        self.dma_item_cnt = 0
+        self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_ABORT, 1)
+        # The following two lines should be removed
+        # when the GN4124 vhdl core will implement auto clear of start bit
+        while('Aborted' != self.get_dma_status()):
+            pass
+        self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_ABORT, 0)
+
+    # Get memory page
+    def get_memory_page(self, page_nb):
+        data = []
+        for i in range(2**10):
+            data.append(self.rd_reg(self.HOST_BAR, (page_nb<<12)+(i<<2)))
+        return data
+
+    # Set memory page
+    def set_memory_page(self, page_nb, pattern):
+        for i in range(2**10):
+            self.wr_reg(self.HOST_BAR, (page_nb<<12)+(i<<2), pattern)
--- a/test/spec/python/i2c.py
+++ b/test/spec/python/i2c.py
+#!/usr/bin/python
+
+import sys
+import rr
+import time
+
+
+class COpenCoresI2C:
+
+    # OpenCores I2C registers description
+    R_PREL = 0x0
+    R_PREH = 0x4
+    R_CTR = 0x8
+    R_TXR = 0xC
+    R_RXR = 0xC
+    R_CR = 0x10
+    R_SR = 0x10
+
+    CTR_EN = (1<<7)
+
+    CR_STA = (1<<7)
+    CR_STO = (1<<6)
+    CR_RD = (1<<5)
+    CR_WR = (1<<4)
+    CR_ACK = (1<<3)
+
+    SR_RXACK = (1<<7)
+    SR_TIP = (1<<1)
+
+
+    def wr_reg(self, addr, val):
+        self.bus.iwrite(0, self.base_addr +  addr, 4, val)
+
+    def rd_reg(self,addr):
+        return self.bus.iread(0, self.base_addr + addr, 4)
+
+    # Function called during object creation
+    #   bus = host bus (PCIe, VME, etc...)
+    #   base_addr = I2C core base address
+    #   prescaler = SCK prescaler, prescaler = (Fsys/(5*Fsck))-1
+    def __init__(self, bus, base_addr, prescaler):
+        self.bus = bus
+        self.base_addr = base_addr
+        self.wr_reg(self.R_CTR, 0)
+        #print("prescaler: %.4X") % prescaler
+        self.wr_reg(self.R_PREL, (prescaler & 0xff))
+        #print("PREL: %.2X") % self.rd_reg(self.R_PREL)
+        self.wr_reg(self.R_PREH, (prescaler >> 8))
+        #print("PREH: %.2X") % self.rd_reg(self.R_PREH)
+        self.wr_reg(self.R_CTR, self.CTR_EN)
+        #print("CTR: %.2X") % self.rd_reg(self.R_CTR)
+        if(not(self.rd_reg(self.R_CTR) & self.CTR_EN)):
+            print "Warning! I2C core is not enabled!"
+
+    def wait_busy(self):
+        while(self.rd_reg(self.R_SR) & self.SR_TIP):
+            pass
+
+    def start(self, addr, write_mode):
+        addr = addr << 1
+        if(write_mode == False):
+            addr = addr | 1
+        self.wr_reg(self.R_TXR, addr)
+        #print("R_TXR: %.2X") % self.rd_reg(self.R_TXR)
+       	self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR)
+       	self.wait_busy()
+
+       	if(self.rd_reg(self.R_SR) & self.SR_RXACK):
+            raise Exception('No ACK upon address (device 0x%x not connected?)' % addr)
+            return "nack"
+        else:
+            return "ack"
+
+    def write(self, data, last):
+        self.wr_reg(self.R_TXR, data)
+        cmd = self.CR_WR
+        if(last):
+            cmd = cmd | self.CR_STO
+        self.wr_reg(self.R_CR, cmd)
+        self.wait_busy()
+        if(self.rd_reg(self.R_SR) & self.SR_RXACK):
+            raise Exception('No ACK upon write')
+
+    def read(self, last):
+        cmd = self.CR_RD
+        if(last):
+            cmd = cmd | self.CR_STO | self.CR_ACK
+        self.wr_reg(self.R_CR, cmd)
+        self.wait_busy()
+
+        return self.rd_reg(self.R_RXR)
+
+    def scan(self):
+        for i in range(0,128):
+            addr = i << 1
+            addr |= 1
+            self.wr_reg(self.R_TXR, addr)
+            self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR)
+            self.wait_busy()
+
+            if(not(self.rd_reg(self.R_SR) & self.SR_RXACK)):
+                print("Device found at address: %.2X") % i
+                self.wr_reg(self.R_TXR, 0)
+                self.wr_reg(self.R_CR, self.CR_STO | self.CR_WR)
+                self.wait_busy()
+
+
+##########################################
+# Usage example
+#gennum = rr.Gennum();
+#i2c = COpenCoresI2C(gennum, 0x80000, 500);
+#i2c.scan()
--- a/test/spec/python/libfpga_loader.so
+++ b/test/spec/python/libfpga_loader.so
--- a/test/spec/python/spi.py
+++ b/test/spec/python/spi.py
+#!/usr/bin/python
+
+import sys
+import rr
+import time
+
+class COpenCoresSPI:
+
+	R_RX = [0x00, 0x04, 0x08, 0x0C]
+	R_TX = [0x00, 0x04, 0x08, 0x0C]
+	R_CTRL = 0x10
+	R_DIV = 0x14
+	R_SS = 0x18
+
+	LGH_MASK = (0x7F)
+	CTRL_GO = (1<<8)
+        CTRL_BSY = (1<<8)
+	CTRL_RXNEG = (1<<9)
+	CTRL_TXNEG = (1<<10)
+	CTRL_LSB = (1<<11)
+       	CTRL_IE = (1<<12)
+        CTRL_ASS = (1<<13)
+
+        DIV_MASK = (0xFFFF)
+
+        SS_SEL = [0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40]
+
+	conf = 0x0
+
+	def wr_reg(self, addr, val):
+		self.bus.iwrite(0, self.base_addr +  addr, 4, val)
+
+	def rd_reg(self, addr):
+		return self.bus.iread(0, self.base_addr + addr, 4)
+
+	def __init__(self, bus, base_addr, divider):
+		self.bus = bus;
+		self.base_addr = base_addr;
+		self.wr_reg(self.R_DIV, (divider & self.DIV_MASK));
+		# default configuration
+		self.conf = self.CTRL_ASS | self.CTRL_TXNEG
+
+	def wait_busy(self):
+		while(self.rd_reg(self.R_CTRL) & self.CTRL_BSY):
+			pass
+
+	def config(self, ass, rx_neg, tx_neg, lsb, ie):
+		self.conf = 0
+		if(ass):
+			self.conf |= self.CTRL_ASS
+		if(tx_neg):
+			self.conf |= self.CTRL_TXNEG
+		if(rx_neg):
+			self.conf |= self.CTRL_RXNEG
+		if(lsb):
+			self.conf |= self.CTRL_LSB
+		if(ie):
+			self.conf |= self.CTRL_IE
+
+	# slave = slave number (0 to 7)
+	# data = byte data array to send, in case if read fill with dummy data of the right size
+	def transaction(self, slave, data):
+		txrx = [0x00000000, 0x00000000, 0x00000000, 0x00000000]
+		for i in range(0,len(data)):
+			txrx[i/4] += (data[i]<<((i%4)*8))
+			#print("tx[%d]=%.8X data[%d]=%.2X") %(i,txrx[i/4],i,data[i])
+
+		for i in range(0, len(txrx)):
+			self.wr_reg(self.R_TX[i], txrx[i])
+
+		self.wr_reg(self.R_SS, self.SS_SEL[slave])
+		self.wr_reg(self.R_CTRL, (self.LGH_MASK & (len(data)<<3)) | self.CTRL_GO | self.conf)
+		self.wait_busy()
+
+		for i in range(0, len(txrx)):
+			txrx[i] = self.rd_reg(self.R_RX[i])
+			#print("rx[%d]=%.8X") %(i,txrx[i])
+
+		return txrx
+
+#gennum = rr.Gennum();
+#spi = COpenCoresSPI(gennum, 0x80000, 500);
--- a/test/spec/python/test00.py
+++ b/test/spec/python/test00.py
+#!/acc/src/dsc/drivers/cohtdrep/siglesia/Python-2.7/python
+
+import sys
+import rr
+import time
+import os
+from tpsexcept import *
+
+BASE_GPIO = 0x40000
+BASE_MINIC = 0xc0000
+GPIO_CODR = 0x0
+GPIO_SODR = 0x4
+GPIO_PSR = 0xc
+        	
+class COpenCoresI2C:
+	R_PREL = 0x0
+	R_PREH = 0x4
+	R_CTR = 0x8
+	R_TXR = 0xC
+	R_RXR = 0xC
+	R_CR = 0x10
+	R_SR = 0x10
+	
+	CTR_EN = (1<<7)
+	
+	CR_STA = (1<<7)
+	CR_STO = (1<<6)
+	CR_WR = (1<<4)
+	CR_RD = (1<<5)
+	CR_NACK = (1<<3)
+	
+	SR_RXACK = (1<<7)
+	SR_TIP = (1<<1)
+	
+	
+	def wr_reg(self, addr, val):
+		self.bus.iwrite(0, self.base +  addr, 4, val)
+
+	def rd_reg(self,addr):
+		return self.bus.iread(0, self.base + addr, 4)
+	
+	def __init__(self, bus, base, prescaler):
+		self.bus = bus;
+		self.base =base;
+		self.wr_reg(self.R_CTR, 0);
+		self.wr_reg(self.R_PREL, (prescaler & 0xff))
+		self.wr_reg(self.R_PREH, (prescaler >> 8))
+		self.wr_reg(self.R_CTR, self.CTR_EN);
+	
+	def wait_busy(self):
+		while(self.rd_reg(self.R_SR) & self.SR_TIP):
+			pass
+	
+	def start(self, addr, write_mode):
+		addr = addr << 1
+		if(write_mode == False):
+			addr = addr | 1;
+		self.wr_reg(self.R_TXR, addr);
+		self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR);
+		self.wait_busy()
+		
+		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
+			raise Exception('No ACK upon address (device 0x%x not connected?)' % addr)
+
+	def write(self, data, last):
+		self.wr_reg(self.R_TXR, data);
+		cmd = self.CR_WR;
+		if(last):
+			cmd = cmd | self.CR_STO;
+		self.wr_reg(self.R_CR, cmd);
+		self.wait_busy();
+		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
+			raise Exception('No ACK upon write')
+
+	def read(self, last):
+		cmd = self.CR_RD;
+		if(last):
+			cmd = cmd | self.CR_STO | self.CR_NACK;
+		self.wr_reg(self.R_CR, cmd);
+		self.wait_busy();
+		
+		return self.rd_reg(self.R_RXR);
+
+class ADC_AD7997:
+	CONVER_R = 0x00;
+	CONFIG_R = 0x02;
+	CH8 = (1 << 11);
+	CH7 = (1 << 10);
+	CH6 = (1 << 9);
+	CH5 = (1 << 8);
+	CH4 = (1 << 7);
+	CH3 = (1 << 6);
+	CH2 = (1 << 5);
+	CH1 = (1 << 4);
+
+	def __init__(self, i2c, addr):
+		self.i2c = i2c;
+		self.addr = addr;
+
+	def wr_reg16(self, addr, value):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		tmp = (value >> 8) & 0xFF;
+		self.i2c.write(value, False);
+		tmp = value & 0xFF;
+		self.i2c.write(value, True)
+
+	def wr_reg8(self, addr, value):
+		self.i2c.start(self.addr, True); # write cycle
+		self.i2c.write(addr, False);
+		self.i2c.write(value, True);	
+
+	def rd_reg16(self, addr):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		self.i2c.start(self.addr, False);
+		tmp_MSB = self.i2c.read(False);
+		tmp_LSB = self.i2c.read(True);
+		value = (tmp_MSB << 8) | tmp_LSB;
+		return value;
+
+	def rd_reg8(self, addr):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		self.i2c.start(self.addr, False);
+		return self.i2c.read(True);	
+
+def adc_value(value) :
+	return str(2.495 * (0x3FF & (value >> 2)) / 1024); # 10 bits
+	
+def 	main ():
+
+    	bitstream_name = 'test_voltage_fmc.bin'
+    	os.system('/user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/fpga_loader_test /user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/'+bitstream_name);
+    	time.sleep(1);
+    
+	gennum = rr.Gennum();
+
+	i2c = COpenCoresI2C(gennum, 0x40000, 99); # Prescaler value calculated using 50 MHz clock
+
+	# The address of the AD7997 is 0x23, pin 15 connected to GND.
+	adc = ADC_AD7997(i2c, 0x23);
+
+	value8 = adc_value(adc.rd_reg16(0xF0));
+	value7 = adc_value(adc.rd_reg16(0xE0));
+	value6 = adc_value(adc.rd_reg16(0xD0));
+	value5 = adc_value(adc.rd_reg16(0xC0));
+	value4 = adc_value(adc.rd_reg16(0xB0));
+	value3 = adc_value(adc.rd_reg16(0xA0));
+	value2 = adc_value(adc.rd_reg16(0x90));
+	value1 = adc_value(adc.rd_reg16(0x80));
+
+	# Check the values of the ADC.
+	if(float(value8) < 2.0) :
+		raise TpsError ("Error in VS_VADJ, value " + value8 + " < 2.0")
+	print "VS_VADJ = " + value8
+
+	if(float(value7) < 2.0) :
+		raise TpsError ("Error in VS_P12V_x, value " + value7 + " < 2.0")
+	print "VS_P12V_x = " + value7
+
+	if(float(value6) < 1.57) :
+		raise TpsError ("Error in VS_P3V3_x, value " + value6 + " < 1.57")
+	print "VS_P3V3_x = " + value6
+
+	if(float(value5) < 2.52) :
+		raise TpsWarning ("Error in P5V_BI, value " + value5 + " < 2.52")
+	print "P5V_BI = " + value5
+
+	if(float(value4) > 2.0) :
+		raise TpsWarning ("Error in M2V_BI, value " + value4 + " > 2.0")
+	print "M2V_BI = " + value4
+
+	if(float(value3) > 2.28) :
+		raise TpsWarning ("Error in M5V2_BI, value " + value3 + " > 2.28")
+	print "M5V2_BI = " + value3
+
+	if(float(value2) > 2.4) :
+		raise  TpsWarning ("Error in M12V_BI, value " + value2 + " > 2.4")
+	print "M12V_BI = " + value2
+
+	if(float(value1) < 2.0) :
+		raise TpsWarning( "Error in P12V_BI, value " + value1 + " < 2.0")
+	print "P12V_BI = " + value1
+
+
+
--- a/test/spec/python/test02.py
+++ b/test/spec/python/test02.py
--- a/test/spec/python/test03.py
+++ b/test/spec/python/test03.py
+#!/acc/src/dsc/drivers/cohtdrep/siglesia/Python-2.7/python
+# It needs Python 2.7 or higher!
+
+import sys
+import rr
+import time
+import os
+from ctypes import *
+from tpsexcept import *
+
+class CGennumFlash :
+    	GENNUM_FLASH = 1;
+    	GENNUM_FPGA = 2;
+    	FPGA_FLASH = 3; 
+
+	def __init__ (self, bus):
+        	self.bus = bus;
+	        self.lib = cdll.LoadLibrary("libfpga_loader.so");
+        	self.lib.rr_init();
+	        self.lib.gpio_init();
+
+
+def main():
+
+    gennum = rr.Gennum();
+    flash = CGennumFlash(gennum);
+
+    start = time.time();
+    flash.lib.gpio_bootselect(flash.GENNUM_FLASH);
+    version = hex(flash.lib.flash_read_id());
+    if (version != "0x202016"):
+	raise TpsError('Error: version of the flash is not correct: ' + version);
+    
+    # Load a new firmware to the Flash memory.
+    print "Starting the process to load a FW into Flash memory"
+    flash.lib.load_mcs_to_flash("./test_flash.bin");
+
+    time.sleep(1);
+    print "Forcing to load FW from Flash memory to FPGA"
+
+    # Force the FPGA to load the FW from the Flash memory
+
+    flash.lib.force_load_fpga_from_flash();
+    
+    finish = time.time();
+
+    print "Time elapsed: " + str(finish - start) + " seconds" 
+
+    ask = "";
+    tmp_stdout = sys.stdout;
+    sys.stdout = sys.__stdout__;
+    tmp_stdin = sys.stdin;
+    sys.stdin = sys.__stdin__;
+    while ((ask != "Y") and (ask != "N")) :
+    	ask = raw_input("Are the LEDs blinking? [Y/N]")
+
+    sys.stdout = tmp_stdout;
+    sys.stdin = tmp_stdin;
+    if (ask == "N") :
+	raise TpsError("Error loading FW through the Flash memory");
+
+
+    
+        
+            
+        
+                
+    
--- a/test/spec/python/test07.py
+++ b/test/spec/python/test07.py
+#!/acc/src/dsc/drivers/cohtdrep/siglesia/Python-2.7/python
+#    coding: utf8
+
+import sys
+import rr
+import random
+import time
+import spi
+import i2c
+import gn4124
+import os
+
+
+GN4124_CSR = 0x0
+
+def main():
+
+    bitstream_name = 'test_ddr.bin'
+    os.system('/user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/fpga_loader_test /user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/'+bitstream_name);
+    time.sleep(1);
+
+
+    # Objects declaration
+    spec = rr.Gennum() # bind to the SPEC board
+    gennum = gn4124.CGN4124(spec, GN4124_CSR)
+
+    print '\n### Configuration ###'
+
+    # Set local bus frequency
+    gennum.set_local_bus_freq(160)
+    print("GN4124 local bus frequency: %d") % gennum.get_local_bus_freq()
+
+    print '\nStart test'
+
+    # Get host memory pages physical address
+    pages = gennum.get_physical_addr()
+
+    num_addr_lines = 64;
+    num_data_lines = 16;
+
+    if (len(pages) < (num_addr_lines + 2)) :
+	raise Exception("Not enough pages");
+
+    # Clear memory pages
+    gennum.set_memory_page(0, 0x0)
+    gennum.set_memory_page(1, 0xBABEFACE)
+    gennum.set_memory_page(2, 0x0)
+    dma_length = 0x400 # DMA length in bytes
+
+    t1 = time.time();
+
+    print "Test Address lines"
+    error = 0;
+    for i in range(num_addr_lines) :
+	if (i==0) :
+		continue;
+
+	for j in range(num_addr_lines/2) :
+            t3 = time.time();
+            if (i != 2*j) :
+                gennum.add_dma_item((1 << 2*j), pages[2], dma_length, 1, 1)
+                gennum.add_dma_item((1 << 2*j), pages[3+2*j], dma_length, 0, 0)
+            	gennum.start_dma()
+            	gennum.wait_irq()
+
+
+            if ((2*j+1) != i) :
+                gennum.add_dma_item((1 << (2*j+1)), pages[2], dma_length, 1, 1)
+                gennum.add_dma_item((1 << (2*j+1)), pages[3+(2*j+1)], dma_length, 0, 0)
+            	gennum.start_dma()
+            	gennum.wait_irq()
+
+        gennum.add_dma_item((1 << i), pages[1], dma_length, 1, 1)
+        gennum.add_dma_item((1 << i), pages[3+i], dma_length, 0, 0)
+        gennum.start_dma()
+        gennum.wait_irq()
+                                        
+
+	page_data = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];
+        for j in range(num_addr_lines):
+	    page_data[j] = gennum.get_memory_page(3+j)
+	    if (j == i) :
+		if (page_data[j][0] != 0xDEADFACE):
+                    print("\n### Compare error @ addr line:0x%.8X wr:0x%.8X rd:0x%.8X") % (j,0xDEADFACE, page_data[j][0])
+                    error = 1;
+            else :
+                if(page_data[j][0] != 0x0):
+                    print("\n### Compare error @ addr line:0x%.8X wr:0x%.8X rd:0x%.8X") % (j,0x0, page_data[j][0])
+                    error = 1;
+
+    if (error) :
+	print "RESULT: [FAILED]"
+    else :
+	print "RESULT: [OK]"
+
+    print "Test Data lines"
+    error = 0;
+    for i in range(num_data_lines) :
+	
+    	gennum.set_memory_page(1, (1<<i))
+        gennum.add_dma_item(0, pages[1], dma_length, 1, 1)
+        gennum.add_dma_item(0, pages[2], dma_length, 0, 0)
+        gennum.start_dma()
+        gennum.wait_irq()
+	page_data = gennum.get_memory_page(2);
+
+	if (page_data[0] != (1 << i)) :
+	    print("### Compare error @ data line:0x%.8X wr:0x%.8X rd:0x%.8X") % (i,(1 << i), page_data[0])
+	    error = 1;
+
+    if (error) :
+	print "RESULT: [FAILED]"
+    else :
+	print "RESULT: [OK]"
+
+    t2 = time.time();
+    print 'End of test'
+    print 'Time DDR test: ' + str(t2-t1) + ' seconds'
--- a/test/spec/python/test08.py
+++ b/test/spec/python/test08.py
--- a/test/spec/python/test_flash.mcs
+++ b/test/spec/python/test_flash.mcs