Commit 1447116b authored by Ross Millar's avatar Ross Millar

clean test00.

parent f940f2f0
#! /usr/bin/env python
x1#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
......@@ -22,14 +22,14 @@ test00: Load firmware and test mezzanine presence line.
def main (default_directory='.'):
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/TestSuite.bin';
path_firmware = '../firmwares/TestSuite.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
# Objects declaration
spec = rr.Gennum()
spec = rr.Gennum()
fmc = fmc_adc_test_suite.CFmcAdc100ks(spec)
# Check bitsteam type
......@@ -41,8 +41,7 @@ def main (default_directory='.'):
if(bitstream_type != 0x1):
raise PtsCritical ("Wrong bitstream type.")
print "Pts Critical - wrong bitstream"
# Dump carrier CSR to log
print("PCB version : %d") % ( fmc.pcb_version() ) # used to be a mask here
print("Carrier type : %d") % ( fmc.carrier_type()) # and here
......
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