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Production Test Suite
Commit 2a795cac authored by Matthieu Cattin's avatar Matthieu Cattin
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demo GUI.

parent 76df2b74
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @ 2a795cac
......@@ -232,12 +232,13 @@ class CFmcAdc100Ms:
return self.eeprom_24aa64.rd_data(addr, size)
# Set input range
def set_input_range(self, channel, range):
def set_input_range(self, channel, in_range):
addr = self.channel_addr(channel,self.R_CH1_SSR)
reg = (self.IN_TERM_MASK & self.fmc_adc_csr.rd_reg(addr))
#print("ssr reg ch%1d: %.8X") %(channel, reg)
if(range in self.IN_RANGES):
reg |= self.IN_RANGES[range]
#print('[set_in_range] Channel %d Input range: %s')%(channel,in_range)
if(in_range in self.IN_RANGES):
reg |= self.IN_RANGES[in_range]
else:
raise Exception('Unsupported parameter.')
#print("ssr reg ch%1d: %.8X") %(channel, reg)
......@@ -268,6 +269,19 @@ class CFmcAdc100Ms:
else:
raise Exception('Unsupported parameter, channel number from 1 to 4')
# Set DC offset
def set_dc_offset(self, channel, offset):
if(1 == channel):
self.dac_ch1.set_offset(offset)
elif(2 == channel):
self.dac_ch2.set_offset(offset)
elif(3 == channel):
self.dac_ch3.set_offset(offset)
elif(4 == channel):
self.dac_ch4.set_offset(offset)
else:
raise Exception('Unsupported parameter, channel number from 1 to 4')
# Reset DC offset DACs
def dc_offset_reset(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
......@@ -466,6 +480,10 @@ class CFmcAdc100Ms:
time.sleep(.1)
self.fmc_adc_csr.wr_reg(self.R_SW_TRIG, 0xFFFFFFFF)
# Software trigger without wait on WAIT_TRIG state
def sw_trig_no_wait(self):
self.fmc_adc_csr.wr_reg(self.R_SW_TRIG, 0xFFFFFFFF)
# Set pre-trigger samples
def set_pre_trig_samples(self, samples):
self.fmc_adc_csr.wr_reg(self.R_PRE_SAMPLES, samples)
......@@ -488,6 +506,10 @@ class CFmcAdc100Ms:
def get_trig_pos(self):
return self.fmc_adc_csr.rd_reg(self.R_TRIG_POS)
# Get number of acquired samples
def get_nb_samples(self):
return self.fmc_adc_csr.rd_reg(self.R_SAMP_CNT)
# Get serdes sync status
def get_serdes_sync_stat(self):
return (self.fmc_adc_csr.rd_bit(self.R_STA, self.STA_SERDES_SYNCED))
......
test/fmcadc100m14b4cha/python/fmc_adc_demo.py 0 → 100755
View file @ 2a795cac
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test/fmcadc100m14b4cha/python/fmc_adc_demo.ui 0 → 100755
View file @ 2a795cac
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test/fmcadc100m14b4cha/python/mplwidget.py 0 → 100644
View file @ 2a795cac
#!/usr/bin/python
from PyQt4 import QtGui
from matplotlib.backends.backend_qt4agg import FigureCanvasQTAgg as FigureCanvas
from matplotlib.figure import Figure
class MplCanvas(FigureCanvas):
def __init__(self):
self.fig = Figure()
self.ax = self.fig.add_subplot(111)
FigureCanvas.__init__(self, self.fig)
FigureCanvas.setSizePolicy(self,QtGui.QSizePolicy.Expanding,QtGui.QSizePolicy.Expanding)
FigureCanvas.updateGeometry(self)
class MplWidget(QtGui.QWidget):
def __init__(self, parent = None):
QtGui.QWidget.__init__(self, parent)
self.canvas = MplCanvas()
self.vbl = QtGui.QVBoxLayout()
self.vbl.addWidget(self.canvas)
self.setLayout(self.vbl)
test/fmcadc100m14b4cha/python/spec_fmc_adc.py
View file @ 2a795cac
......@@ -5,6 +5,8 @@ import sys
import rr
import random
import time
import math
import gn4124
import csr
import onewire
import ds18b20
......@@ -12,12 +14,20 @@ import ds18b20
class CSpecFmcAdc100Ms:
GNUM_CSR_ADDR = 0x00000
SPEC_ONEWIRE_ADDR = 0x20000
SPEC_CSR_ADDR = 0x30000
UTC_CORE_ADDR = 0x40000
IRQ_CONTROLLER_ADDR = 0x50000
# SPEC CSR
SPEC_CSR={0x00:'Carrier type, PCB version',
0x04:'Bitstream type',
0x08:'Bitstream date',
0x0C:'Status',
0x10:'Control'}
CSR_TYPE_VER = 0x00
CSR_BSTM_TYPE = 0x04
CSR_BSTM_DATE = 0x08
......@@ -51,14 +61,26 @@ class CSpecFmcAdc100Ms:
IRQ_CTRL_SRC = 0x4
IRQ_CTRL_EN_MASK = 0x8
IRQ_SRC_DMA_END = 0x1
IRQ_SRC_DMA_ERR = 0x2
IRQ_SRC_ACQ_TRG = 0x4
IRQ_SRC_ACQ_END = 0x8
# Gennum interface
DMA_LENGTH = 4096 # DMA length in bytes
def __init__(self, bus):
self.bus = bus
# Objects declaration
self.gnum = gn4124.CGN4124(self.bus, self.GNUM_CSR_ADDR)
self.spec_onewire = onewire.COpenCoresOneWire(self.bus, self.SPEC_ONEWIRE_ADDR, 624, 124)
self.ds18b20 = ds18b20.CDS18B20(self.spec_onewire, 0)
self.spec_csr = csr.CCSR(self.bus, self.SPEC_CSR_ADDR)
self.utc_core = csr.CCSR(self.bus, self.UTC_CORE_ADDR)
self.irq_controller = csr.CCSR(self.bus, self.IRQ_CONTROLLER_ADDR)
# Get physical addresses of the pages for DMA transfer
self.dma_pages = self.gnum.get_physical_addr()
def __del__(self):
pass
......@@ -206,4 +228,74 @@ class CSpecFmcAdc100Ms:
self.irq_controller.wr_reg(self.IRQ_CTRL_SRC, irq)
return self.irq_controller.rd_reg(self.IRQ_CTRL_SRC)
# Print CSR
def print_csr(self):
print("\nCarrier configuration/status")
for i in range(0,0x14,4):
print("%31s: 0x%.8X (%d)") % (self.SPEC_CSR[i],self.spec_csr.rd_reg(i),self.spec_csr.rd_reg(i))
# Make a DMA transfer
# carrier_addr and length are in bytes
def get_data(self, carrier_addr, length):
# Configure DMA
items_required = int(math.ceil(length/float(self.DMA_LENGTH)))
#print('Required items: %d')%items_required
for num in range(items_required):
if(items_required == num+1):
next_item = 0
item_length = ((carrier_addr+length)-(num*self.DMA_LENGTH))
else:
next_item = 1
item_length = self.DMA_LENGTH
if(0 == num):
item_start_addr = carrier_addr
else:
item_start_addr = carrier_addr + (num*self.DMA_LENGTH)
#print("item nb:%d item_carrier_addr:0x%.8X item_host_addr:0x%.8X item_length:%d next_item:%d)")%(num,item_start_addr,self.dma_pages[num+1],item_length,next_item)
self.gnum.add_dma_item(item_start_addr, self.dma_pages[num+1], item_length, 0, next_item)
items = self.gnum.get_memory_page(0)
#print('DMA items:')
#for i in range(items_required*8):
# print('%.4X: %.8X')%(i*4,items[i])
# Start DMA
self.gnum.start_dma()
# Wait for end of DMA interrupt
#print('Wait GN4124 interrupt')
self.gnum.wait_irq()
#print('GN4124 interrupt occured')
dma_finished = 0
#print('irq mask:%.4X')%self.get_irq_en_mask()
while(0 == dma_finished):
irq_src = self.get_irq_source()
#print('IRQ source : %.4X')%irq_src
#print('DMA status: %s')%self.gnum.get_dma_status()
if(irq_src & self.IRQ_SRC_DMA_END):
#print('IRQ source : %.4X')%irq_src
self.clear_irq_source(self.IRQ_SRC_DMA_END)
#print('IRQ source : %.4X')%self.get_irq_source()
dma_finished = 1
time.sleep(0.5)
#print('DMA finished!')
# Retrieve data from host memory
data = []
for i in range(items_required):
data += self.gnum.get_memory_page(i+1)
#print('data length:%d')%(len(data)*4)
channels_data = []
for i in range(length/4):
channels_data.append(data[i] & 0xFFFF)
channels_data.append(data[i]>>16)
#print('channels data length:%d')%(len(channels_data))
return channels_data
# Wait end of acquisition
def wait_end_acq(self):
acq_end = 0
while(0 == acq_end):
irq_src = self.get_irq_source()
print('IRQ source : %.4X')%irq_src
if(irq_src & self.IRQ_SRC_ACQ_END):
self.clear_irq_source(self.IRQ_SRC_ACQ_END)
print('IRQ source : %.4X')%self.get_irq_source()
acq_end = 1
print('ACQ finished!')
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