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Commit 45d1369d authored by Evangelia Gousiou's avatar Evangelia Gousiou
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svec_pts_gtp_pllclk renamed to svec_pts_gtp_clkpll

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test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/syn/gsi_pexaria2a/wishbone_demo/Manifest.py deleted 100644 → 0
View file @ eebdf8e7
target = "altera"
action = "synthesis"
#syn_device = "xc6slx45t"
#syn_grade = "-3"
#syn_package = "fgg484"
syn_top = "wishbone_demo"
syn_project = "wishbone_demo.qpf"
modules = {
"local" : [ "../../../top/gsi_pexaria2a/wishbone_demo" ]
}
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/syn/gsi_pexaria2a/wishbone_demo/wishbone_demo.qpf deleted 100644 → 0
View file @ eebdf8e7
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
# Date created = 12:33:22 May 18, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "12:33:22 May 18, 2012"
# Revisions
PROJECT_REVISION = "wishbone_demo"
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/syn/gsi_pexaria2a/wishbone_demo/wishbone_demo.qsf deleted 100644 → 0
View file @ eebdf8e7
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
# Date created = 12:33:22 May 18, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# wishbone_demo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Arria II GX"
set_global_assignment -name DEVICE EP2AGX125DF25C6ES
set_global_assignment -name TOP_LEVEL_ENTITY wishbone_demo_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:33:22 MAY 18, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SDC_FILE ../../../top/gsi_pexaria2a/wishbone_demo/wishbone_demo.sdc
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
set_global_assignment -name QIP_FILE ../../../modules/wishbone/wb_pcie/altera_pcie.qip
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_pcie.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_pcie_core.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_pcie_serdes.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_reconfig.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_dma/xwb_dma.vhd
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/platform/altera/jtag_tap.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_shifter.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_ram.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_logic_op.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_dp_ram.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_addsub.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_adder.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/jtag_cores.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_crossbar/xwb_crossbar.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_crossbar/sdb_rom.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_dpram/xwb_dpram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wishbone_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_sync_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_spram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_dpram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_async_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/generic_shiftreg_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_wfifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_dual_clock_ram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_sync_ffs.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_dual_pi_controller.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_delay_gen.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_extend_pulse.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_moving_average.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_crc_gen.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gencores_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_pexaria2a/wishbone_demo/sys_pll.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_pexaria2a/wishbone_demo/wishbone_demo_top.vhd
set_global_assignment -name QIP_FILE ../../../top/gsi_pexaria2a/wishbone_demo/sys_pll.qip
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_U23 -to pcie_refclk_i
set_location_assignment PIN_W1 -to pcie_rstn_i
set_location_assignment PIN_N23 -to pcie_rx_i[3]
set_location_assignment PIN_R23 -to pcie_rx_i[2]
set_location_assignment PIN_W23 -to pcie_rx_i[1]
set_location_assignment PIN_AA23 -to pcie_rx_i[0]
set_location_assignment PIN_M21 -to pcie_tx_o[3]
set_location_assignment PIN_P21 -to pcie_tx_o[2]
set_location_assignment PIN_V21 -to pcie_tx_o[1]
set_location_assignment PIN_Y21 -to pcie_tx_o[0]
set_location_assignment PIN_U9 -to leds_o[0]
set_location_assignment PIN_V9 -to leds_o[1]
set_location_assignment PIN_AA7 -to leds_o[2]
set_location_assignment PIN_AB7 -to leds_o[3]
set_location_assignment PIN_W9 -to leds_o[4]
set_location_assignment PIN_W10 -to leds_o[5]
set_location_assignment PIN_AA10 -to leds_o[6]
set_location_assignment PIN_AB10 -to leds_o[7]
set_location_assignment PIN_D11 -to clk125_i
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2]
set_location_assignment PIN_R24 -to "pcie_rx_i[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1]
set_location_assignment PIN_W24 -to "pcie_rx_i[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0]
set_location_assignment PIN_AA24 -to "pcie_rx_i[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3]
set_location_assignment PIN_M22 -to "pcie_tx_o[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2]
set_location_assignment PIN_P22 -to "pcie_tx_o[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1]
set_location_assignment PIN_V22 -to "pcie_tx_o[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0]
set_location_assignment PIN_Y22 -to "pcie_tx_o[0](n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pcie_rstn_i
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
set_instance_assignment -name IO_STANDARD LVDS -to clk125_i
set_location_assignment PIN_C11 -to "clk125_i(n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/testbench/wishbone/lm32_testsys/sw/board.h deleted 100644 → 0
View file @ eebdf8e7
#ifndef __BOARD_H
#define __BOARD_H
#define BASE_GPIO 0x20000000
static inline int delay(int x)
{
while(x--) asm volatile("nop");
}
#endif
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/testbench/wishbone/lm32_testsys/sw/gpio.h deleted 100644 → 0
View file @ eebdf8e7
#ifndef __GPIO_H
#define __GPIO_H
#include "inttypes.h"
#include "board.h"
struct GPIO_WB
{
uint32_t CODR; /*Clear output register*/
uint32_t SODR; /*Set output register*/
uint32_t DDR; /*Data direction register (1 means out)*/
uint32_t PSR; /*Pin state register*/
};
static volatile struct GPIO_WB *__gpio = (volatile struct GPIO_WB *) BASE_GPIO;
static inline void gpio_out(int pin, int val)
{
if(val)
__gpio->SODR = (1<<pin);
else
__gpio->CODR = (1<<pin);
}
static inline void gpio_dir(int pin, int val)
{
if(val)
__gpio->DDR |= (1<<pin);
else
__gpio->DDR &= ~(1<<pin);
}
static inline int gpio_in(int pin)
{
return __gpio->PSR & (1<<pin) ? 1: 0;
}
#endif
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/testbench/wishbone/lm32_testsys/sw/inttypes.h deleted 100644 → 0
View file @ eebdf8e7
#ifndef __WRAPPED_INTTYPES_H
#define __WRAPPED_INTTYPES_H
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef signed long long uint64_t;
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef signed long long int64_t;
#endif
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/testbench/wishbone/lm32_testsys/sw/uart.h deleted 100644 → 0
View file @ eebdf8e7
#ifndef __UART_H
#define __UART_H
int mprintf(char const *format, ...);
void uart_init();
void uart_write_byte(unsigned char x);
#endif
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/testbench/wishbone/lm32_testsys/sw/wb_uart.h deleted 100644 → 0
View file @ eebdf8e7
/*
Register definitions for slave core: Simple Wishbone UART
* File : wb_uart.h
* Author : auto-generated by wbgen2 from simple_uart_wb.wb
* Created : Tue Oct 4 18:46:41 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB
#define __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Host VUART Tx register */
/* definitions for field: TX Data in reg: Host VUART Tx register */
#define UART_HOST_TDR_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_HOST_TDR_DATA_SHIFT 0
#define UART_HOST_TDR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_HOST_TDR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: TX Ready in reg: Host VUART Tx register */
#define UART_HOST_TDR_RDY WBGEN2_GEN_MASK(8, 1)
/* definitions for register: Host VUART Rx register */
/* definitions for field: RX Data in reg: Host VUART Rx register */
#define UART_HOST_RDR_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_HOST_RDR_DATA_SHIFT 0
#define UART_HOST_RDR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_HOST_RDR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: RX Ready in reg: Host VUART Rx register */
#define UART_HOST_RDR_RDY WBGEN2_GEN_MASK(8, 1)
/* definitions for field: RX FIFO Count in reg: Host VUART Rx register */
#define UART_HOST_RDR_COUNT_MASK WBGEN2_GEN_MASK(9, 16)
#define UART_HOST_RDR_COUNT_SHIFT 9
#define UART_HOST_RDR_COUNT_W(value) WBGEN2_GEN_WRITE(value, 9, 16)
#define UART_HOST_RDR_COUNT_R(reg) WBGEN2_GEN_READ(reg, 9, 16)
PACKED struct UART_WB {
/* [0x0]: REG Status Register */
uint32_t SR;
/* [0x4]: REG Baudrate control register */
uint32_t BCR;
/* [0x8]: REG Transmit data regsiter */
uint32_t TDR;
/* [0xc]: REG Receive data regsiter */
uint32_t RDR;
/* [0x10]: REG Host VUART Tx register */
uint32_t HOST_TDR;
/* [0x14]: REG Host VUART Rx register */
uint32_t HOST_RDR;
};
#endif
test/svec/VHDL/svec_pts_gtp_pllclk/ip_cores/general-cores/testbench/wishbone/lm32_testsys/sw/wb_vuart.h deleted 100644 → 0
View file @ eebdf8e7
/*
Register definitions for slave core: Simple Wishbone UART
* File : wb_uart.h
* Author : auto-generated by wbgen2 from uart.wb
* Created : Mon Jul 18 01:19:24 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_UART_WB
#define __WBGEN2_REGDEFS_UART_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Status Register */
#define UART_REG_SR 0x00000000
/* [0x4]: REG Baudrate control register */
#define UART_REG_BCR 0x00000004
/* [0x8]: REG Transmit data regsiter */
#define UART_REG_TDR 0x00000008
/* [0xc]: REG Receive data regsiter */
#define UART_REG_RDR 0x0000000c
#endif
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