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9108c6e0
Commit
9108c6e0
authored
Jul 24, 2013
by
Matthieu Cattin
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fmc_adc_svec: Add support for wbgen2 interrupt controller and an interrupt test.
parent
045edf58
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3 changed files
with
191 additions
and
37 deletions
+191
-37
fmc_adc_svec.py
test/fmcadc100m14b4cha/python/fmc_adc_svec.py
+17
-34
svec_irq_controller_regs.py
test/fmcadc100m14b4cha/python/svec_irq_controller_regs.py
+9
-3
svec_test02.py
test/fmcadc100m14b4cha/python/svec_test02.py
+165
-0
No files found.
test/fmcadc100m14b4cha/python/fmc_adc_svec.py
View file @
9108c6e0
...
...
@@ -47,13 +47,6 @@ class CFmcAdc100mSvec:
# Onewire core port
DS18B20_PORT
=
0
# IRQ controller
IRQ_SRC_DMA_END
=
0x1
IRQ_SRC_DMA_ERR
=
0x2
IRQ_SRC_ACQ_TRG
=
0x4
IRQ_SRC_ACQ_END
=
0x8
#======================================================================
# Class initialisation
...
...
@@ -208,45 +201,31 @@ class CFmcAdc100mSvec:
# Set IRQ enable mask
def
set_irq_en_mask
(
self
,
mask
):
try
:
self
.
irq_controller
.
set_reg
(
'EN_MASK'
,
mask
)
return
self
.
irq_controller
.
get_reg
(
'EN_MASK'
)
self
.
irq_controller
.
set_reg
(
'ENABLE'
,
mask
)
self
.
irq_controller
.
set_reg
(
'DISABLE'
,
~
mask
)
return
self
.
irq_controller
.
get_reg
(
'MASK'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
# Get IRQ enable mask
def
get_irq_en_mask
(
self
):
try
:
return
self
.
irq_controller
.
get_reg
(
'EN_MASK'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
# Returns multiple IRQ status
def
get_irq_mult
(
self
):
try
:
return
self
.
irq_controller
.
get_reg
(
'MULTI_IRQ'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
# Clears multiple IRQ status
def
clear_irq_mult
(
self
,
irq
):
try
:
self
.
irq_controller
.
set_reg
(
'MULTI_IRQ'
,
irq
)
return
self
.
irq_controller
.
get_reg
(
'MULTI_IRQ'
)
return
self
.
irq_controller
.
get_reg
(
'MASK'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
# Returns IRQ s
ource
def
get_irq_s
ource
(
self
):
# Returns IRQ s
tatus
def
get_irq_s
tatus
(
self
):
try
:
return
self
.
irq_controller
.
get_reg
(
'S
RC
'
)
return
self
.
irq_controller
.
get_reg
(
'S
TATUS
'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
# Clears
IRQ source
def
clear_i
rq_source
(
self
,
irq
):
# Clears
interrupt
def
clear_i
nterrupt
(
self
,
irq
):
try
:
self
.
irq_controller
.
set_reg
(
'S
RC
'
,
irq
)
return
self
.
irq_controller
.
get_reg
(
'S
RC
'
)
self
.
irq_controller
.
set_reg
(
'S
TATUS
'
,
irq
)
return
self
.
irq_controller
.
get_reg
(
'S
TATUS
'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
...
...
@@ -259,7 +238,9 @@ class CFmcAdc100mSvec:
fmc
=
'FMC1_ACQ_END'
else
:
raise
FmcAdc100mSvecOperationError
(
"Slot number out of range [0:1]"
)
return
self
.
irq_controller
.
set_field
(
'EN_MASK'
,
fmc
,
value
)
self
.
irq_controller
.
set_field
(
'ENABLE'
,
fmc
,
value
)
self
.
irq_controller
.
set_field
(
'DISABLE'
,
fmc
,
~
value
)
return
self
.
irq_controller
.
get_field
(
'MASK'
,
fmc
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
...
...
@@ -272,6 +253,8 @@ class CFmcAdc100mSvec:
fmc
=
'FMC1_ACQ_TRG'
else
:
raise
FmcAdc100mSvecOperationError
(
"Slot number out of range [0:1]"
)
return
self
.
irq_controller
.
set_field
(
'EN_MASK'
,
fmc
,
value
)
self
.
irq_controller
.
set_field
(
'ENABLE'
,
fmc
,
value
)
self
.
irq_controller
.
set_field
(
'DISABLE'
,
fmc
,
~
value
)
return
self
.
irq_controller
.
get_field
(
'MASK'
,
fmc
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSvecOperationError
(
e
)
test/fmcadc100m14b4cha/python/svec_irq_controller_regs.py
View file @
9108c6e0
...
...
@@ -10,19 +10,25 @@
# IRQ controller core registers
IRQ_CONTROLLER_REGS
=
[
'IRQ controller registers'
,
{
'
MULTI_IRQ'
:[
0x00
,
'Multiple interrupt
'
,
{
'
DISABLE'
:[
0x00
,
'Interrupt disable
'
,
{
'FMC0_ACQ_TRG'
:[
0
,
'FMC 1 acquisition triggered'
,
0x1
],
'FMC0_ACQ_END'
:[
1
,
'FMC 1 acquisition finished'
,
0x1
],
'FMC1_ACQ_TRG'
:[
2
,
'FMC 2 acquisition triggered'
,
0x1
],
'FMC1_ACQ_END'
:[
3
,
'FMC 2 acquisition finished'
,
0x1
],
'RESERVED'
:[
4
,
'Reserved'
,
0xFFFFFFF
]}],
'
SRC'
:[
0x04
,
'Interrupt sources
'
,
{
'
ENABLE'
:[
0x04
,
'Interrupt enable
'
,
{
'FMC0_ACQ_TRG'
:[
0
,
'FMC 1 acquisition triggered'
,
0x1
],
'FMC0_ACQ_END'
:[
1
,
'FMC 1 acquisition finished'
,
0x1
],
'FMC1_ACQ_TRG'
:[
2
,
'FMC 2 acquisition triggered'
,
0x1
],
'FMC1_ACQ_END'
:[
3
,
'FMC 2 acquisition finished'
,
0x1
],
'RESERVED'
:[
4
,
'Reserved'
,
0xFFFFFFF
]}],
'EN_MASK'
:[
0x08
,
'Interrupt enable mask'
,
{
'MASK'
:[
0x08
,
'Interrupt mask'
,
{
'FMC0_ACQ_TRG'
:[
0
,
'FMC 1 acquisition triggered'
,
0x1
],
'FMC0_ACQ_END'
:[
1
,
'FMC 1 acquisition finished'
,
0x1
],
'FMC1_ACQ_TRG'
:[
2
,
'FMC 2 acquisition triggered'
,
0x1
],
'FMC1_ACQ_END'
:[
3
,
'FMC 2 acquisition finished'
,
0x1
],
'RESERVED'
:[
4
,
'Reserved'
,
0xFFFFFFF
]}],
'STATUS'
:[
0x0C
,
'Interrupt status'
,
{
'FMC0_ACQ_TRG'
:[
0
,
'FMC 1 acquisition triggered'
,
0x1
],
'FMC0_ACQ_END'
:[
1
,
'FMC 1 acquisition finished'
,
0x1
],
'FMC1_ACQ_TRG'
:[
2
,
'FMC 2 acquisition triggered'
,
0x1
],
...
...
test/fmcadc100m14b4cha/python/svec_test02.py
0 → 100755
View file @
9108c6e0
#! ./python
# coding: utf8
# Copyright CERN, 2013
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Import system modules
import
sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../common/'
)
sys
.
path
.
append
(
'../../../../svec_pts/ubuntu/pts/pyts/'
)
# Import common modules
from
ptsexcept
import
*
from
rr2vv
import
*
# Import specific modules
from
fmc_adc_svec
import
*
from
fmc_adc
import
*
"""
test02: Test interrupts
"""
def
main
(
default_directory
=
'.'
):
# Constants declaration
LUN
=
0
TEST_NB
=
2
FMC_ADC_BITSTREAM
=
'../../../../../firmwares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x0
NB_CHANNELS
=
4
EEPROM_ADDR
=
0x50
SI570_ADDR
=
0x55
TEST_PATTERN
=
0x6A1
start_test_time
=
time
.
time
()
print
"
\n
================================================================================"
print
"==> [SVEC] Test
%02
d start
\n
"
%
TEST_NB
# SVEC object declaration
print
"Loading hardware access library and opening device.
\n
"
bus
=
VME_rr_compatible
(
LUN
)
print
"Initialising device.
\n
"
# Load FMC ADC firmware
ask
=
'N'
while
((
ask
!=
"Y"
)
and
(
ask
!=
"N"
))
:
ask
=
raw_input
(
"Do you want to load the firmware:
%
s? [y,n]"
%
(
FMC_ADC_BITSTREAM
))
ask
=
ask
.
upper
()
print
" "
if
(
ask
==
"Y"
):
print
"Loading FMC ADC firmware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
bus
.
vv_init
()
ret
=
bus
.
vv_load
(
FMC_ADC_BITSTREAM
,
1
)
print
(
''
)
time
.
sleep
(
2
)
else
:
bus
.
vv_open
()
# Carrier object declaration (SPEC board specific part)
try
:
carrier
=
CFmcAdc100mSvec
(
bus
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSvecOperationError
as
e
:
raise
PtsCritical
(
"Carrier init failed, test stopped:
%
s"
%
e
)
# Test carrier periherals
print
(
'
\n
-------------------------------------------------------------'
)
print
(
'[Carrier]'
)
carrier
.
print_unique_id
()
carrier
.
print_temp
()
# Mezzanines object declaration (FmcAdc100m14b4cha board specific part)
fmc
=
[]
for
i
in
range
(
2
):
try
:
print
(
'
\n
-------------------------------------------------------------'
)
print
(
'[FMC slot
%
d]'
%
(
i
+
1
))
mezz_offset
=
0x2000
+
i
*
0x4000
print
(
'Mezzanine offset: 0x
%08
X'
%
(
mezz_offset
))
fmc
.
append
(
CFmcAdc100m
(
bus
,
mezz_offset
))
except
FmcAdc100mOperationError
as
e
:
raise
PtsCritical
(
"Mezzanine
%
d init failed, test stopped:
%
s"
%
(
i
+
1
,
e
))
# Test mezzanines peripherals
error
=
[
''
,
''
]
for
i
in
range
(
2
):
try
:
print
(
'
\n
-------------------------------------------------------------'
)
print
(
'[FMC slot
%
d]'
%
(
i
+
1
))
# Disable and clear all interrupts
carrier
.
set_irq_en_mask
(
0x0
)
ret
=
carrier
.
get_irq_status
()
carrier
.
clear_interrupt
(
ret
)
# Enable trigger interrupt
carrier
.
print_irq_controller_regs
()
print
(
'Enable trigger interrupt'
)
carrier
.
set_irq_trig_mask
(
i
,
1
)
carrier
.
print_irq_controller_regs
()
# Acquisition setup
# hw trig, rising edge, external, sw disable, no delay
print
(
''
)
for
j
in
range
(
100
):
fmc
[
i
]
.
set_trig_config
(
1
,
0
,
1
,
1
,
1
,
0
,
0
)
fmc
[
i
]
.
set_pre_trig_samples
(
500
)
fmc
[
i
]
.
set_post_trig_samples
(
500
)
fmc
[
i
]
.
set_shots
(
1
)
fmc
[
i
]
.
stop_acq
()
print
"
%
d: Acquisition FSM state :
%
s (should be IDLE)"
%
(
j
,
fmc
[
i
]
.
get_acq_fsm_state
())
fmc
[
i
]
.
start_acq
()
#time.sleep(3)
print
"Wait for trigger."
# Wait from interrupt
ret
=
bus
.
vv_irqwait
()
print
(
'[irq wait] irq source reg = 0x
%.8
X'
%
ret
)
ret
=
carrier
.
get_irq_status
()
print
(
'irq status = 0x
%.8
X'
%
ret
)
time
.
sleep
(
1
)
ret
=
carrier
.
clear_interrupt
(
ret
)
print
(
'Clear interrupt, irq status = 0x
%.8
X'
%
ret
)
#carrier.print_irq_controller_regs()
time
.
sleep
(
1
)
# Disable trigger interrupt
print
(
'Disable trigger interrupt'
)
carrier
.
set_irq_trig_mask
(
i
,
0
)
carrier
.
print_irq_controller_regs
()
except
FmcAdc100mOperationError
as
e
:
raise
PtsError
(
"Mezzanine
%
d onewire test failed:
%
s"
%
(
i
+
1
,
e
))
print
(
''
)
print
"==> End of test
%02
d"
%
TEST_NB
print
"================================================================================"
end_test_time
=
time
.
time
()
print
"[SVEC] Test
%02
d elapsed time:
%.2
f seconds
\n
"
%
(
TEST_NB
,
end_test_time
-
start_test_time
)
if
(
error
[
0
]
!=
''
):
raise
PtsError
(
'[FMC slot 1]'
+
error
[
0
])
if
(
error
[
1
]
!=
''
):
raise
PtsError
(
'[FMC slot 2]'
+
error
[
1
])
bus
.
vv_close
()
if
__name__
==
'__main__'
:
main
()
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