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Commit b4ec16ba authored by Matthieu Cattin's avatar Matthieu Cattin
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fmc_adc: Add acquisition methods, fix get_data for svec.

parent 6580fe29
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Showing with 58 additions and 22 deletions
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @ b4ec16ba
......@@ -37,18 +37,7 @@ from fmcadc100m_csr import *
# Converts digital value to volts
def digital2volt(value, full_scale, nb_bit):
return float(value) * float(full_scale)/2**nb_bit - full_scale/2.0
# Converts volts to digital value with half full range offset
def volt2digital(value, full_scale, nb_bit):
digital = (value + full_scale/2) * 2**nb_bit/full_scale
if(digital > 2**nb_bit - 1):
digital = 2**nb_bit - 1
if(digital < 0):
digital = 0
#print('volt2digital: %2.9f > %2.9f')%(value,digital)
return int(digital)
return float(value) * float(full_scale)/2**nb_bit
# Converts two's complement hex to signed
def hex2signed(value):
......@@ -57,13 +46,6 @@ def hex2signed(value):
else:
return value
# Converts signed to two's complement hex
def signed2hex(value):
if value < 0:
return (((abs(value) ^ 0xffff) + 1) & 0xffff)
else:
return value
# Class to access fmcadc100m14b4cha mezzanine specific Wishbone cores
......@@ -889,7 +871,7 @@ class CFmcAdc100m:
# Read data from DDR
# carrier_addr and length are in 32-bit word
def get_data(self, carrier_addr, length):
def get_data(self, carrier_addr, length, raw=False):
ret = []
data = []
cc = self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, carrier_addr)
......@@ -900,10 +882,13 @@ class CFmcAdc100m:
#print('[get_data] read: addr=0x%.9X i=%d'%(self.DDR_DAT_ADDR, i))
#adr_cnt = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
#print('[get_data] address counter: before=0x%.8X after=0x%.8X'%(adr_cnt_b, adr_cnt))
for i in range(length/4):
for i in range(length):
ret.append(data[i] & 0xFFFF)
ret.append(data[i]>>16)
return ret
if raw:
return data # 32-bit data array
else:
return ret # 16-bit data array
# Write data to DDR
# carrier_addr is in 32-bit word
......@@ -923,3 +908,54 @@ class CFmcAdc100m:
for i in range(0x4000000):
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, 0x0)
#======================================================================
# Acquisition
def open_all_channels(self):
for i in range(1,5):
self.set_input_range(i, 'OPEN')
time.sleep(0.05)
def acq_init(self, pre_trig=100, post_trig=1000, nb_shots=1):
# Reset offset DACs
self.dc_offset_reset()
# Make sure all switches are OFF
self.open_all_channels()
# Set software trigger
self.set_soft_trig()
# Set acquisition
self.set_pre_trig_samples(pre_trig)
self.set_post_trig_samples(post_trig)
self.set_shots(nb_shots)
def acq_channels(self, carrier_type, carrier, adc_fs, acq_length=1000, pause=1, timeout=10):
# Make sure no acquisition is running
self.stop_acq()
time.sleep(0.05)
# Start acquisition
self.start_acq()
time.sleep(pause)
# Trigger
self.sw_trig()
# Wait end of acquisition
timeout_cnt = 0
while('IDLE' != self.get_acq_fsm_state()):
time.sleep(.1)
timeout_cnt += 1
if(timeout < timeout_cnt):
raise FmcAdc100mOperationError('Acquisition timeout. Missing trigger?\nAcq FSM state: %s'%self.get_acq_fsm_state())
# Retrieve data from DDR memory
# Read ACQ_LENGTH samples after the trigger for all channels
trig_pos = self.get_trig_pos()
if carrier_type == 'spec':
channels_data = self.get_data((trig_pos<<3), acq_length*8)
elif carrier_type == 'svec':
channels_data = self.get_data((trig_pos<<3), acq_length*8)
else:
raise FmcAdc100mOperationError('Unsupported carrier type: %s'%carrier_type)
#print [hex(val) for val in channels_data[0::4][:10]]
channels_data = [hex2signed(item) for item in channels_data]
#print [hex(val) for val in channels_data[0::4][:10]]
channels_data = [digital2volt(item,adc_fs,16) for item in channels_data]
#print channels_data[0::4][:10]
return channels_data
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