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Production Test Suite
Commit ba20a0fe authored by Richard R. Carrillo's avatar Richard R. Carrillo Committed by Benoit Rat
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SPEC test07 modified to test all DDR memory address lines

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test/spec/python/gn4124.py
View file @ ba20a0fe
......@@ -166,6 +166,7 @@ class CGN4124:
# Start DMA transfer
def start_dma(self):
self.wr_reg(0,0x50000 + 2*4, 1) # Enable interrupt
self.dma_item_cnt = 0
self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 1)
# The following two lines should be removed
......
test/spec/python/test07.py
View file @ ba20a0fe
#! /usr/bin/env python
# coding: utf8
#!/usr/bin/python
#coding: utf8
# Copyright CERN, 2011
# Author: Samuel Iglesias Gonsalvez <siglesia@cern.ch>
# Copyright CERN, 2012 (Seven Solutions S.L.)
# Author: Richard Carrillo <rcarrillo(AT)sevensols.com>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Website: http://www.sevensols.com
# Version: 1.0 (Last modifications: 21/12/2012)
# remove unused libraries?
import sys
import rr
import random
......@@ -18,169 +21,129 @@ import os
from ptsexcept import *
"""
test07: checks data and address lines of DDR memory.
test07: Check the connectivity of data and address lines of DDR memory
Conditions: SPEC board correctly configured (test00 passed and jumper removed)
User intervention required: No
Procedure details:
- Load FPGA firmware
- Set local bus frequency
- Test the connectivity of address lines
- Test the connectivity of data lines
"""
GN4124_CSR = 0x0
def main (default_directory='.'):
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/test07.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gennum = gn4124.CGN4124(spec, GN4124_CSR)
print '\n### Configuration ###'
# Set local bus frequency
gennum.set_local_bus_freq(160)
print("GN4124 local bus frequency: %d") % gennum.get_local_bus_freq()
print '\nStart test'
# Get host memory pages physical address
pages = gennum.get_physical_addr()
num_addr_lines = 19;
num_data_lines = 16;
if (len(pages) < (num_addr_lines + 2)) :
raise PtsError("Not enough pages");
data = 0xDEADBABE
# Clear memory pages
gennum.set_memory_page(0, 0x0)
gennum.set_memory_page(1, data);
gennum.set_memory_page(2, 0x0)
dma_length = 0x4 # DMA length in bytes
t1 = time.time();
print "Test Address lines"
print "Checking if some pin is tied to GND"
error = 0;
for i in range(1,num_addr_lines) :
print "[%d]" % i
for j in range(1,num_addr_lines) :
gennum.add_dma_item((1 << j), pages[0], dma_length, 1, 0)
gennum.start_dma()
gennum.wait_irq()
time.sleep(0.01)
time.sleep(0.01)
gennum.add_dma_item((1 << i), pages[1], dma_length, 1, 0)
gennum.start_dma()
gennum.wait_irq()
# Read all the pages
for j in range(1,num_addr_lines) :
time.sleep(0.01)
gennum.add_dma_item((1 << j), pages[3+j], dma_length, 0, 0)
gennum.start_dma()
gennum.wait_irq()
# Compare
page_data = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];
for j in range(1,num_addr_lines):
page_data[j] = gennum.get_memory_page(3+j)
if (j == i) :
if (page_data[j][0] != data):
print("\n### Compare error (pin is tied to GND?) @ addr line: %d wr:0x%.8X rd:0x%.8X") % (j,data, page_data[j][0])
error = 1;
else :
if(page_data[j][0] != 0x0):
print("\n### Compare error (pin is tied to GND?) @ addr line: %d wr:0x%.8X rd:0x%.8X") % (j,0x0, page_data[j][0])
error = 1;
print "Checking if some pin is tied to Vcc"
addr_mask = 0xFFFFFFFFFFFFFFFF;
for i in range(1,num_addr_lines) :
print "[%d]" % i
for j in range(1,num_addr_lines) :
gennum.add_dma_item(~(1 << j), pages[0], dma_length, 1, 0)
gennum.start_dma()
gennum.wait_irq()
time.sleep(0.01)
time.sleep(0.01)
gennum.add_dma_item(~(1 << i), pages[1], dma_length, 1, 0)
gennum.start_dma()
gennum.wait_irq()
# Read all the pages
for j in range(1,num_addr_lines) :
time.sleep(0.01)
gennum.add_dma_item(~(1 << j), pages[3+j], dma_length, 0, 0)
gennum.start_dma()
gennum.wait_irq()
time.sleep(0.01)
page_data = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];
for j in range(1,num_addr_lines):
page_data[j] = gennum.get_memory_page(3+j)
if (j == i) :
if (page_data[j][0] != data):
print("\n### Compare error (pin is tied to Vcc?) @ addr line:0x%.8X wr:0x%.8X rd:0x%.8X") % (j,data, page_data[j][0])
error = 1;
else :
if(page_data[j][0] != 0x0):
print("\n### Compare error (pin is tied to Vcc?) @ addr line:0x%.8X wr:0x%.8X rd:0x%.8X") % (j,0x0, page_data[j][0])
error = 1;
print "Test Data lines"
for i in range(num_data_lines) :
print "[%d]" % i
gennum.set_memory_page(1, (1<<i))
gennum.add_dma_item(0, pages[1], dma_length, 1, 0)
gennum.start_dma()
gennum.wait_irq()
time.sleep(0.01)
gennum.add_dma_item(0, pages[2], dma_length, 0, 0)
gennum.start_dma()
gennum.wait_irq()
time.sleep(0.01)
page_data = gennum.get_memory_page(2);
if (page_data[0] != (1 << i)) :
print("### Compare error @ data line:0x%.8X wr:0x%.8X rd:0x%.8X") % (i,(1 << i), page_data[0])
error = 1;
if (error) :
print "RESULT: [FAILED]"
raise PtsError ("Error in DDR data/address lines. Please check log file for more information")
else :
print "RESULT: [OK]"
t2 = time.time();
print 'End of test'
print 'Time DDR test: ' + str(t2-t1) + ' seconds'
if __name__ == '__main__' :
main();
class test07:
GN4124_CSR = 0x0
dma_length = 0x4 # DMA block length in bytes
# parameters of the memory interface
num_addr_lines = 14
num_bank_lines = 3
num_data_lines = 16
def __init__(self, spec):
""" Initialize (get a list of pages for DMA access, configure interrupts) """
try:
self.gennum = gn4124.CGN4124(spec, self.GN4124_CSR) # Initialize the board
self.gennum.set_local_bus_freq(160) # Set local bus frequency
self.pages = self.gennum.get_physical_addr() # Get host memory pages physical address
except:
exctype, value = sys.exc_info()[:2]
err_msg="While board initialization: "+str(exctype)+" : "+str(value)
raise PtsError(err_msg) # Non-critical error: further tests could be performed successfully
if len(self.pages) < 1:
raise PtsError("While board initialization: Not enough host memory pages for DMA access")
def wishbone_address_bit_to_DDR_interface_line(self,wishbone_addr_bit_number):
first_bank_bit_in_wishbone_addr=11
first_row_bit_in_wishbone_addr=14
first_column_bit_in_wishbone_addr=1
if wishbone_addr_bit_number > 10 and wishbone_addr_bit_number < 14:
DDR_interface_line="bank line {}".format(wishbone_addr_bit_number-first_bank_bit_in_wishbone_addr)
elif wishbone_addr_bit_number >= first_row_bit_in_wishbone_addr:
DDR_interface_line="address line {}".format(wishbone_addr_bit_number-first_row_bit_in_wishbone_addr)
elif wishbone_addr_bit_number >= first_column_bit_in_wishbone_addr:
DDR_interface_line="address line {}".format(wishbone_addr_bit_number-first_column_bit_in_wishbone_addr)
else:
DDR_interface_line="line"
return DDR_interface_line
def test_address_and_bank_lines(self):
first_test_wishbone_addr_bit=11
memory_wishbone_addr_mask=0x0FFFFFFF
test_wishbone_addr_mask=memory_wishbone_addr_mask ^ ((0x1 << first_test_wishbone_addr_bit)-1)
""" Test the memory-interface address lines """
# Bank lines are tested first and then the address lines (rows)
ret_error=None
addr_list=[(0x1 << addr_line-1+first_test_wishbone_addr_bit) & test_wishbone_addr_mask for addr_line in range(self.num_addr_lines+self.num_bank_lines+1)] # DDR addresses: 0x00000000, 0x00000800, 0x00001000, 0x00002000...
value_list=[addr_line+1 for addr_line in range(self.num_addr_lines+self.num_bank_lines+1)] # values to write in DDR adresses: 1, 2, 3, 4...
for addr_line in reversed(range(len(addr_list))): # Write value_list in DDR addr_list in reverse order
self.gennum.set_memory_page(0, value_list[addr_line])
self.gennum.add_dma_item(addr_list[addr_line], self.pages[0], self.dma_length, 1, 0) # write host page[0] in addr_list[addr_line]
self.gennum.start_dma()
self.gennum.wait_irq()
for addr_line in reversed(range(len(addr_list))): # Compare values in DDR addr_list in reverse order
self.gennum.add_dma_item(addr_list[addr_line], self.pages[0], self.dma_length, 0, 0) # Store addr_list[addr_line] in host page[0]
self.gennum.start_dma()
self.gennum.wait_irq()
page_data = self.gennum.get_memory_page(0)
if page_data[0] <> value_list[addr_line]:
error_str="Value read from memory (0x{:X}) is differnt from what was expected (0x{:X}) at Wishbone address (0x{:X}). At least DDR-interface {} is tied to Vcc or GND, or unconnected.".format(page_data[0],value_list[addr_line],addr_list[addr_line],self.wishbone_address_bit_to_DDR_interface_line(0 if addr_line==0 else addr_line-1+first_test_wishbone_addr_bit))
print(error_str)
ret_error="While testing DDR address and bank lines: "+error_str
break
return ret_error
def test_data_lines(self):
""" Test the memory-interface data lines """
ret_error=None
test_data_addr=0x0 # any valid address is OK
value_list=[0x0001 << data_line for data_line in range(self.num_data_lines)] # DDR data values: 0x0001, 0x0002, 0x0004, 0x0008...
for data_line in range(len(value_list)): # Write value_list in DDR address 0
self.gennum.set_memory_page(0, value_list[data_line])
self.gennum.add_dma_item(test_data_addr, self.pages[0], self.dma_length, 1, 0) # write host page[0] in DDR test_data_addr
self.gennum.start_dma()
self.gennum.wait_irq()
self.gennum.add_dma_item(test_data_addr, self.pages[0], self.dma_length, 0, 0) # Store content of DDR test_data_addr in host page[0]
self.gennum.start_dma()
self.gennum.wait_irq()
page_data = self.gennum.get_memory_page(0)
if page_data[0] <> value_list[data_line]:
error_str="Value read from memory (0x{:X}) is differnt from what was expected (0x{:X}) at Wishbone address (0x{:X}). DDR-interface data line/s is tied to Vcc or GND, or unconnected.".format(page_data[0],value_list[data_line],test_data_addr)
print(error_str)
ret_error="While testing DDR data lines: "+error_str
break
return ret_error
def main(default_directory="."):
# Configure the FPGA using the program fpga_loader
path_fpga_loader = '../firmwares/fpga_loader'
path_firmware = '../firmwares/test07.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream)
os.system( firmware_loader + ' ' + bitstream )
# Load board library and open the corresponding device
print "Loading hardware access library and opening device\n"
spec = rr.Gennum()
print "Test07 Start"
init_test_time = time.time()
print "Configuring board"
test=test07(spec)
print "\nChecking DDR address and bank lines"
ret_error=test.test_address_and_bank_lines()
if ret_error==None:
print "Checking DDR data lines"
ret_error=test.test_data_lines()
end_test_time = time.time()
print "\nEnd of Test07"
print "RESULT: [{}]".format("FAIL" if ret_error else "OK")
print 'Test07 elapsed time: {:.2f} seconds'.format(end_test_time-init_test_time)
if ret_error:
raise PtsError(ret_error)
if __name__ == "__main__":
main(".")
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