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Production Test Suite
Commit c80e296a authored by Matthieu Cattin's avatar Matthieu Cattin
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Modify log format.

parent 9b163f35
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Showing with 8 additions and 6 deletions
test/fmcadc100m14b4cha/python/test06.py
View file @ c80e296a
......@@ -88,6 +88,8 @@ def main (default_directory='.'):
if('WAIT_TRIG' == fmc.get_acq_fsm_state()):
print('Acquisition FSM state : %s') % fmc.get_acq_fsm_state()
raise PtsError('External trigger input is not working')
else:
print('The external trigger input is working fine.')
if __name__ == '__main__' :
......
test/fmcadc100m14b4cha/python/test07.py
View file @ c80e296a
......@@ -63,7 +63,7 @@ def main (default_directory='.'):
# Read channels current data register
for i in range(1,NB_CHANNELS+1):
adc_value = fmc.get_current_adc_value(i)
print('ADC channel %d value:0x%.4X expected value:0x%.4X') % (i, adc_value, ADC_POS)
print('ADC channel %d value:%d expected value:%d') % (i, adc_value, ADC_POS)
if(ADC_POS != adc_value):
print('Channel %d offset circuit is malfunctioning')%(i)
error += 1
......@@ -77,7 +77,7 @@ def main (default_directory='.'):
# Read channels current data register
for i in range(1,NB_CHANNELS+1):
adc_value = fmc.get_current_adc_value(i)
print('ADC channel %d value:0x%.4X expected value:0x%.4X tolerance:0x%.4X') % (i, adc_value, ADC_MID, ADC_TOL)
print('ADC channel %d value:%d expected value:%d tolerance:%d') % (i, adc_value, ADC_MID, ADC_TOL)
if((ADC_MID-ADC_TOL > adc_value) | (ADC_MID+ADC_TOL < adc_value)):
print('Channel %d offset circuit is malfunctioning')%(i)
error += 1
......@@ -92,7 +92,7 @@ def main (default_directory='.'):
# Read channels current data register
for i in range(1,NB_CHANNELS+1):
adc_value = fmc.get_current_adc_value(i)
print('ADC channel %d value:0x%.4X expected value:0x%.4X') % (i, adc_value, ADC_NEG)
print('ADC channel %d value:%d expected value:%d') % (i, adc_value, ADC_NEG)
if(ADC_NEG != adc_value):
print('Channel %d offset circuit is malfunctioning')%(i)
error += 1
......
test/fmcadc100m14b4cha/python/test08.py
View file @ c80e296a
......@@ -82,7 +82,7 @@ def sw_test(gen, sine, awg_offset, fmc, sw, ssr_1, ssr_2, diff_tol, retry_nb=0,
time.sleep(SSR_SET_SLEEP)
adc_value = fmc.get_current_adc_value(i)
diff = adc_value_before-adc_value
print('CH%d ssr=0x%.2X: %d ssr=0x%.2X: %d diff:%d tolerance:%d') % (i, ssr_1, adc_value_before, ssr_2, adc_value, abs(diff), diff_tol)
print('CH%d ssr=0x%.2X: %d ssr=0x%.2X: %d diff:%d min_diff:%d') % (i, ssr_1, adc_value_before, ssr_2, adc_value, abs(diff), diff_tol)
if(diff_tol <= abs(diff)):
pass_nb += 1
fmc.set_ssr(i,0x0)
......@@ -234,8 +234,8 @@ def main (default_directory='.'):
error += sw_test(gen, sine, 0.25, fmc, 1, 0x00, 0x01, SW1_TOL, RETRY_NB, SW1_THRESHOLD)
error += sw_test(gen, sine, 0.25, fmc, 4, 0x01, 0x09, SW4_TOL, RETRY_NB, SW4_THRESHOLD)
error += sw_test(gen, sine, 0.25, fmc, 5, 0x41, 0x51, SW5_TOL, RETRY_NB, SW5_THRESHOLD)
error += sw_test(gen, sine, 0.25, fmc, 6, 0x00, 0x60, SW5_TOL, RETRY_NB, SW6_THRESHOLD)
error += sw_test(gen, sine, 0.25, fmc, 7, 0x01, 0x41, SW6_TOL, RETRY_NB, SW7_THRESHOLD)
error += sw_test(gen, sine, 0.25, fmc, 6, 0x00, 0x60, SW6_TOL, RETRY_NB, SW6_THRESHOLD)
error += sw_test(gen, sine, 0.25, fmc, 7, 0x01, 0x41, SW7_TOL, RETRY_NB, SW7_THRESHOLD)
error += sw_test(gen, sine, 0.01, fmc, 2, 0x20, 0x22, SW2_TOL, RETRY_NB, SW2_THRESHOLD)
error += sw_test(gen, sine, 0.01, fmc, 3, 0x22, 0x26, SW3_TOL, RETRY_NB, SW3_THRESHOLD)
......
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