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e35306e8
Commit
e35306e8
authored
Jul 12, 2013
by
Matthieu Cattin
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fmc_adc: Add ddr memory access for svec board.
parent
a779408d
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fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+34
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
e35306e8
...
...
@@ -77,6 +77,10 @@ class CFmcAdc100m:
UTC_CORE_ADDR
=
0x0
# FOR SVEC ONLY
DDR_DAT_ADDR
=
0x0100
DDR_ADR_ADDR
=
0x0200
FMC_SYS_I2C_ADDR
=
0x1000
EEPROM_ADDR
=
0x50
...
...
@@ -123,6 +127,10 @@ class CFmcAdc100m:
self
.
adc_mezz_offset
=
offset
self
.
adc_core_offset
=
offset
+
0x2000
# FOR SVEC ONLY
self
.
DDR_DAT_ADDR
=
self
.
adc_mezz_offset
+
DDR_DAT_ADDR
self
.
DDR_ADR_ADDR
=
self
.
adc_mezz_offset
+
DDR_ADR_ADDR
try
:
# Objects declaration
self
.
utc_core
=
CCSR
(
self
.
bus
,
self
.
adc_mezz_offset
+
self
.
UTC_CORE_ADDR
,
UTC_CORE_REGS
)
...
...
@@ -875,3 +883,29 @@ class CFmcAdc100m:
except
Si57xOperationError
as
e
:
raise
FmcAdc100mOperationError
(
e
)
#======================================================================
# DDR memory interface, FOR SVEC ONLY
# Read data from DDR
# carrier_addr and length are in 32-bit word
def
get_data
(
self
,
carrier_addr
,
length
):
ret
=
[]
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
carrier_addr
)
for
i
in
range
(
length
):
ret
.
append
(
self
.
bus
.
iread
(
0
,
self
.
DDR_DAT_ADDR
,
4
))
# Write data to DDR
# carrier_addr is in 32-bit word
# data must be a array of 32-bit words
def
get_data
(
self
,
carrier_addr
,
data
):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
carrier_addr
)
for
i
in
range
(
len
(
data
)):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_DAT_ADDR
,
4
,
data
[
i
]))
# Clear DDR
def
get_data
(
self
):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
0x0
)
for
i
in
range
(
0x4000000
):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_DAT_ADDR
,
4
,
0x0
))
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