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Production Test Suite
Commit e39e6802 authored by Samuel Iglesias Gonsalvez's avatar Samuel Iglesias Gonsalvez
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tps/tests: change to relative paths 

It is needed to change the header that indicates which version of python use.

Step by step... we walk the road.
parent 794cc3ae
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Showing with 1383 additions and 50 deletions
test/spec/python/test00.py
View file @ e39e6802
......@@ -128,11 +128,16 @@ class ADC_AD7997:
def adc_value(value) :
return str(2.495 * (0x3FF & (value >> 2)) / 1024); # 10 bits
def main ():
def main (default_directory='.'):
bitstream_name = 'test_voltage_fmc.bin'
os.system('/user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/fpga_loader_test /user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/'+bitstream_name);
time.sleep(1);
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/test00.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
gennum = rr.Gennum();
......@@ -183,5 +188,6 @@ def main ():
raise TpsWarning( "Error in P12V_BI, value " + value1 + " < 2.0")
print "P12V_BI = " + value1
if __name__ == '__main__' :
main();
test/spec/python/test01.py 0 → 100644
View file @ e39e6802
This diff is collapsed.
test/spec/python/test02.py
View file @ e39e6802
......@@ -285,33 +285,28 @@ class EEPROM_GENNUM:
else :
raise TpsUser('EEPROM= %.2X, FILE= %.2X => ERROR' %(eeprom_data[i],file_data[i]))
def main ():
bitstream_name = 'test_ddr.bin'
os.system('/user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/fpga_loader_test /user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/'+bitstream_name);
time.sleep(1);
gennum = rr.Gennum();
eeprom = EEPROM_GENNUM(gennum);
# eeprom.eeprom_dump_to_screen();
eeprom.eeprom_dump_to_file("/tmp/eeprom.dat"); #
def main (default_directory='.'):
# f_test = open("/tmp/eeprom_test.dat","w+");
# with open("/tmp/eeprom.dat") as f:
# for line in f:
# f_test.write(line);
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/test02.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
# f.close();
time.sleep(2);
# f_test.seek(-14, os.SEEK_END);
# f_test.write("FFFF FFFFFFFF");
# f_test.close();
gennum = rr.Gennum();
eeprom = EEPROM_GENNUM(gennum);
eeprom.eeprom_dump_to_file("/tmp/eeprom.dat");
eeprom.file_dump_to_eeprom("test/eeprom_test_A.dat");
eeprom.file_dump_to_eeprom(default_directory+"/eeprom_test_A.dat");
eeprom.eeprom_dump_to_screen();
eeprom.compare_eeprom_with_file("test/eeprom_test_A.dat");
eeprom.compare_eeprom_with_file(default_directory +"/eeprom_test_A.dat");
eeprom.file_dump_to_eeprom("/tmp/eeprom.dat");
eeprom.eeprom_dump_to_screen();
eeprom.compare_eeprom_with_file("/tmp/eeprom.dat");
if __name__ == '__main__' :
main();
test/spec/python/test03.py
View file @ e39e6802
......@@ -13,17 +13,18 @@ class CGennumFlash :
GENNUM_FPGA = 2;
FPGA_FLASH = 3;
def __init__ (self, bus):
def __init__ (self, bus, path):
self.bus = bus;
self.lib = cdll.LoadLibrary("libfpga_loader.so");
library = path + "libfpga_loader.so";
self.lib = cdll.LoadLibrary(library);
self.lib.rr_init();
self.lib.gpio_init();
def main():
def main (default_directory='.'):
gennum = rr.Gennum();
flash = CGennumFlash(gennum);
flash = CGennumFlash(gennum, default_directory);
start = time.time();
flash.lib.gpio_bootselect(flash.GENNUM_FLASH);
......@@ -33,7 +34,7 @@ def main():
# Load a new firmware to the Flash memory.
print "Starting the process to load a FW into Flash memory"
flash.lib.load_mcs_to_flash("./test_flash.bin");
flash.lib.load_mcs_to_flash(default_directory + "/test_flash.bin");
time.sleep(1);
print "Forcing to load FW from Flash memory to FPGA"
......@@ -59,10 +60,5 @@ def main():
if (ask == "N") :
raise TpsError("Error loading FW through the Flash memory");
if __name__ == '__main__' :
main();
test/spec/python/test05.py
View file @ e39e6802
......@@ -299,11 +299,16 @@ def rx_thread(minic, size):
def main():
def main (default_directory='.'):
bitstream_name = 'test_sata.bin'
os.system('/user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/fpga_loader_test /user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/'+bitstream_name);
time.sleep(1);
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/test05.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
gennum = rr.Gennum();
......@@ -448,3 +453,5 @@ def main():
p.terminate();
raise TpsError ("Test DP0 -> SATA1: Error in SATA 1, RX")
if __name__ == '__main__' :
main();
test/spec/python/test06.py
View file @ e39e6802
......@@ -149,10 +149,17 @@ class CSI570 :
val = (1 << 7);
self.wr_reg8(self.RST_MEM_CTRL, val);
def main ():
bitstream_name = 'test_si570.bin'
os.system('/user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/fpga_loader_test /user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/'+bitstream_name);
time.sleep(1);
def main (default_directory='.'):
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/test06.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
gennum = rr.Gennum();
......@@ -170,3 +177,6 @@ def main ():
else :
raise TpsError("SIS570 CLK present: FAILED")
if __name__ == '__main__' :
main();
test/spec/python/test07.py
View file @ e39e6802
......@@ -13,12 +13,17 @@ import os
GN4124_CSR = 0x0
def main():
def main (default_directory='.'):
bitstream_name = 'test_ddr.bin'
os.system('/user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/fpga_loader_test /user/siglesia/vhdl/gennum/fpga_loader/gnurabbit/user/'+bitstream_name);
time.sleep(1);
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/test07.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
......@@ -116,3 +121,7 @@ def main():
t2 = time.time();
print 'End of test'
print 'Time DDR test: ' + str(t2-t1) + ' seconds'
if __name__ == '__main__' :
main();
test/spec/python/test08.py
View file @ e39e6802
......@@ -320,7 +320,16 @@ class AD5662_1:
self.spi.transaction(0, data)
def main():
def main (default_directory='.'):
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/test08.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
global double_counter
......
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