Add a class to control utc core, irq controller and SPEC 1-wire + preliminary tests.

e8da9cc6 · Matthieu Cattin · 0d94e608 · e8da9cc6 · e8da9cc6
Commit e8da9cc6 authored Nov 22, 2011 by Matthieu Cattin
Hide whitespace changes
Inline Side-by-side

Showing with 286 additions and 0 deletions

spec_fmc_adc.py test/fmcadc100m14b4cha/python/spec_fmc_adc.py +182 -0

test13.py test/fmcadc100m14b4cha/python/test13.py +104 -0

No files found.
--- a/test/fmcadc100m14b4cha/python/spec_fmc_adc.py
+++ b/test/fmcadc100m14b4cha/python/spec_fmc_adc.py
+#!   /usr/bin/env	python
+#    coding: utf8
+
+import sys
+import rr
+import random
+import time
+import csr
+import onewire
+import ds18b20
+
+
+class CSpecFmcAdc100Ms:
+
+    SPEC_ONEWIRE_ADDR = 0x20000
+    SPEC_CSR_ADDR = 0x30000
+    UTC_CORE_ADDR = 0x40000
+    IRQ_CONTROLLER_ADDR = 0x50000
+
+    # SPEC CSR
+    CSR_TYPE_VER = 0x00
+    CSR_BSTM_TYPE = 0x04
+    CSR_BSTM_DATE = 0x08
+    CSR_STATUS = 0x0C
+    CSR_CTRL = 0x10
+
+    PCB_VER_MASK = 0x000F
+    CARRIER_TYPE_MASK = 0xFFFF0000
+
+    STATUS_FMC_PRES = (1<<0)
+    STATUS_P2L_PLL_LCK = (1<<1)
+    STATUS_SYS_PLL_LCK = (1<<2)
+    STATUS_DDR3_CAL_DONE = (1<<3)
+
+    CTRL_LED_GREEN = (1<<0)
+    CTRL_LED_RED = (1<<1)
+    CTRL_DAC_CLR_N = (1<<2)
+
+    # UTC core
+    UTC_CORE_SECONDS = 0x0
+    UTC_CORE_COARSE = 0x4
+
+    # tag = [wb_addr_offset, meta, second, coarse, fine]
+    tag_trig = [0x8, 0, 0, 0, 0]
+    tag_start = [0x18, 0, 0, 0, 0]
+    tag_stop = [0x28, 0, 0, 0, 0]
+
+    # IRQ controller
+    IRQ_CTRL_MULT = 0x0
+    IRQ_CTRL_SRC = 0x4
+    IRQ_CTRL_EN_MASK = 0x8
+
+
+    def __init__(self, bus):
+        self.bus = bus
+        self.spec_onewire = onewire.COpenCoresOneWire(self.bus, self.SPEC_ONEWIRE_ADDR, 624, 124)
+        self.ds18b20 = ds18b20.CDS18B20(self.spec_onewire, 0)
+        self.spec_csr = csr.CCSR(self.bus, self.SPEC_CSR_ADDR)
+        self.utc_core = csr.CCSR(self.bus, self.UTC_CORE_ADDR)
+        self.irq_controller = csr.CCSR(self.bus, self.IRQ_CONTROLLER_ADDR)
+
+    def __del__(self):
+        pass
+
+    # print SPEC unique ID
+    def print_unique_id(self):
+        print('SPEC unique ID: %.12X') % self.ds18b20.read_serial_number()
+
+    # print SPEC temperature
+    def print_temp(self):
+        serial_number = self.ds18b20.read_serial_number()
+        print("SPEC temperature: %3.3f°C") % self.ds18b20.read_temp(serial_number)
+
+    # Returns SPEC unique ID
+    def get_unique_id(self):
+        return self.ds18b20.read_serial_number()
+
+    # Returns SPEC temperature
+    def get_temp(self):
+        serial_number = self.ds18b20.read_serial_number()
+        if(serial_number == -1):
+            return -1
+        else:
+            return self.ds18b20.read_temp(serial_number)
+
+    # Returns UTC seconds counter value
+    def get_utc_second_cnt(self):
+        return self.utc_core.rd_reg(self.UTC_CORE_SECONDS)
+
+    # Set UTC seconds counter
+    def set_utc_second_cnt(self, value):
+        self.utc_core.wr_reg(self.UTC_CORE_SECONDS, value)
+        return self.utc_core.rd_reg(self.UTC_CORE_SECONDS)
+
+    # Returns UTC coarse counter value
+    def get_utc_coarse_cnt(self):
+        return self.utc_core.rd_reg(self.UTC_CORE_COARSE)
+
+    # Set UTC coarse counter
+    def set_utc_coarse_cnt(self, value):
+        self.utc_core.wr_reg(self.UTC_CORE_COARSE, value)
+        return self.utc_core.rd_reg(self.UTC_CORE_COARSE)
+
+    # Returns last trigger event time-tag
+    def get_utc_trig_tag(self):
+        # Get metadata
+        addr = self.tag_trig[0]
+        self.tag_trig[1] = self.utc_core.rd_reg(addr)
+        # Get seconds
+        addr = self.tag_trig[0]+0x4
+        self.tag_trig[2] = self.utc_core.rd_reg(addr)
+        # Get coarse
+        addr = self.tag_trig[0]+0x8
+        self.tag_trig[3] = self.utc_core.rd_reg(addr)
+        # Get fine
+        addr = self.tag_trig[0]+0xc
+        self.tag_trig[4] = self.utc_core.rd_reg(addr)
+
+        return self.tag_trig
+
+    # Returns last acquisition start event time-tag
+    def get_utc_start_tag(self):
+        # Get metadata
+        addr = self.tag_start[0]
+        self.tag_start[1] = self.utc_core.rd_reg(addr)
+        # Get seconds
+        addr = self.tag_start[0]+0x4
+        self.tag_start[2] = self.utc_core.rd_reg(addr)
+        # Get coarse
+        addr = self.tag_start[0]+0x8
+        self.tag_start[3] = self.utc_core.rd_reg(addr)
+        # Get fine
+        addr = self.tag_start[0]+0xc
+        self.tag_start[4] = self.utc_core.rd_reg(addr)
+
+        return self.tag_start
+
+    # Returns last acquisition stop event time-tag
+    def get_utc_stop_tag(self):
+        # Get metadata
+        addr = self.tag_stop[0]
+        self.tag_stop[1] = self.utc_core.rd_reg(addr)
+        # Get seconds
+        addr = self.tag_stop[0]+0x4
+        self.tag_stop[2] = self.utc_core.rd_reg(addr)
+        # Get coarse
+        addr = self.tag_stop[0]+0x8
+        self.tag_stop[3] = self.utc_core.rd_reg(addr)
+        # Get fine
+        addr = self.tag_stop[0]+0xc
+        self.tag_stop[4] = self.utc_core.rd_reg(addr)
+
+        return self.tag_stop
+
+    # Set IRQ enable mask
+    def set_irq_en_mask(self, mask):
+        self.irq_controller.wr_reg(self.IRQ_CTRL_EN_MASK, mask)
+        return self.irq_controller.rd_reg(self.IRQ_CTRL_EN_MASK)
+
+    # Get IRQ enable mask
+    def get_irq_en_mask(self):
+        return self.irq_controller.rd_reg(self.IRQ_CTRL_EN_MASK)
+
+    # Returns multiple IRQ status
+    def get_irq_mult(self):
+        return self.irq_controller.rd_reg(self.IRQ_CTRL_MULT)
+
+    # Clears multiple IRQ status
+    def clear_irq_mult(self, irq):
+        self.irq_controller.wr_reg(self.IRQ_CTRL_MULT, irq)
+        return self.irq_controller.rd_reg(self.IRQ_CTRL_MULT)
+
+    # Returns IRQ source
+    def get_irq_source(self):
+        return self.irq_controller.rd_reg(self.IRQ_CTRL_SRC)
+
+    # Clears IRQ source
+    def clear_irq_source(self, irq):
+        self.irq_controller.wr_reg(self.IRQ_CTRL_SRC, irq)
+        return self.irq_controller.rd_reg(self.IRQ_CTRL_SRC)
+
+
--- a/test/fmcadc100m14b4cha/python/test13.py
+++ b/test/fmcadc100m14b4cha/python/test13.py
+#!   /usr/bin/env   python
+#    coding: utf8
+
+# Copyright CERN, 2011
+# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+
+import sys
+import rr
+import time
+import os
+
+from ptsexcept import *
+
+import gn4124
+import csr
+import fmc_adc
+import spec_fmc_adc
+
+
+"""
+test13: Test 1-wire thermometer and read the unique ID of the SPEC board.
+
+Note: Requires test00.py to run first to load the firmware!
+"""
+
+
+GN4124_CSR = 0x0
+
+FAMILY_CODE = 0x28
+
+def main (default_directory='.'):
+
+    load_firmware = raw_input('Do you want to load the firmware? [y,n]')
+    if(load_firmware == 'y'):
+        path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
+        path_firmware = '../firmwares/spec_fmcadc100m14b4cha_test.bin';
+
+        firmware_loader = os.path.join(default_directory, path_fpga_loader)
+        bitstream = os.path.join(default_directory, path_firmware)
+        print firmware_loader + ' ' + bitstream
+        os.system( firmware_loader + ' ' + bitstream )
+
+        time.sleep(2);
+
+    # Objects declaration
+    spec = rr.Gennum() # bind to the SPEC board
+    fmc = fmc_adc.CFmcAdc100Ms(spec)
+    spec_fmc = spec_fmc_adc.CSpecFmcAdc100Ms(spec)
+    gnum = gn4124.CGN4124(spec, GN4124_CSR)
+
+
+    print('\nSPEC 1-wire thremo/ID test')
+
+    # Read unique ID and print to log
+    unique_id = spec_fmc.get_unique_id()
+    if(unique_id == -1):
+        raise PtsError ("Can't read DS18D20 1-wire thermometer on SPEC board.")
+    else:
+        print('SPEC Unique ID: %.12X') % unique_id
+
+    # Read temperatur and print to log
+    temp = spec_fmc.get_temp()
+    print('SPEC temperature: %3.3f°C') % temp
+
+    if((unique_id & 0xFF) != FAMILY_CODE):
+        family_code = unique_id & 0xFF
+        print('family code: 0x%.8X') % family_code
+        raise PtsError ("SPEC's 1-wire thermometer has the wrong family code:0x.2X expected:0x%.2X" % family_code,FAMILY_CODE)
+
+
+    print('\nUTC core test')
+
+    current_time = time.time()
+    utc_seconds = int(current_time)
+    print('UTC seconds %d [s]')%utc_seconds
+    spec_fmc.set_utc_second_cnt(utc_seconds)
+    print('UTC core seconds counter: %d')%spec_fmc.get_utc_second_cnt()
+
+    utc_coarse = int((current_time - utc_seconds)/8E-9)
+    print('UTC coarse %d [8ns]')%utc_coarse
+    spec_fmc.set_utc_coarse_cnt(utc_coarse)
+    print('UTC core coarse counter: %d')%spec_fmc.get_utc_coarse_cnt()
+
+
+    print('\nIRQ controller test')
+
+    print('Wait IRQ')
+    gnum.wait_irq()
+    print('IRQ detected')
+
+    print('IRQ enable mask: %.4X')%spec_fmc.get_irq_en_mask()
+    print('IRQ controller status: %.4X')%spec_fmc.get_irq_ctrl_status()
+    # Enables 'DMA finished' and 'DMA error' interrupts
+    print('Set IRQ enable mask: %.4X')%spec_fmc.set_irq_en_mask(0x3)
+
+    print('Wait IRQ')
+    gnum.wait_irq()
+    print('IRQ detected')
+
+
+if __name__ == '__main__' :
+    main()