tps/test: removed VHDL code.

It will be added to the repository at the end of the development.

tps/test: removed VHDL code.
It will be added to the repository at the end of the development.
eb35fe66 · Samuel Iglesias Gonsalvez · 27ac02ff · 27ac02ff · 27ac02ff · 27ac02ff
Commit eb35fe66 authored Jul 15, 2011 by Samuel Iglesias Gonsalvez
Showing with 0 additions and 1219 deletions

README test/spec/hdl/test00/README +0 -18

spec_ddr_test_top.vhd test/spec/hdl/test00/spec_ddr_test_top.vhd +0 -622

spec_top.ucf test/spec/hdl/test00/spec_top.ucf +0 -579

No files found.
--- a/test/spec/hdl/test00/README
+++ b/test/spec/hdl/test00/README
-------------------------------------------------------------------------------
--------------------------------    TEST 1    ---------------------------------
-------------------------------------------------------------------------------
-
-1.- WHAT IS INCLUDED
-
-  A.- A top VHDL in which 3 wishbone slaves can be addressed. Only the first
-      two are used. This two wishbone slaves correspond to the I2C master that
-      connect to i2c devices in fmc-carrier-tester: I2C_A, I2C_B.
-      Its wishbone mappings are
-        - I2C_A: 0x40000
-        - I2C_B: 0x80000
-  B.- "test00.bin" which is the bitstream for programming spec FPGA with the
-      aforementioned configuration.
-  C.- "test00.py" that it's a python test which is an aggregate of the rest
-      of python code.
-
-This test checks the voltage values of the power supply pins on the FMC.
--- a/test/spec/hdl/test00/spec_ddr_test_top.vhd
+++ b/test/spec/hdl/test00/spec_ddr_test_top.vhd
--- a/test/spec/hdl/test00/spec_top.ucf
+++ b/test/spec/hdl/test00/spec_top.ucf