Add EEPROM write/readback in test02, increase tolerance in test07, add recovery mechanism in test09.

Added the generation of the libfpga_loader shared library. And
comment the output messages of the fpga_loader.

This fpga_loader is only valid for SPEC V2.0 or higher.

The timeout was setup to 1 second (HZ constant in jiffies) to fix a problem
in the test/spec/python/test07.py.

This test file was always waiting for the IRQ from the first DMA.

The DMA transfer was properly finished but the IRQ doesn't arrive. It seems
that the problem behind is a wrong initialization (reset?) of the corresponding
DMA core in the Firmware.

This is a workaround of the problem.