added internal reset that would be activated for few cycles after the reprogramming of the fpga

added internal reset that would be activated for few cycles after the reprogramming of the fpga

svec_dac_vcxo_pll updated to use latest vme core; added internal reset that would be activated for few cycles after the reprogramming of the fpga

svec_pts_dac_vcxo_pll: updated to the latest version of VMEcore (ProgramID: 5a); added initialization reset logic

svec_pts_dac_vcxo_pll: updated to the latest version of VMEcore (ProgramID: 5a); added initialization reset logic

The fmc reference clock for gtp firmware implements a gtp wrapper (only to get the reference clocks).
Each clock increments a counter which is latch every second to a register accessible via VME.

svec pts: added gtp_clkpll vhdl files; added gtp_clkfmc vhdl and firmware; doc updated (still not final version); svec_pts_sfp_sata_hsfmc.bit renamed to svec_pts_gtp_clkpll.bin

the procedure carried out by test00 of the fmcdio5chttla now is divided into test00, test01, test02 and test03 (three new tests created)

This function is used by the fmc_delay C library.

Add a first set of common modules from fmcadc100m14b4cha.

Fix C shared library path in rr.py
Remove undefined rr_read and rr_write from rrlib.h
Remove rr.py and rrlib.so from pts root directory.
Put updated versions of rr.py, rrlib.so and rr_loader_lib.so in
test/fmcadc100m14b4cha/python those should be removed when all
tests will use common modules.

Library features are:
- Gennum GPIO configuration
- SPEC boot mode selection (Gennum to FPAG, Genum to Flash or Flash to FPGA)
- Bit bang SPI programming/erase/readback of the Flash
- Force FPGA reload from flash
- FPGA firmware loading using Gennum FCL (= FPGA Configuration Loader)

Function to load FPGA firmware from Gennum added to Python wrapper rr.py

Modify test04 to verify that Si570 output frequency is within the limits. Instead of just checking Si570 registers value, that might be different from chip to chip.