- 25 Oct, 2011 8 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 21 Oct, 2011 3 commits
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Samuel Iglesias Gonsalvez authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 18 Oct, 2011 5 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 13 Oct, 2011 4 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
Add EEPROM write/readback in test02, increase tolerance in test07, add recovery mechanism in test09.
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- 12 Oct, 2011 1 commit
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Samuel Iglesias Gonsalvez authored
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- 11 Oct, 2011 1 commit
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Matthieu Cattin authored
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- 10 Oct, 2011 1 commit
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Matthieu Cattin authored
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- 05 Oct, 2011 1 commit
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Matthieu Cattin authored
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- 06 Sep, 2011 2 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 07 Sep, 2011 1 commit
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Matthieu Cattin authored
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- 06 Sep, 2011 1 commit
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Matthieu Cattin authored
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- 31 Aug, 2011 1 commit
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Matthieu Cattin authored
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- 30 Aug, 2011 3 commits
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Samuel Iglesias Gonsalvez authored
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Samuel Iglesias Gonsalvez authored
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Samuel Iglesias Gonsalvez authored
Added the generation of the libfpga_loader shared library. And comment the output messages of the fpga_loader. This fpga_loader is only valid for SPEC V2.0 or higher.
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- 26 Aug, 2011 1 commit
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Samuel Iglesias Gonsalvez authored
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- 24 Aug, 2011 1 commit
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Samuel Iglesias Gonsalvez authored
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- 22 Aug, 2011 1 commit
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Samuel Iglesias Gonsalvez authored
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- 19 Aug, 2011 1 commit
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Samuel Iglesias Gonsalvez authored
The timeout was setup to 1 second (HZ constant in jiffies) to fix a problem in the test/spec/python/test07.py. This test file was always waiting for the IRQ from the first DMA. The DMA transfer was properly finished but the IRQ doesn't arrive. It seems that the problem behind is a wrong initialization (reset?) of the corresponding DMA core in the Firmware. This is a workaround of the problem.
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- 18 Aug, 2011 3 commits
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Samuel Iglesias Gonsalvez authored
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Samuel Iglesias Gonsalvez authored
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Samuel Iglesias Gonsalvez authored
The problem was a wrong setup of the polarity in the crossing point chip (ADN4600) mounted in the FMC carrier tester.
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- 17 Aug, 2011 1 commit
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Samuel Iglesias Gonsalvez authored
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