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Samuel Iglesias Gonsalvez authored
The timeout was setup to 1 second (HZ constant in jiffies) to fix a problem in the test/spec/python/test07.py. This test file was always waiting for the IRQ from the first DMA. The DMA transfer was properly finished but the IRQ doesn't arrive. It seems that the problem behind is a wrong initialization (reset?) of the corresponding DMA core in the Firmware. This is a workaround of the problem.
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