Proyect Description
This core is a QDRII controller with two pipelined Wishbone slave
ports.
It is based on the Virtex-6 hardware core and a management core for
QDRII+ generated by Xilinx
CoreGen.
Overview
QDRII controller developing steps:
- Writing VHDL code and functional test for QDRII memory controller
(based on QDRII+ MIG from Xilinx) Completed
- Generation of QDRII+ memory interface from Xilinx Core Generator (ISE 13.1). QDRII+ is supported by MIG (Memory interface Generator) but not QDRII. (doc: “UG406.Virtex-6 FPGA Memory Interface Solutions”)
- Functional test simulated and internal understanding of the generated VHDL in part 1.1.
- Differences between QDRII devices and QDRII+ devices made us
modify the provided code. (doc: “xapp886.Interfacing QDRII_SRAM
Devices with V6 FPGAs”)
- Modification of parameter values to adapt it to QDRII specifications.
- Modification of memory words burst. Following this QDRII
specifications and datasheet: the QDRII is two-words burst
whereas the given design is a four-words burst design. That
involved:
- Modify the W/R state machine to operate properly for two-words burst.
- Modify the testbench to verify correct operation for two-words burst.
- Modify the generic testbench and verify the functional test for our QDRII memory CY7C1314CV18. For that purpose the verilog model provided by Cypress was downloaded and used. Test completed and passed successfully
- Once the SCBv3 was released, we tested and implemented in hardware
the QDRII controller done in step 1. (red) Completed
- An ISE project was created in order to implement the memory controller inside de FPGA. In this design, we had to take into account temporal constrains and FPGA pins (following SCBv3 schematics). At first, the project did not work properly (no writing neither reading was properly done), we also noticed that the behaviour was different from simulation. Since it was quite difficult to find the problem with this amount of possibilities and variables, we decided to step back and start testing the hardware first (2.2 and 2.3 steps).
- To avoid hardware related problems (pin errors, short-circuits, clock problems,…), it was created another simple ISE project where the main QDRII tracks were tested with the Oscilloscope.
- Following the 2.2 step and the QDRII datasheet (CY7C1314CV18), we created a basic project where the reading and writing processes were done and successfully achieved. We checked the result with ChipScope (Xilinx tool that inserts logic analyzer, system analyzer, and virtual I/O low-profile software cores directly into the design, allowing us to view any internal signal or node “in real time”). Although this project proves the correct operation of the memory, it can not be used as a real controller since it is not efficient and the frequency used is too slow. If we try to increase frequency in order to use it more efficiently, we will start having problems with temporal constrains within internal FPGA track, PCB tracks and clock delays. This is out of the scope of this small and functional design.
- Once the PCB and hardware had been checked, we continued testing the project from step 2.1(QDRII controller based on MIG) in order to make it worked properly. For that reason we introduced the ChipScope analyzer inside this project, testing and checking all main signals in the design. Further tests provided that the problem was located in the calibration process, the delay in some tracks were out of the range, so the design could never start without these proper delays. Once it was fixed, we tested all memory addresses and data bits successfully. Bandwidth: 2 channel of 72 data bits for writing and reading simultaneously over a frequency of 100MHz or, in order words, it is possible to write and read 72 bits from/to the memory in the same 200MHz cycle.
- Implementation and test of the second QDRII memory controller from SCB board. Modification of FPGA pins and minor changes inside the controller. Test completed and passed successfully
- Development of a bridge interface between the QDRII memory controller and wishbone bus. ****
Documents
attachment:CY7C1314CV18.pdf CY7C1314CV18 – QDRII memory datasheet
attachment:ug406.pdf ug406 – Virtex-6 FPGA Memory Interface Solutions
attachment:xapp886.pdf xapp886 – Interfacing QDRII SRAM Devices with
Virtex-6 FPGAs
Check Xilinx website for latest version:
http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_meminterfacecontrol_mig.htm
Date | Event |
---|---|
23-11-2011 | First prototype in simulation (QDRII memory controller docs and code) |