clarify why these traces are needed

7d53bdf7 · Fernando Hueso González · ac782c94 · 7d53bdf7
Commit 7d53bdf7 authored Jun 05, 2021 by Fernando Hueso González
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BoardIO.kicad_sch BoardIO/BoardIO.kicad_sch +2 -2

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--- a/BoardIO/BoardIO.kicad_sch
+++ b/BoardIO/BoardIO.kicad_sch
@@ -1459,11 +1459,11 @@
    (effects (font (size 2.54 2.54)) (justify left bottom))
    (uuid d1284965-35c9-4932-a78d-c1d11f5daa11)
  )
-  (text "NOTES" (at 300.99 171.45 0)
+  (text "NOTES" (at 300.99 169.545 0)
    (effects (font (size 2.54 2.54)) (justify left bottom))
    (uuid eddfabf4-0a83-413f-a823-bd3725017d9f)
  )
-  (text "Layer buildup is ML4-1mm. PCB thickness: 1mm\nGND - LVDS isolation height: 0.232 mm\nAll LVDS are length and skew-matched to 100mm, but not the TTL.\nTrace edge-coupled surface microstrip width: 0.25 mm, gap: 0.20 mm, height: 0.035mm \nhttps://eu.beta-layout.com/pcb/technology/specifications/\nhttps://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html"
+  (text "Layer buildup is ML4-1mm. PCB thickness: 1mm\nGND - LVDS isolation height: 0.232 mm\nAll LVDS are length and skew-matched to 100mm, but not the TTL.\nTrace edge-coupled surface microstrip width: 0.25 mm, gap: 0.20 mm, height: 0.035mm \nhttps://eu.beta-layout.com/pcb/technology/specifications/\nhttps://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html\nThis is needed so that the e.g. 100 MHz clock is not lost when routing"
    (at 300.99 185.42 0)
    (effects (font (size 1.27 1.27)) (justify left bottom))
    (uuid 6272d202-300c-45be-92a6-dffe8dd56caf)