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(text "NOTES" (at 300.99 185.42 0)
(text "NOTES" (at 300.99 171.45 0)
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(text "Layer buildup is ML4-1mm. PCB thickness: 1mm\nGND - LVDS isolation height: 0.232 mm\nAll LVDS are length and skew-matched to 100mm, but not the TTL.\nTrace edge-coupled surface microstrip width: 0.25 mm, gap: 0.20 mm, height: 0.035mm \nhttps://eu.beta-layout.com/pcb/technology/specifications/\nhttps://www.multi-circuit-boards.eu/en/pcb-design-aid/impedance-calculation.html"
(at 300.99 199.39 0)
(at 300.99 185.42 0)
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(text "The board is supplied by PCI 6-pin PEG ATX power (J10) on the back end.\nThe J11 on the back end connects via flat cable to J70 of SIS1160.\nThe front end has 6 digital channels.\nJ1-J3 are LVDS outputs directly from the J70 of SIS1160.\nJ4-J6 are inputs into the J70. J4 is LVDS and non-isolated.\nJ5, J6 are non-isolated and LVTTL.\nAdapt SW70 on SIS1160 pull-up depending on wanted termination."
(at 300.99 220.98 0)
(text "The board is supplied by PCI 6-pin PEG ATX power (J10) on the back end.\nThe J11 on the back end connects via flat cable to J70 of SIS1160.\nThe front end has 6 digital channels J1-J6 (non-isolated).\nJ1-J4 are LVDS from/into the J70 of SIS1160 (input/output configurable).\nJ5-J6 are LVTTL from/into the J70 of SIS1160 (input/output configurable).\nAdapt SW70 on SIS1160 pull-up depending on wanted termination."
(at 300.99 205.105 0)
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(text "The direction of every pair/signal at J70 can be controlled individually.\nJ1 <=> J70-[1,2]: [CLK_P, CLK_N] LVDS Synchronous clock source distribution\nJ2 <=> J70-[3,4]: [TRIG_P, TRIG_N] LVDS (Suggestion) Global trigger distribution, firmware defined\nJ3 <=> J70-[5,6]: [TIMES_P, TIMES_N] LVDS (Suggestion) Global timestamp distribution, firmware defined\nJ4 <=> J70-[7,8]: [USER1_P, USER1_N] LVDS General purpose\nJ5 <=> J70-[9]: [USER2_L] LVTTL General purpose, single ended, open drain\nJ6 <=> J70-[10]: [USER3_L] LVTTL General purpose, single ended, open drain"
(at 301.625 220.98 0)
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(text "SW70-1: When ON, enable 100Ω Termination for CLK_P/CLK_N\nSW70-2: When ON, enable 100Ω Termination for TRIG_P/TRIG_N\nSW70-3: When ON, enable 100Ω Termination for TIMES_P/TIMES_N\nSW70-4: When ON, enable 100Ω Termination for USER1_P/USER1_N\nSW70-5: When ON, enable 4.7kΩ Pullup to 3.3V on USER2_L\nSW70-6: When ON, enable 4.7kΩ Pullup to 3.3V on USER3_L"
(at 301.625 235.585 0)
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(text "Potential upgrade:\n- Blinking LEDs on front panel\n- Change to Gompf bracket 9456-0000C ?\n- Optical Isolation of J5 and J6\n- Add SVG logos"
(at 301.625 247.65 0)
(text "Potential upgrade:\n- Blinking LEDs on front panel\n- Change to Gompf bracket 9456-0000C ?\n- Galvanic Isolation of J5 and J6\n- Add SVG logos\n- LVTTL to LVDS converter for CLK to CLK_P, CLK_N"
(at 301.625 250.19 0)
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