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Getting Started with the SPEC
Commit 72370a73 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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update missing pins in the gn4124-core component instances

parent 24725f47
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Showing with 23 additions and 2 deletions
hdl/top/spec/demo_user+dio/spec_top.vhd
View file @ 72370a73
......@@ -215,6 +215,9 @@ architecture rtl of spec_top is
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic; -- not used internally
csr_int_i : in std_logic; -- not used internally
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
......@@ -227,7 +230,11 @@ architecture rtl of spec_top is
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_ack_i : in std_logic := '0';
dma_stall_i : in std_logic := '0'
dma_stall_i : in std_logic := '0';
dma_err_i : in std_logic := '0'; -- not used internally
dma_rty_i : in std_logic := '0'; -- not used internally
dma_int_i : in std_logic := '0' -- not used internally
);
end component; -- gn4124_core
......@@ -456,6 +463,9 @@ begin
csr_dat_i => genum_wb_in.dat,
csr_ack_i => genum_wb_in.ack,
csr_stall_i => genum_wb_in.stall,
csr_err_i => '0',
csr_rty_i => '0', -- not used internally
csr_int_i => '0', -- not used internally
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
......
hdl/top/spec/demo_user/spec_top.vhd
View file @ 72370a73
......@@ -192,6 +192,10 @@ architecture rtl of spec_top is
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic; -- not used internally
csr_int_i : in std_logic; -- not used internally
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
......@@ -204,7 +208,11 @@ architecture rtl of spec_top is
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_ack_i : in std_logic := '0';
dma_stall_i : in std_logic := '0'
dma_stall_i : in std_logic := '0';
dma_err_i : in std_logic := '0'; -- not used internally
dma_rty_i : in std_logic := '0'; -- not used internally
dma_int_i : in std_logic := '0' -- not used internally
);
end component; -- gn4124_core
......@@ -392,6 +400,9 @@ begin
csr_dat_i => genum_wb_in.dat,
csr_ack_i => genum_wb_in.ack,
csr_stall_i => genum_wb_in.stall,
csr_err_i => '0',
csr_rty_i => '0', -- not used internally
csr_int_i => '0', -- not used internally
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
......
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