wbgen-regs/vic-regs.wb and .h: from general-cores

The .wb file comes from general-cores/modules/wishbone/wb_vic, commit 6041224. I built the header with wbgen2 by running "make vic-regs.h" in this same directory. Signed-off-by: Alessandro Rubini <rubini@gnudd.com>

wbgen-regs/vic-regs.wb and .h: from general-cores
The .wb file comes from general-cores/modules/wishbone/wb_vic, commit 6041224. I built the header with wbgen2 by running "make vic-regs.h" in this same directory. Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
64b1e044 · Alessandro Rubini · adc4d72a · 64b1e044 · 64b1e044
Commit 64b1e044 authored Sep 07, 2012 by Alessandro Rubini
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vic-regs.h kernel/wbgen-regs/vic-regs.h +86 -0

vic-regs.wb kernel/wbgen-regs/vic-regs.wb +132 -0

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--- a/kernel/wbgen-regs/vic-regs.h
+++ b/kernel/wbgen-regs/vic-regs.h
+/*
+  Register definitions for slave core: Vectored Interrupt Controller (VIC)
+
+  * File           : vic-regs.h
+  * Author         : auto-generated by wbgen2 from vic-regs.wb
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE vic-regs.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_VIC
+#define __WBGEN2_REGDEFS_VIC
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: VIC Control Register */
+
+/* definitions for field: VIC Enable in reg: VIC Control Register */
+#define VIC_CTL_ENABLE                        WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: VIC output polarity in reg: VIC Control Register */
+#define VIC_CTL_POL                           WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for register: Raw Interrupt Status Register */
+
+/* definitions for register: Interrupt Enable Register */
+
+/* definitions for register: Interrupt Disable Register */
+
+/* definitions for register: Interrupt Mask Register */
+
+/* definitions for register: Vector Address Register */
+
+/* definitions for register: Software Interrupt Register */
+
+/* definitions for register: End Of Interrupt Acknowledge Register */
+/* definitions for RAM: Interrupt Vector Table */
+#define VIC_IVT_RAM_BYTES 0x00000080 /* size in bytes */                               
+#define VIC_IVT_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */        
+
+PACKED struct VIC_WB {
+  /* [0x0]: REG VIC Control Register */
+  uint32_t CTL;
+  /* [0x4]: REG Raw Interrupt Status Register */
+  uint32_t RISR;
+  /* [0x8]: REG Interrupt Enable Register */
+  uint32_t IER;
+  /* [0xc]: REG Interrupt Disable Register */
+  uint32_t IDR;
+  /* [0x10]: REG Interrupt Mask Register */
+  uint32_t IMR;
+  /* [0x14]: REG Vector Address Register */
+  uint32_t VAR;
+  /* [0x18]: REG Software Interrupt Register */
+  uint32_t SWIR;
+  /* [0x1c]: REG End Of Interrupt Acknowledge Register */
+  uint32_t EOIR;
+  /* padding to: 32 words */
+  uint32_t __padding_0[24];
+  /* [0x80 - 0xff]: RAM Interrupt Vector Table, 32 32-bit words, 32-bit aligned, word-addressable */
+  uint32_t IVT_RAM [32];
+};
+
+#endif
--- a/kernel/wbgen-regs/vic-regs.wb
+++ b/kernel/wbgen-regs/vic-regs.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+	 name = "Vectored Interrupt Controller (VIC)";
+	 description = "Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.";
+	 prefix = "VIC";
+	 hdl_entity = "wb_slave_vic";
+
+	 reg {
+			name = "VIC Control Register";
+			prefix = "CTL";
+
+			field {
+				 name = "VIC Enable";
+				 description = "1: enables VIC operation\n0: disables VIC operation";
+				 prefix = "ENABLE";
+				 type = BIT;
+				 access_dev = READ_ONLY;
+				 access_bus = READ_WRITE;
+			};
+
+			field {
+				 name = "VIC output polarity";
+				 description = "1: IRQ output is active high\n0: IRQ output is active low";
+				 prefix = "POL";
+				 type = BIT;
+				 access_dev = READ_ONLY;
+				 access_bus = READ_WRITE;
+			};
+	 };
+
+	 reg {
+			name = "Raw Interrupt Status Register";
+			prefix = "RISR";
+			
+			field {
+				 name = "Raw interrupt status";
+				 description = "Each bit reflects the current state of corresponding IRQ input line.\nread 1: interrupt line is currently active\nread 0: interrupt line is inactive";
+				 type = SLV;
+				 size = 32;
+				 access_dev = WRITE_ONLY;
+				 access_bus = READ_ONLY;
+			};
+	 };
+
+	 reg {
+			name = "Interrupt Enable Register";
+			prefix = "IER";
+			
+			field {
+				 name = "Enable IRQ";
+				 description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
+				 type = PASS_THROUGH;
+				 size = 32;
+			};
+	 };
+
+	 reg {
+			name = "Interrupt Disable Register";
+			prefix = "IDR";
+			
+			field {
+				 name = "Disable IRQ";
+				 description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
+				 type = PASS_THROUGH;
+				 size = 32;
+			};
+	 };
+
+	 reg {
+			name = "Interrupt Mask Register";
+			prefix = "IMR";
+			
+			field {
+				 name = "IRQ disabled/enabled";
+				 description = "Read 1: interrupt associated with bitfield is enabled\nRead 0: interrupt is disabled";
+				 type = SLV;
+				 size = 32;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+	 };
+
+	 reg {
+			name = "Vector Address Register";
+			prefix = "VAR";
+			
+			field {
+				 name = "Vector Address";
+				 description = "Address of pending interrupt vector, read from Interrupt Vector Table";
+				 type = SLV;
+				 size = 32;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+	 };
+
+	 reg {
+			name = "Software Interrupt Register";
+			description = "Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.";
+			prefix = "SWIR";
+			field {
+				 name = "SWI interrupt mask";
+				 type = PASS_THROUGH;
+				 size = 32;
+			};
+	 };
+
+	 reg {
+			name = "End Of Interrupt Acknowledge Register";
+			prefix = "EOIR";
+			
+			field {
+				 name = "End of Interrupt";
+				 description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s).";
+				 type = PASS_THROUGH;
+				 size = 32;
+			};
+	 };
+
+	 ram {
+			name = "Interrupt Vector Table";
+			description = "Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register.";
+			prefix = "IVT_RAM";
+			
+			size = 32;
+			width = 32;
+			
+			access_bus = READ_WRITE;
+			access_dev = READ_ONLY;
+	 };
+};
\ No newline at end of file