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S
Simple PCIe FMC carrier SPEC
Commit 6729e610 authored by Vasco Guita's avatar Vasco Guita
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test

parent b52a7929
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.gitlab-ci.yml
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......@@ -3,7 +3,7 @@
# SPDX-FileCopyrightText: 2020 CERN
include:
- project: 'be-cem-edl/evergreen/gitlab-ci'
- project: 'vantonio/gitlab-ci'
ref: master
file:
- 'edl-gitlab-ci.yml'
......@@ -12,28 +12,11 @@ variables:
EDL_CI_DOC_SRC_PATH: 'doc'
EDL_CI_DOC_DST_PATH: '$EDL_CI_EOS_OUTPUT_DIR/doc'
cppcheck:
stage: analyse
image:
name: gitlab-registry.cern.ch/coht/common-containers/static-analysis:latest
script:
- make -C software cppcheck
synthesis:
extends: .synthesis-ise-14-7
parallel:
matrix:
- EDL_CI_SYN_SRC_PATH:
- hdl/syn/golden-45T
- hdl/syn/golden-150T
.script_build_kernel_dep: &script_build_kernel_dep
- export FPGA_MGR="/opt/fpga-mgr"
- git clone --depth 1 https://gitlab.cern.ch/fvaga/fpga-manager.git "$FPGA_MGR"
- make -C "$FPGA_MGR" all
kernel_build_cc7:
extends: .kernel_build_cc7
variables:
EDL_CI_KBUILD_PATHS: software/kernel
before_script:
- *script_build_kernel_dep
kernel_build_validation:
extends: .kernel_build_validation
before_script:
- |
echo "Checking Dependencies"
if [ "$FMC_BUILDS" != "0" ]; then echo 'FMC did not build successfully. Exiting'; exit 1; fi
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