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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
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V4 - Package type D1,D2 wrongly mentioned in BOM. Partnumber OK.
#4
· opened
Nov 08, 2017
by
Erik van der Bij
feature
1
updated
Nov 09, 2022
V4 - PCB Hard Gold plating card edge connector not specified
#3
· opened
Nov 17, 2017
by
Erik van der Bij
bug
0
updated
Nov 15, 2022
V4 - SW1 Black jumper not needed
#6
· opened
Nov 06, 2017
by
Erik van der Bij
bug
0
updated
Nov 16, 2022
V4 - front-panel drawing does not show licenced under CERN OHL.
#11
· opened
May 29, 2017
by
Erik van der Bij
feature
0
updated
Jan 19, 2023
V4 - Pull-down resistor on PCIe PERST_N line
#17
· opened
Mar 16, 2015
by
Projects
bug
2
updated
Apr 11, 2023
V4 - consider adding a header with power and user-defined FPGA pins.
#18
· opened
Sep 24, 2014
by
Tomasz Wlostowski
feature
0
updated
Jul 24, 2023
PTS: timing violation in DAC signal.
#19
· opened
Sep 22, 2014
by
Erik van der Bij
feature
0
updated
Aug 24, 2023
V4 - consider placing fan instead of the cutout under FMC
#20
· opened
Sep 19, 2014
by
Tomasz Wlostowski
feature
0
updated
Oct 13, 2023
V4 - Make hardwired PLL settings configurable
#22
· opened
Jul 24, 2014
by
Erik van der Bij
feature
0
updated
Mar 22, 2024
V4 - not compatible PCIe Gen3?
#23
· opened
Jun 10, 2014
by
Erik van der Bij
bug
0
updated
Apr 10, 2024
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