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SPEC7
Commit 033bb773 authored by Pascal Bos's avatar Pascal Bos
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Removed old arm_base_sytstem

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    hdl/arm_base_system/syn/.gitignore deleted 100644 → 0
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    /.Xil
    /NONE
    /work
    /*.bak
    /*.jou
    /*.log
    /*.prm
    /*.mcs
    /*.bin
    /*.bit
    /spec7_write_top_bd.bmm
    /revisiondate_log.txt
    /hdl_version.xdc
    hdl/arm_base_system/syn/README.TXT deleted 100644 → 0
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    Synthesis and Place&Route README.TXT October 09, 2019
    --------------------------------------------------------
    Scripts:
    --------
    1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
    2) do_vivado_tcl.cmd start vivado tcl console.
    You may want to type:
    a) "start_gui" to start the vivado gui
    b) "source proj_properties.tcl" to find the path to the scripts and next
    "source $script_dir/viv_do_all.tcl"
    3) do_vivado_prog.cmd download the configuration ("%DesName%.bit") into the Evaluation board via the USB
    download cable.
    Project info and sources:
    --------
    proj_properties.tcl contains the project properties (name, device etc.)
    proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
    using "hdlmake list-files > proj_file_list.txt" in
    directory "../../wr-cores/syn/clbv3_ref_design"
    Scripts that are called by the scripts above or can be executed separately on the tcl command line:
    --------
    viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
    viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
    viv_do_program.tcl sourced by do_vivado_prog.cmd
    hdl/arm_base_system/syn/do_vivado.cmd deleted 100644 → 0
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    rem do_vivado.cmd PeterJ, 19-Jan-2018.
    @prompt $$$s
    rem ### Cleanup old log files and stuff
    del *.log
    del *.jou
    rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
    rem ### in your (User) Environment Variables
    "%VIVADO%\vivado.bat" -mode batch -source viv_do_all.tcl
    hdl/arm_base_system/syn/do_vivado_prog.cmd deleted 100644 → 0
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    rem prog.cmd PeterJ, 23-Jan-2018.
    @prompt $$$s
    rem ### Cleanup old log files and stuff
    del vivado_prog.log
    rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
    rem ### in your (User) Environment Variables
    "%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
    hdl/arm_base_system/syn/do_vivado_tcl.cmd deleted 100644 → 0
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    rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
    @prompt $$$s
    rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
    rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
    rem set DesName=clbv3_wr_ref_top
    rem set LogName=%DesName%-vivado
    rem ### Cleanup old log files and stuff (
    rem del vivado*.log
    rem del vivado*.jou
    rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
    rem ### in your (User) Environment Variables
    "%VIVADO%\vivado.bat" -mode tcl
    hdl/arm_base_system/syn/proj_file_list.txt deleted 100644 → 0
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    # From directory ../../wr-cores/syn/spec7_write_design
    # hdlmake list-files > proj_file_list.txt
    #../top/ip/processing_system7_0/processing_system7_0.xci
    ../top/arm_base_sys.vhd
    ../top/arm_base_sys.xdc
    # include hardware version ID un FPGA USER_ID register:
    hdl_version.xdc
    hdl/arm_base_system/syn/proj_properties.tcl deleted 100644 → 0
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    #
    # projetc_properties.tcl
    # This file contains the general project properties such as the project name and
    # the directory where Vivado is doing it's job
    #
    set proj_name arm_base_sys
    set proj_dir work
    set script_dir [pwd]/../../../sw/scripts
    # update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
    if {$argc == 0 || $argv != "no_update_revision"} {
    source $script_dir/revisiondate.tcl
    set generics ""
    }
    # SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
    set device xc7z035fbg676-1
    #set device xc7z030fbg676-1
    hdl/arm_base_system/syn/viv_do_all.tcl deleted 100644 → 0
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    # viv_do_all.tcl PeterJ, 24-Jan-2018.
    #
    # This script does:
    # set project name
    # set part name
    # creates a new project
    # imports the source files
    # launches synthesis
    # launches implementation
    # generates a bitfile
    # ------------------------------------
    # set proj_name and proj_dir:
    source proj_properties.tcl
    # Format the raw time [clock seconds] to a date string
    puts "[set date_string [clock format [clock seconds] -format "date: %y-%m-%d, time: %H:%M:%S"]] Implementation Started of $proj_name"
    #Close currently open project and create a new one. (OVERWRITES PROJECT!!)
    close_project -quiet
    # Remove old and Create the new build directory
    file delete -force $proj_dir
    #file mkdir $proj_dir
    create_project -force -part $device $proj_name ./$proj_dir
    # work_directory is *full* path project directory.
    # Vivado doesn't seem to accept relative paths!?
    set work_directory [get_property DIRECTORY [current_project]]
    # Create a hdl_version.xdc file to set the bitfile USERID to the revision date/version
    set revision_log_file "revisiondate_log.txt"
    if [file exists $revision_log_file] {
    set revision_log_fileptr [open $revision_log_file]
    gets $revision_log_fileptr revision_log_date
    gets $revision_log_fileptr revision_log_revnumber
    close $revision_log_fileptr
    set userid [format "0x%6d%02d" $revision_log_date $revision_log_revnumber]
    puts "Bitfile USERID set to $userid"
    } else {
    set userid 0xFFFFFFFF
    puts "WARNING Bitfile USERID set to 0xFFFFFFFF"
    }
    set hdl_version_file [open hdl_version.xdc w]
    puts $hdl_version_file "set_property BITSTREAM.CONFIG.USERID $userid \[current_design\]"
    close $hdl_version_file
    set_property target_language VHDL [current_project]
    # ------------------------------------------------------------------------------
    # Read source files
    # ------------------------------------------------------------------------------
    set fp [open "proj_file_list.txt" r]
    set file_data [read $fp]
    close $fp
    set content [split $file_data "\n"]
    set use_bmm false
    foreach line $content {
    puts $line
    set line_length [ string length $line ]
    if {[string range $line 0 0] == "#"} {
    # puts "comment"
    } elseif {[string range $line $line_length-4 $line_length] == ".vhd"} {
    # puts "vhdl"
    read_vhdl -library work $line
    } elseif {[string range $line $line_length-2 $line_length] == ".v"} {
    # puts "verilog"
    read_verilog -library work $line
    } elseif {[string range $line $line_length-3 $line_length] == ".vh"} {
    # puts "verilog"
    read_verilog -library work $line
    } elseif {[string range $line $line_length-3 $line_length] == ".sv"} {
    # puts "verilog"
    read_verilog -sv -library work $line
    } elseif {[string range $line $line_length-4 $line_length] == ".svh"} {
    # puts "verilog"
    read_verilog -sv -library work $line
    } elseif {[string range $line $line_length-4 $line_length] == ".xci"} {
    # puts "system verilog"
    read_ip $line
    } elseif {[string range $line $line_length-4 $line_length] == ".xdc"} {
    # Read constraints file if any
    # puts "xdc"
    read_xdc -verbose $line
    } elseif {[string range $line $line_length-4 $line_length] == ".bmm"} {
    # Set pointer to bmm file if any
    # puts "bmm"
    set use_bmm true
    set bmm_file [pwd]/$line
    set bmm_bd ${proj_name}_bd.bmm
    add_files -norecurse $bmm_file
    }
    }
    # Set Top level
    set_property top $proj_name [current_fileset]
    set_property source_mgmt_mode All [current_project]
    update_compile_order -fileset sources_1
    # Pass generics
    set_property generic $generics [current_fileset]
    puts "INFO: Reading Source Files Done!"
    source ../top/ip/processing_system_bd.tcl
    # ------------------------------------------------------------------------------
    source $script_dir/viv_do_synt.tcl
    source $script_dir/viv_do_impl.tcl
    if {$use_bmm} {
    source $script_dir/viv_generate_bd_bmm.tcl
    }
    file copy -force $proj_dir/$proj_name.runs/impl_1/$proj_name.bit .
    write_hw_platform -fixed -force -include_bit -file $proj_name.xsa
    hdl/arm_base_system/top/arm_base_sys.vhd deleted 100644 → 0
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    -------------------------------------------------------------------------------
    -- Title : WRPC reference design for SPEC7
    -- : based on ZYNQ Z030/Z035/Z045
    -- Project : ARM_BASE_SYS
    -- URL : http://empir.npl.co.uk/write/
    -------------------------------------------------------------------------------
    -- File : arm_base_sys.vhd
    -- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
    -- Company : Nikhef
    -- Created : 2019-10-09
    -- Last update: 2019-10-09
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description: Top-level file for the WRPC reference design on the SPEC7
    -- in combination with the High Stability external Oscillator.
    -- See also EMPIR 17IND14 WRITE Project (http://empir.npl.co.uk/write/)
    --
    -------------------------------------------------------------------------------
    -- Copyright (c) 2019 Nikhef
    -------------------------------------------------------------------------------
    -- GNU LESSER GENERAL PUBLIC LICENSE
    --
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    --
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    --
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- from http://www.gnu.org/licenses/lgpl-2.1.html
    --
    -------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    library work;
    library unisim;
    use unisim.vcomponents.all;
    entity arm_base_sys is
    port (
    MIO : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
    DDR_CAS_n : INOUT STD_LOGIC;
    DDR_CKE : INOUT STD_LOGIC;
    DDR_Clk_n : INOUT STD_LOGIC;
    DDR_Clk_p : INOUT STD_LOGIC;
    DDR_CS_n : INOUT STD_LOGIC;
    DDR_DRSTB : INOUT STD_LOGIC;
    DDR_ODT : INOUT STD_LOGIC;
    DDR_RAS_n : INOUT STD_LOGIC;
    DDR_WEB : INOUT STD_LOGIC;
    DDR_BankAddr : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    DDR_Addr : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
    DDR_VRN : INOUT STD_LOGIC;
    DDR_VRP : INOUT STD_LOGIC;
    DDR_DM : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    DDR_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    DDR_DQS_n : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    DDR_DQS_p : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    PS_SRSTB : INOUT STD_LOGIC;
    PS_CLK : INOUT STD_LOGIC;
    PS_PORB : INOUT STD_LOGIC;
    leds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
    end entity arm_base_sys;
    architecture top of arm_base_sys is
    -----------------------------------------------------------------------------
    -- Constants
    -----------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    -- Signals
    -----------------------------------------------------------------------------
    component processing_system is
    port (
    DDR_cas_n : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    gpio_rtl_0_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 )
    );
    end component processing_system;
    begin
    processing_system_i: component processing_system
    port map (
    DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
    DDR_ba(2 downto 0) => DDR_BankAddr(2 downto 0),
    DDR_cas_n => DDR_cas_n,
    DDR_ck_n => DDR_Clk_n,
    DDR_ck_p => DDR_Clk_p,
    DDR_cke => DDR_cke,
    DDR_cs_n => DDR_cs_n,
    DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
    DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
    DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
    DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
    DDR_odt => DDR_odt,
    DDR_ras_n => DDR_ras_n,
    DDR_reset_n => DDR_DRSTB,
    DDR_we_n => DDR_WEB,
    FIXED_IO_ddr_vrn => DDR_VRN,
    FIXED_IO_ddr_vrp => DDR_VRP,
    FIXED_IO_mio(53 downto 0) => MIO(53 downto 0),
    FIXED_IO_ps_clk => PS_CLK,
    FIXED_IO_ps_porb => PS_PORB,
    FIXED_IO_ps_srstb => PS_SRSTB,
    gpio_rtl_0_tri_o => leds(3 downto 0)
    );
    end architecture top;
    hdl/arm_base_system/top/arm_base_sys.xdc deleted 100644 → 0
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    hdl/arm_base_system/top/ip/processing_system_bd.tcl deleted 100644 → 0
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