Skip to content

S
SPEC7
Commit 1e58bc04 authored by Peter Jansweijer's avatar Peter Jansweijer
Browse files
Options

Add generic g_dac_bits to accomodate 20 bits DAC MAX5719A for main pll

parent b222ae5b
Hide whitespace changes
Inline Side-by-side
Showing with 69 additions and 20 deletions
hdl/board/wr_spec7_pkg.vhd
View file @ 1e58bc04
......@@ -59,6 +59,7 @@ package wr_spec7_pkg is
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
g_dac_bits : integer := 16;
g_refclk_tune_pos_slope : boolean := TRUE);
port (
areset_n_i : in std_logic;
......
hdl/board/xwrc_board_spec7.vhd
View file @ 1e58bc04
......@@ -77,6 +77,7 @@ entity xwrc_board_spec7 is
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
g_dac_bits : integer := 16;
g_refclk_tune_pos_slope : boolean := TRUE
);
port (
......@@ -302,10 +303,11 @@ architecture struct of xwrc_board_spec7 is
-- PLL DACs
signal dac_dmtd_load : std_logic;
signal dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_dmtd_data : std_logic_vector(g_dac_bits-1 downto 0);
signal dac_refclk_load : std_logic;
signal dac_refclk_data : std_logic_vector(15 downto 0);
signal dac_refclk_data_slp : std_logic_vector(15 downto 0);
signal dac_refclk_data : std_logic_vector(g_dac_bits-1 downto 0);
signal dac_refclk_data_slp : std_logic_vector(g_dac_bits-1 downto 0);
signal dac_max5719_data : std_logic_vector(23 downto 0);
-- OneWire
signal onewire_in : std_logic_vector(1 downto 0);
......@@ -602,6 +604,9 @@ begin -- architecture struct
-- 2x SPI DAC
-----------------------------------------------------------------------------
-- 16 bit DAC AD5662 uses 24 SCLK; 8 bits '0' + bits [D15 to D0]
-- Note: The WR PI control loop is g_dac_bits wide.
-- Use 16 MSBs to drive the 16 DMTD DAC bits (15 downto 0)
cmp_dmtd_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
......@@ -611,7 +616,7 @@ begin -- architecture struct
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_dmtd_data,
value_i => dac_dmtd_data(g_dac_bits-1 downto g_dac_bits-16),
cs_sel_i => "1",
load_i => dac_dmtd_load,
sclk_divsel_i => "001",
......@@ -631,22 +636,49 @@ begin -- architecture struct
dac_refclk_data_slp <= not dac_refclk_data;
end generate gen_refclk_tune_neg_slope;
cmp_refclk_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 1)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_refclk_data_slp,
cs_sel_i => "1",
load_i => dac_refclk_load,
sclk_divsel_i => "001",
dac_cs_n_o(0) => dac_refclk_cs_n_o,
dac_sclk_o => dac_refclk_sclk_o,
dac_sdata_o => dac_refclk_din_o);
gen_default_dac16 : if (g_dac_bits /= 20)
generate
-- Default 16 bit DAC AD5662 uses 24 SCLK; 8 bits '0' + bits [D15 to D0]
cmp_refclk_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 1)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_refclk_data_slp,
cs_sel_i => "1",
load_i => dac_refclk_load,
sclk_divsel_i => "001",
dac_cs_n_o(0) => dac_refclk_cs_n_o,
dac_sclk_o => dac_refclk_sclk_o,
dac_sdata_o => dac_refclk_din_o);
end generate gen_default_dac16;
gen_dac20 : if (g_dac_bits = 20)
generate
-- 20 bit DAC MAX5719A uses 24 SCLK; bits [D19 to D0] + 4 bits don't care
dac_max5719_data <= dac_refclk_data_slp & "0000";
cmp_refclk_dac : gc_serial_dac
generic map (
g_num_data_bits => 24,
g_num_extra_bits => 0,
g_num_cs_select => 1,
g_sclk_polarity => 1)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_max5719_data,
cs_sel_i => "1",
load_i => dac_refclk_load,
sclk_divsel_i => "001",
dac_cs_n_o(0) => dac_refclk_cs_n_o,
dac_sclk_o => dac_refclk_sclk_o,
dac_sdata_o => dac_refclk_din_o);
end generate gen_dac20;
-----------------------------------------------------------------------------
-- The WR PTP core with optional fabric interface attached
......@@ -676,6 +708,7 @@ begin -- architecture struct
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_dac_bits => g_dac_bits,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
......
hdl/syn/spec7_ref_design/proj_properties.tcl
View file @ 1e58bc04
......@@ -49,6 +49,17 @@ set refclk_tune_pos_slope FALSE
set irig_b_enable TRUE
# ====================================================
# ====================================================
# SELECT DAC BITS:
# ====================================================
# AD5662 => dac bits = 16 (DEFAULT)
# MAX5719A => dac bits = 20
set dac_bits 16
#set dac_bits 20
# ====================================================
# ====================================================
# Translate True/False into boolean values 1'b1, 1'b0, that are accepted by Vivado
set vivbool_refclk_tune_pos_slope 1'b1
if [info exists refclk_tune_pos_slope] {
......@@ -79,5 +90,6 @@ if {$argc == 0 || $argv != "no_update_revision"} {
g_use_pps_in=$pps_in \
g_dpram_initf=$wrpc_cpu_initf \
g_refclk_tune_pos_slope=$vivbool_refclk_tune_pos_slope \
g_dac_bits=$dac_bits \
g_irig_b_enable=$vivbool_irig_b_enable"
}
hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
View file @ 1e58bc04
......@@ -80,6 +80,7 @@ entity spec7_wr_ref_top is
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0;
g_dac_bits : integer := 16;
g_use_pps_in : string := "single";
g_refclk_tune_pos_slope : boolean := TRUE;
g_irig_b_enable : boolean := FALSE
......@@ -581,6 +582,7 @@ end generate gen_irig_b;
cmp_xwrc_board_spec7 : xwrc_board_spec7
generic map (
g_simulation => g_simulation,
g_dac_bits => g_dac_bits,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => PLAIN,
......
sw/scripts/viv_do_all.tcl
View file @ 1e58bc04
......@@ -223,6 +223,7 @@ if [info exists irig_b_enable] {
puts $git_log_fp "IRIG-B module implemented"
}
}
puts $git_log_fp "DAC bits = $dac_bits"
puts $git_log_fp "Build was based on the following SHA codes:"
puts $git_log_fp "spec7.git $spec7_sha"
puts $git_log_fp "wr-cores.git $wr_cores_sha"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment