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SPEC7
Commits
3637edc9
Commit
3637edc9
authored
Dec 19, 2022
by
Peter Jansweijer
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use '-add' to keep derived domains
parent
5fde1bbb
Pipeline
#5034
failed with stage
in 2 minutes and 15 seconds
Changes
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4 changed files
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20 deletions
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-20
spec7_wr_hpsec_top.xdc
hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
+3
-5
spec7_wr_hpsec_top_v2.xdc
hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc
+3
-5
spec7_wr_ref_top.xdc
hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
+3
-5
spec7_wr_ref_top_v2.xdc
hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
+3
-5
No files found.
hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
View file @
3637edc9
...
...
@@ -28,10 +28,10 @@ create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
#create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 16.000 -
add -
name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -
add -
name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
#
kent ie niet
:
#
not known by Vivado
:
#create_clock -period 100.000 -name clk_ext_10m -waveform {0.000 50.000} [get_nets clk_ext_10m]
#create_clock -period 100.000 -name dio_clk -waveform {0.000 50.000} [get_ports dio_clk_p_i]
...
...
@@ -43,8 +43,6 @@ set_clock_groups -asynchronous \
-group clk_125m_gtx_odiv2 \
-group clk_125m_dmtd \
-group clk_125m_dmtd_div2 \
-group RXOUTCLK \
-group TXOUTCLK \
-group fmc_clk_ext_10m \
-group be_clk_ext_10m
...
...
hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc
View file @
3637edc9
...
...
@@ -28,10 +28,10 @@ create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 16.000 -
add -
name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -
add -
name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
#
kent ie niet
:
#
not known by Vivado
:
#create_clock -period 100.000 -name clk_ext_10m -waveform {0.000 50.000} [get_nets clk_ext_10m]
#create_clock -period 100.000 -name dio_clk -waveform {0.000 50.000} [get_ports dio_clk_p_i]
...
...
@@ -43,8 +43,6 @@ set_clock_groups -asynchronous \
-group clk_125m_gtx_odiv2 \
-group clk_125m_dmtd \
-group clk_125m_dmtd_div2 \
-group RXOUTCLK \
-group TXOUTCLK \
-group fmc_clk_ext_10m \
-group be_clk_ext_10m
...
...
hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
View file @
3637edc9
...
...
@@ -28,10 +28,10 @@ create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
#create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 16.000 -
add -
name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -
add -
name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
#
kent ie niet
:
#
not known by Vivado
:
#create_clock -period 100.000 -name clk_ext_10m -waveform {0.000 50.000} [get_nets clk_ext_10m]
#create_clock -period 100.000 -name dio_clk -waveform {0.000 50.000} [get_ports dio_clk_p_i]
...
...
@@ -43,8 +43,6 @@ set_clock_groups -asynchronous \
-group clk_125m_gtx_odiv2 \
-group clk_125m_dmtd \
-group clk_125m_dmtd_div2 \
-group RXOUTCLK \
-group TXOUTCLK \
-group fmc_clk_ext_10m \
-group be_clk_ext_10m
...
...
hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
View file @
3637edc9
...
...
@@ -28,10 +28,10 @@ create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 16.000 -
add -
name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -
add -
name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
#
kent ie niet
:
#
not known by Vivado
:
#create_clock -period 100.000 -name clk_ext_10m -waveform {0.000 50.000} [get_nets clk_ext_10m]
#create_clock -period 100.000 -name dio_clk -waveform {0.000 50.000} [get_ports dio_clk_p_i]
...
...
@@ -43,8 +43,6 @@ set_clock_groups -asynchronous \
-group clk_125m_gtx_odiv2 \
-group clk_125m_dmtd \
-group clk_125m_dmtd_div2 \
-group RXOUTCLK \
-group TXOUTCLK \
-group fmc_clk_ext_10m \
-group be_clk_ext_10m
...
...
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