add fsbl build commands

8301e5b3 · Peter Jansweijer · b8c9f759 · 8301e5b3 · 8301e5b3 · 8301e5b3
Commit 8301e5b3 authored Jul 08, 2021 by Peter Jansweijer
Hide whitespace changes
Inline Side-by-side

Showing with 104 additions and 0 deletions

Makefile sw/fsbl/Makefile +7 -0

do_vitis.cmd sw/fsbl/do_vitis.cmd +6 -0

fsbl.tcl sw/fsbl/fsbl.tcl +91 -0

No files found.
--- a/sw/fsbl/Makefile
+++ b/sw/fsbl/Makefile
+build:
+	xsct ./fsbl.tcl
+
+clean:
+	rm -rf build *.Xil
+
+
--- a/sw/fsbl/do_vitis.cmd
+++ b/sw/fsbl/do_vitis.cmd
+rem do_vitis.cmd  PeterJ,    08-Jul-2021.
+@prompt $$$s
+
+rem ### note that environment variable "VITIS" must be set to something like "C:\Xilinx\Vitis_HLS\2020.2\bin"
+rem ### in your (User) Environment Variables
+"%VITIS%\xsct.bat" .\fsbl.tcl > fsbl.log
--- a/sw/fsbl/fsbl.tcl
+++ b/sw/fsbl/fsbl.tcl
+#-----------------------------------------------------------------------------
+# Title      : fsbl
+#-----------------------------------------------------------------------------
+# File       : fsbl.tcl
+# Author     : Mamta Shukla <mamta.ramendra.shukla@cern.ch>
+#            : Peter Jansweijer <peterj@nikhef.nl>
+# Company    : CERN / Nikhef
+# Created    : 2021-06-08
+# Last update: 2021-06-08
+# Platform   : FPGA-embedded software
+# Standard   : 
+#-----------------------------------------------------------------------------
+# Description:
+#
+# This script does:
+# build the First Stage Boot Loader (FSBL) using Vitis
+# See also <https://spec7.readthedocs.io/en/latest/fsbl.html>
+#-----------------------------------------------------------------------------
+#
+# Copyright (c) 2021 CERN, Mamta Shukla; Nikhef, Peter Jansweijer
+#
+# This source file is free software; you can redistribute it   
+# and/or modify it under the terms of the GNU Lesser General   
+# Public License as published by the Free Software Foundation; 
+# either version 2.1 of the License, or (at your option) any   
+# later version.                                               
+#
+# This source is distributed in the hope that it will be       
+# useful, but WITHOUT ANY WARRANTY; without even the implied   
+# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+# PURPOSE.  See the GNU Lesser General Public License for more 
+# details.                                                     
+#
+# You should have received a copy of the GNU Lesser General    
+# Public License along with this source; if not, download it   
+# from http://www.gnu.org/licenses/lgpl-2.1.html
+#
+#-----------------------------------------------------------------------------
+
+set hwdir_base_name "../../hdl/syn/spec7_tandem_boot/work/spec7_tandem_boot_top"
+set xsa_file [glob $hwdir_base_name*.xsa]
+
+# check if Vivado exported hardware description (xsa) exists
+if ![file exists $xsa_file] {
+  puts "### no xsa file exists in ../../hdl/syn/spec7_tandem_boot/work !"
+  puts "### Build the firmware first (i.e. execute: ../../hdl/syn/spec7_tandem_boot/do_vivado.cmd)."
+  exit 0
+} else {
+  # hardware file exists! create pointer to corresponding log file
+  set log_file [glob $hwdir_base_name*.log]
+  # and extract the timestamp
+  set idx_start [string length $hwdir_base_name]
+  set len_xsa_file [string length $xsa_file]
+  set timestamp [string range $xsa_file $idx_start [expr ($len_xsa_file - 5)]]
+  
+  # Copy the "current" timestamped xsa file to a general name exported_hw.xsa
+  file copy -force $xsa_file exported_hw.xsa
+  # Copy the full timestamped and logged xsa and log file to enable version trace-back 
+  file copy -force $xsa_file .
+  file copy -force $log_file .
+  # Format the raw time [clock seconds] to a date string
+  puts "[set date_string [clock format [clock seconds] -format "date: %y-%m-%d, time: %H:%M:%S"]] Implementation Started"
+  puts "Using hardware design: $xsa_file"
+}
+
+# Remove old and Set the new build directory
+file delete -force build
+setws build
+
+platform create -name spec7 \
+-hw exported_hw.xsa -no-boot-bsp
+platform active spec7
+
+# Create FSBL application
+domain create -name "fsbl_domain" -os standalone -proc ps7_cortexa9_0
+bsp setlib xilffs
+bsp config stdin ps7_uart_1
+bsp config stdout ps7_uart_1
+
+platform generate
+
+app create -name zynq_fsbl -template {Zynq FSBL} \
+-platform spec7 -domain fsbl_domain -sysproj spec7_system
+
+app config -name zynq_fsbl build-config release
+app config -name zynq_fsbl build-config
+app build -name zynq_fsbl
+
+# Create a copy of zynq_fsbl with xsa timestamp
+file copy -force ./build/zynq_fsbl/Release/zynq_fsbl.elf . 
+file copy -force ./build/zynq_fsbl/Release/zynq_fsbl.elf zynq_fsbl${timestamp}.elf