svec: add Luis' code (fw loader and VME bus matching)

I made some minor fixes to correctly build the driver 1. compile under 3.2 (actually 2.6.26+) with no Module.symvers dependencies on vmebridge. Module.symvers.vme has been consequently added 2. usleep_range belongs to <linux/delay.h>, not <linux/timer.h> 3. include/ is now a sibling of kernel/

svec: add Luis' code (fw loader and VME bus matching)
I made some minor fixes to correctly build the driver 1. compile under 3.2 (actually 2.6.26+) with no Module.symvers dependencies on vmebridge. Module.symvers.vme has been consequently added 2. usleep_range belongs to <linux/delay.h>, not <linux/timer.h> 3. include/ is now a sibling of kernel/
10dacc1d · Juan David González Cobas · 7b13a8b2 · 10dacc1d · 10dacc1d · 10dacc1d
Commit 10dacc1d authored Nov 13, 2012 by Juan David González Cobas
9 changed files
--- a/include/libvmebus.h
+++ b/include/libvmebus.h
+/**
+ * \file libvmebus.h
+ * \brief VME Bus access user library interface
+ * \author Sbastien Dugu
+ * \date 04/02/2009
+ *
+ * This library gives userspace applications access to the VME bus
+ *
+ * Copyright (c) 2009 \em Sbastien \em Dugu
+ *
+ * \par License:
+ *      This program is free software; you can redistribute  it and/or
+ *      modify it under  the terms of  the GNU General  Public License as
+ *      published by the Free Software Foundation;  either version 2 of the
+ *      License, or (at your option) any later version.
+ *
+ */
+
+#ifndef _LIBVMEBUS_H_INCLUDE_
+#define _LIBVMEBUS_H_INCLUDE_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <vmebus.h>
+
+/**
+ * \brief Swap a 16-bit halfword bytewise
+ * \param val The 16-bit halfword to swap
+ *
+ * \return The swapped value
+ *
+ */
+static inline unsigned short swapbe16(unsigned short val)
+{
+	return (((val & 0xff00) >> 8) | ((val & 0xff) << 8));
+}
+
+/**
+ * \brief Swap a 32-bit word bytewise
+ * \param val The 32-bit word to swap
+ *
+ * \return The swapped value
+ *
+ */
+static inline unsigned int swapbe32(unsigned int val)
+{
+	return (((val & 0xff000000) >> 24) | ((val & 0xff0000) >> 8) |
+		((val & 0xff00) << 8) | ((val & 0xff) << 24));
+}
+
+
+extern int vme_bus_error_check(struct vme_mapping *desc);
+extern int vme_bus_error_check_clear(struct vme_mapping *desc, __u64 address);
+
+/* VME address space mapping - CES library emulation */
+extern unsigned long find_controller(unsigned long vmeaddr, unsigned long len,
+				     unsigned long am, unsigned long offset,
+				     unsigned long size,
+				     struct pdparam_master *param);
+extern unsigned long return_controller(struct vme_mapping *desc);
+
+/* VME address space mapping */
+extern void *vme_map(struct vme_mapping *, int);
+extern int vme_unmap(struct vme_mapping *, int);
+
+/* DMA access */
+extern int vme_dma_read(struct vme_dma *);
+extern int vme_dma_write(struct vme_dma *);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _LIBVMEBUS_H_INCLUDE_ */
--- a/include/vmebus.h
+++ b/include/vmebus.h
--- a/kernel/Kbuild
+++ b/kernel/Kbuild
+EXTRA_CFLAGS += -I $(M)/../include
+KBUILD_EXTRA_SYMBOLS += $(M)/Module.symvers.vme
+
+obj-m := svec.o
+svec-objs := svec_drv.o
--- a/kernel/Makefile
+++ b/kernel/Makefile
+CPU	:= L865
+KVER	:= 3.2.33-rt50
+KERN_DIR:= "/acc/sys/$(CPU)/usr/src/kernels/$(KVER)"
+VME_DIR := "../../repo/vmebridge/driver"
+#VME_OBJDIR := "../../repo/vmebridge/driver/$(CPU)/$(KVER)"
+VME_OBJDIR := "../../repo/vmebridge/driver/"
+
+ccflags-y += -DDEBUG
+
+all: modules
+	$(MAKE) -C $(KERN_DIR) M=$(shell /bin/pwd)
+.PHONY: all clean help
+
+modules:
+	$(MAKE) -C $(KERN_DIR) M=$(shell pwd) CPU=$(CPU) KVER=$(KVER) 
+
+clean:
+	$(MAKE) -C $(KERN_DIR) M=`pwd` clean
+
+help:
+	$(MAKE) -C $(KERN_DIR) M=`pwd` help
--- a/kernel/Module.symvers.vme
+++ b/kernel/Module.symvers.vme
+0x00000000	vme_bus_error_check	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_create_window	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_release_mapping	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_unregister_driver	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_do_dma_kernel	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	find_controller	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_register_berr_handler	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_request_irq	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_free_irq	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	find_vme_mapping_from_addr	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_find_mapping	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_bus_error_check_clear	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_register_driver	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_generate_interrupt	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_destroy_window	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_do_dma	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	return_controller	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_unregister_berr_handler	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_intset	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_intclr	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
+0x00000000	vme_get_window_attr	/acc/src/dsc/drivers/coht/vmebridge/driver/vmebus	EXPORT_SYMBOL_GPL
--- a/kernel/install.SVEC_WIP
+++ b/kernel/install.SVEC_WIP
+#!/bin/sh
+echo Installing svec WIP driver...
+echo 8 > /proc/sys/kernel/printk
+
+/sbin/insmod svec.ko lun=0 vmebase1=0x900000 vmebase2=0x6000 vector=0x86 level=2
+MAJOR=`cat /proc/devices | awk '{if ($2 == "svec") printf $1}'`
+echo Making nodes for ${MODULE} major device svec ${MAJOR}
+if [ -z "$MAJOR" ]; then
+     echo "driver SVEC not installed !"
+     exit 2
+fi
+
+rm -f /dev/svec.*
+#/bin/mknod  -m 0666 /dev/svec.0 c ${MAJOR} 0
+
--- a/kernel/svec.h
+++ b/kernel/svec.h
+/*
+ * svec_priv.h
+ *
+ * private SVEC definitions
+ */
+
+#ifndef _SVEC_PRIV_H_
+#define _SVEC_PRIV_H_
+
+#define SVEC_MAX_DEVICES        32
+
+#define SVEC_DEFAULT_IDX { [0 ... (SVEC_MAX_DEVICES-1)] = -1 }
+
+
+
+#endif
+
+
--- a/kernel/svec_drv.c
+++ b/kernel/svec_drv.c
--- a/kernel/xloader_regs.h
+++ b/kernel/xloader_regs.h
+/*
+  Register definitions for slave core: Xilinx FPGA loader
+
+  * File           : xloader_regs.h
+  * Author         : auto-generated by wbgen2 from xloader_wb.wb
+  * Created        : Thu Jun 21 15:17:30 2012
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xloader_wb.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_XLOADER_WB_WB
+#define __WBGEN2_REGDEFS_XLOADER_WB_WB
+
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Control/status register */
+
+/* definitions for field: Start configuration in reg: Control/status register */
+#define XLDR_CSR_START                        WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Configuration done in reg: Control/status register */
+#define XLDR_CSR_DONE                         WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Configuration error in reg: Control/status register */
+#define XLDR_CSR_ERROR                        WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Loader busy in reg: Control/status register */
+#define XLDR_CSR_BUSY                         WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: Byte order select in reg: Control/status register */
+#define XLDR_CSR_MSBF                         WBGEN2_GEN_MASK(4, 1)
+
+/* definitions for field: Software resest in reg: Control/status register */
+#define XLDR_CSR_SWRST                        WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: Exit bootloader mode in reg: Control/status register */
+#define XLDR_CSR_EXIT                         WBGEN2_GEN_MASK(6, 1)
+
+/* definitions for field: Serial clock divider in reg: Control/status register */
+#define XLDR_CSR_CLKDIV_MASK                  WBGEN2_GEN_MASK(8, 6)
+#define XLDR_CSR_CLKDIV_SHIFT                 8
+#define XLDR_CSR_CLKDIV_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
+#define XLDR_CSR_CLKDIV_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)
+
+/* definitions for register: Bootloader Trigger Register */
+
+/* definitions for register: GPIO Output Register */
+
+/* definitions for register: ID Register */
+
+/* definitions for register: FIFO 'Bitstream FIFO' data input register 0 */
+
+/* definitions for field: Entry size in reg: FIFO 'Bitstream FIFO' data input register 0 */
+#define XLDR_FIFO_R0_XSIZE_MASK               WBGEN2_GEN_MASK(0, 2)
+#define XLDR_FIFO_R0_XSIZE_SHIFT              0
+#define XLDR_FIFO_R0_XSIZE_W(value)           WBGEN2_GEN_WRITE(value, 0, 2)
+#define XLDR_FIFO_R0_XSIZE_R(reg)             WBGEN2_GEN_READ(reg, 0, 2)
+
+/* definitions for field: Last xfer in reg: FIFO 'Bitstream FIFO' data input register 0 */
+#define XLDR_FIFO_R0_XLAST                    WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for register: FIFO 'Bitstream FIFO' data input register 1 */
+
+/* definitions for field: Data in reg: FIFO 'Bitstream FIFO' data input register 1 */
+#define XLDR_FIFO_R1_XDATA_MASK               WBGEN2_GEN_MASK(0, 32)
+#define XLDR_FIFO_R1_XDATA_SHIFT              0
+#define XLDR_FIFO_R1_XDATA_W(value)           WBGEN2_GEN_WRITE(value, 0, 32)
+#define XLDR_FIFO_R1_XDATA_R(reg)             WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'Bitstream FIFO' control/status register */
+
+/* definitions for field: FIFO full flag in reg: FIFO 'Bitstream FIFO' control/status register */
+#define XLDR_FIFO_CSR_FULL                    WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: FIFO empty flag in reg: FIFO 'Bitstream FIFO' control/status register */
+#define XLDR_FIFO_CSR_EMPTY                   WBGEN2_GEN_MASK(17, 1)
+
+/* definitions for field: FIFO clear in reg: FIFO 'Bitstream FIFO' control/status register */
+#define XLDR_FIFO_CSR_CLEAR_BUS               WBGEN2_GEN_MASK(18, 1)
+
+/* definitions for field: FIFO counter in reg: FIFO 'Bitstream FIFO' control/status register */
+#define XLDR_FIFO_CSR_USEDW_MASK              WBGEN2_GEN_MASK(0, 8)
+#define XLDR_FIFO_CSR_USEDW_SHIFT             0
+#define XLDR_FIFO_CSR_USEDW_W(value)          WBGEN2_GEN_WRITE(value, 0, 8)
+#define XLDR_FIFO_CSR_USEDW_R(reg)            WBGEN2_GEN_READ(reg, 0, 8)
+/* [0x0]: REG Control/status register */
+#define XLDR_REG_CSR 0x00000000
+/* [0x4]: REG Bootloader Trigger Register */
+#define XLDR_REG_BTRIGR 0x00000004
+/* [0x8]: REG GPIO Output Register */
+#define XLDR_REG_GPIOR 0x00000008
+/* [0xc]: REG ID Register */
+#define XLDR_REG_IDR 0x0000000c
+/* [0x10]: REG FIFO 'Bitstream FIFO' data input register 0 */
+#define XLDR_REG_FIFO_R0 0x00000010
+/* [0x14]: REG FIFO 'Bitstream FIFO' data input register 1 */
+#define XLDR_REG_FIFO_R1 0x00000014
+/* [0x18]: REG FIFO 'Bitstream FIFO' control/status register */
+#define XLDR_REG_FIFO_CSR 0x00000018
+#endif