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Simple VME FMC Carrier SVEC
Commit 1f3df4cd authored by Federico Vaga's avatar Federico Vaga
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sw:drv: checkpatch fixes 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 4164a478
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Showing with 29 additions and 23 deletions
software/kernel/svec-compat.c
View file @ 1f3df4cd
...@@ -56,7 +56,8 @@ struct fpga_manager *fpga_mgr_get(struct device *dev) ...@@ -56,7 +56,8 @@ struct fpga_manager *fpga_mgr_get(struct device *dev)
struct class *fpga_mgr_class = (struct class *) kallsyms_lookup_name("fpga_mgr_class"); struct class *fpga_mgr_class = (struct class *) kallsyms_lookup_name("fpga_mgr_class");
struct device *mgr_dev; struct device *mgr_dev;
mgr_dev = class_find_device(fpga_mgr_class, NULL, dev, fpga_mgr_dev_match); mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
fpga_mgr_dev_match);
if (!mgr_dev) if (!mgr_dev)
return ERR_PTR(-ENODEV); return ERR_PTR(-ENODEV);
......
software/kernel/svec-core-fpga.c
View file @ 1f3df4cd
...@@ -83,7 +83,7 @@ static int svec_fpga_dbg_bld_info(struct seq_file *s, void *offset) ...@@ -83,7 +83,7 @@ static int svec_fpga_dbg_bld_info(struct seq_file *s, void *offset)
} }
for (off = SVEC_BASE_REGS_BUILDINFO; for (off = SVEC_BASE_REGS_BUILDINFO;
off < SVEC_BASE_REGS_BUILDINFO + SVEC_BASE_REGS_BUILDINFO_SIZE -1; off < SVEC_BASE_REGS_BUILDINFO + SVEC_BASE_REGS_BUILDINFO_SIZE - 1;
off += 4) { off += 4) {
uint32_t tmp = ioread32be(svec_fpga->fpga + off); uint32_t tmp = ioread32be(svec_fpga->fpga + off);
int k; int k;
...@@ -145,7 +145,8 @@ static int svec_fpga_dbg_init(struct svec_fpga *svec_fpga) ...@@ -145,7 +145,8 @@ static int svec_fpga_dbg_init(struct svec_fpga *svec_fpga)
goto err; goto err;
} }
svec_fpga->dbg_bld_info = debugfs_create_file(SVEC_DBG_BLD_INFO_NAME, 0444, svec_fpga->dbg_bld_info = debugfs_create_file(SVEC_DBG_BLD_INFO_NAME,
0444,
svec_fpga->dbg_dir, svec_fpga->dbg_dir,
svec_fpga, svec_fpga,
&svec_fpga_dbg_bld_info_ops); &svec_fpga_dbg_bld_info_ops);
...@@ -241,7 +242,8 @@ static struct resource svec_fpga_fmc_i2c_res[] = { ...@@ -241,7 +242,8 @@ static struct resource svec_fpga_fmc_i2c_res[] = {
.name = "i2c-ocores-mem", .name = "i2c-ocores-mem",
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
.start = SVEC_BASE_REGS_FMC_I2C, .start = SVEC_BASE_REGS_FMC_I2C,
.end = SVEC_BASE_REGS_FMC_I2C + SVEC_BASE_REGS_FMC_I2C_SIZE -1, .end = SVEC_BASE_REGS_FMC_I2C
+ SVEC_BASE_REGS_FMC_I2C_SIZE - 1,
}, { }, {
.name = "i2c-ocores-irq", .name = "i2c-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
...@@ -264,7 +266,8 @@ static struct resource svec_fpga_spi_res[] = { ...@@ -264,7 +266,8 @@ static struct resource svec_fpga_spi_res[] = {
.name = "spi-ocores-mem", .name = "spi-ocores-mem",
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
.start = SVEC_BASE_REGS_FLASH_SPI, .start = SVEC_BASE_REGS_FLASH_SPI,
.end = SVEC_BASE_REGS_FLASH_SPI + SVEC_BASE_REGS_FLASH_SPI_SIZE - 1, .end = SVEC_BASE_REGS_FLASH_SPI
+ SVEC_BASE_REGS_FLASH_SPI_SIZE - 1,
}, { }, {
.name = "spi-ocores-irq", .name = "spi-ocores-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
...@@ -376,7 +379,8 @@ static ssize_t temperature_show(struct device *dev, ...@@ -376,7 +379,8 @@ static ssize_t temperature_show(struct device *dev,
struct svec_dev *svec_dev = dev_get_drvdata(svec_fpga->dev.parent); struct svec_dev *svec_dev = dev_get_drvdata(svec_fpga->dev.parent);
if (svec_dev->meta.cap & SVEC_META_CAP_THERM) { if (svec_dev->meta.cap & SVEC_META_CAP_THERM) {
uint32_t temp = ioread32be(svec_fpga->fpga + SVEC_FPGA_THERM_TEMP); uint32_t temp = ioread32be(svec_fpga->fpga
+ SVEC_FPGA_THERM_TEMP);
return snprintf(buf, PAGE_SIZE, "%d.%d C\n", return snprintf(buf, PAGE_SIZE, "%d.%d C\n",
temp / 16, (temp & 0xF) * 1000 / 16); temp / 16, (temp & 0xF) * 1000 / 16);
...@@ -395,8 +399,10 @@ static ssize_t serial_number_show(struct device *dev, ...@@ -395,8 +399,10 @@ static ssize_t serial_number_show(struct device *dev,
struct svec_dev *svec_dev = dev_get_drvdata(svec_fpga->dev.parent); struct svec_dev *svec_dev = dev_get_drvdata(svec_fpga->dev.parent);
if (svec_dev->meta.cap & SVEC_META_CAP_THERM) { if (svec_dev->meta.cap & SVEC_META_CAP_THERM) {
uint32_t msb = ioread32be(svec_fpga->fpga + SVEC_FPGA_THERM_SERID_MSB); uint32_t msb = ioread32be(svec_fpga->fpga
uint32_t lsb = ioread32be(svec_fpga->fpga + SVEC_FPGA_THERM_SERID_LSB); + SVEC_FPGA_THERM_SERID_MSB);
uint32_t lsb = ioread32be(svec_fpga->fpga
+ SVEC_FPGA_THERM_SERID_LSB);
return snprintf(buf, PAGE_SIZE, "0x%08x%08x\n", msb, lsb); return snprintf(buf, PAGE_SIZE, "0x%08x%08x\n", msb, lsb);
} else { } else {
...@@ -491,7 +497,7 @@ static ssize_t reset_app_store(struct device *dev, ...@@ -491,7 +497,7 @@ static ssize_t reset_app_store(struct device *dev,
return count; return count;
} }
static DEVICE_ATTR(reset_app, 0644, reset_app_show, reset_app_store); static DEVICE_ATTR_RW(reset_app);
static struct attribute *svec_fpga_csr_attrs[] = { static struct attribute *svec_fpga_csr_attrs[] = {
&dev_attr_pcb_rev.attr, &dev_attr_pcb_rev.attr,
...@@ -620,16 +626,17 @@ static int svec_fpga_app_id_build(struct svec_fpga *svec_fpga, ...@@ -620,16 +626,17 @@ static int svec_fpga_app_id_build(struct svec_fpga *svec_fpga,
unsigned long app_off, unsigned long app_off,
char *id, unsigned int size) char *id, unsigned int size)
{ {
uint32_t vendor = ioread32(svec_fpga->fpga + app_off + FPGA_META_VENDOR); uint32_t vendor = ioread32(svec_fpga->fpga + app_off
uint32_t device = ioread32(svec_fpga->fpga + app_off + FPGA_META_DEVICE); + FPGA_META_VENDOR);
uint32_t device = ioread32(svec_fpga->fpga + app_off
+ FPGA_META_DEVICE);
memset(id, 0, size); memset(id, 0, size);
if (vendor == 0xFF000000) { if (vendor == 0xFF000000) {
dev_warn(&svec_fpga->dev, "Vendor UUID not supported yet\n"); dev_warn(&svec_fpga->dev, "Vendor UUID not supported yet\n");
return -ENODEV; return -ENODEV;
} else {
snprintf(id, size, "id:%4phN%4phN", &vendor, &device);
} }
snprintf(id, size, "id:%4phN%4phN", &vendor, &device);
return 0; return 0;
} }
......
software/kernel/svec-core.c
View file @ 1f3df4cd
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* SPDX-License-Identifier: GPLv2
* *
* Copyright (C) 2017 CERN (www.cern.ch) * Copyright (C) 2017 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch> * Author: Federico Vaga <federico.vaga@cern.ch>
...@@ -267,11 +267,9 @@ static int svec_fpga_write_word(struct fpga_manager *mgr, ...@@ -267,11 +267,9 @@ static int svec_fpga_write_word(struct fpga_manager *mgr,
uint32_t xldr_fifo_r0; /* Bitstream data input control register */ uint32_t xldr_fifo_r0; /* Bitstream data input control register */
uint32_t xldr_fifo_r1; /* Bitstream data input register */ uint32_t xldr_fifo_r1; /* Bitstream data input register */
int rv, try = 10000; int rv, try = 10000;
static int cnt = 0;
if (size <= 0 || size >= 5) { if (size <= 0 || size >= 5)
return -EINVAL; return -EINVAL;
}
xldr_fifo_r0 = ((size - 1) & 0x3) | (is_last ? XLDR_FIFO_R0_XLAST : 0); xldr_fifo_r0 = ((size - 1) & 0x3) | (is_last ? XLDR_FIFO_R0_XLAST : 0);
xldr_fifo_r1 = htonl(word); xldr_fifo_r1 = htonl(word);
...@@ -279,14 +277,12 @@ static int svec_fpga_write_word(struct fpga_manager *mgr, ...@@ -279,14 +277,12 @@ static int svec_fpga_write_word(struct fpga_manager *mgr,
rv = ioread32be(loader_addr + XLDR_REG_FIFO_CSR); rv = ioread32be(loader_addr + XLDR_REG_FIFO_CSR);
} while (rv & XLDR_FIFO_CSR_FULL && --try >= 0); } while (rv & XLDR_FIFO_CSR_FULL && --try >= 0);
if(rv & XLDR_FIFO_CSR_FULL) if (rv & XLDR_FIFO_CSR_FULL)
return -EBUSY; /* bootloader busy */ return -EBUSY; /* bootloader busy */
iowrite32be(xldr_fifo_r0, loader_addr + XLDR_REG_FIFO_R0); iowrite32be(xldr_fifo_r0, loader_addr + XLDR_REG_FIFO_R0);
iowrite32be(xldr_fifo_r1, loader_addr + XLDR_REG_FIFO_R1); iowrite32be(xldr_fifo_r1, loader_addr + XLDR_REG_FIFO_R1);
cnt++;
return 0; return 0;
} }
...@@ -367,7 +363,8 @@ static int svec_fpga_write_stop(struct fpga_manager *mgr, ...@@ -367,7 +363,8 @@ static int svec_fpga_write_stop(struct fpga_manager *mgr,
rval = ioread32be(loader_addr + XLDR_REG_CSR); rval = ioread32be(loader_addr + XLDR_REG_CSR);
if (rval & XLDR_CSR_DONE) if (rval & XLDR_CSR_DONE)
break; break;
msleep(1); usleep_range(900, 1100);
} }
if (!(rval & XLDR_CSR_DONE)) { if (!(rval & XLDR_CSR_DONE)) {
...@@ -384,7 +381,7 @@ out: ...@@ -384,7 +381,7 @@ out:
iowrite32be(XLDR_CSR_EXIT, loader_addr + XLDR_REG_CSR); iowrite32be(XLDR_CSR_EXIT, loader_addr + XLDR_REG_CSR);
/* give the VME core a little while to settle up */ /* give the VME core a little while to settle up */
msleep(10); usleep_range(10000, 20000);
return err; return err;
} }
...@@ -450,7 +447,8 @@ static int svec_fpga_write_init(struct fpga_manager *mgr, ...@@ -450,7 +447,8 @@ static int svec_fpga_write_init(struct fpga_manager *mgr,
} }
static int svec_fpga_write(struct fpga_manager *mgr, const char *buf, size_t count) static int svec_fpga_write(struct fpga_manager *mgr, const char *buf,
size_t count)
{ {
return svec_fpga_write_buf(mgr, buf, count); return svec_fpga_write_buf(mgr, buf, count);
} }
......
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