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Simple VME FMC Carrier SVEC
Commit 2ffb0319 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] fix DDR constraints

parent 9e4d8b96
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Showing with 64 additions and 61 deletions
CHANGELOG.rst
View file @ 2ffb0319
......@@ -2,6 +2,12 @@
Change Log
==========
[unreleased]
============
Fixed
-----
- [hdl] DDR constraints
[1.4.5] 2019-12-16
==================
Fixed
......
hdl/syn/common/Manifest.py
View file @ 2ffb0319
......@@ -14,5 +14,6 @@ for p in svec_base_ucf:
f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'svec_base_ucf'".format(p)
if p == 'ddr4' or p == 'ddr5':
if 'svec_base_ddr_common.ucf' not in files:
files.append('svec_base_ddr_common.ucf')
files.append(f)
hdl/syn/common/svec_base_common.ucf
View file @ 2ffb0319
......@@ -218,10 +218,6 @@ TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "inst_svec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
......
hdl/syn/common/svec_base_ddr5.ucf
View file @ 2ffb0319
......@@ -49,27 +49,27 @@ NET "ddr5_a_o[1]" LOC = D30;
NET "ddr5_a_o[0]" LOC = D28;
# DDR IO standards and terminations
NET "ddr5_udqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_udqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_p_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_n_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_rzq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_we_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_udm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_reset_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ras_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_odt_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ldm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_cke_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_cas_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr5_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_p_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_n_b[*]" IN_TERM = NONE;
NET "ddr5_udqs_p_b[*]" IN_TERM = NONE;
NET "ddr5_udqs_n_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_p_b" IN_TERM = NONE;
NET "ddr5_ldqs_n_b" IN_TERM = NONE;
NET "ddr5_udqs_p_b" IN_TERM = NONE;
NET "ddr5_udqs_n_b" IN_TERM = NONE;
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