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Simple VME FMC Carrier SVEC
Commit 4b432b68 authored by Tristan Gingold's avatar Tristan Gingold
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Update golden after renaming.

parent 46bd7e78
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Showing with 4 additions and 6 deletions
hdl/syn/golden/Manifest.py
View file @ 4b432b68
...@@ -16,13 +16,13 @@ syn_top = "svec_golden" ...@@ -16,13 +16,13 @@ syn_top = "svec_golden"
board = "svec" board = "svec"
ctrls = ["bank4_64b_32b"] ctrls = ["bank4_64b_32b"]
svec_template_ucf = ['ddr4'] svec_base_ucf = []
files = [ "buildinfo_pkg.vhd" ] files = [ "buildinfo_pkg.vhd" ]
modules = { modules = {
"local" : [ "local" : [
"../../top/golden", "../../top/golden", "../common",
], ],
"git" : [ "git" : [
"https://ohwr.org/project/wr-cores.git", "https://ohwr.org/project/wr-cores.git",
......
hdl/top/golden/svec_golden.vhd
View file @ 4b432b68
...@@ -148,13 +148,13 @@ architecture top of svec_golden is ...@@ -148,13 +148,13 @@ architecture top of svec_golden is
signal app_wb_out : t_wishbone_master_out; signal app_wb_out : t_wishbone_master_out;
signal app_wb_in : t_wishbone_master_in; signal app_wb_in : t_wishbone_master_in;
begin begin
inst_svec_template: entity work.svec_template_wr inst_svec_base: entity work.svec_base_wr
generic map ( generic map (
g_with_vic => True, g_with_vic => True,
g_with_onewire => True, g_with_onewire => True,
g_with_spi => True, g_with_spi => True,
g_with_wr => False, g_with_wr => False,
g_with_ddr4 => True, g_with_ddr4 => False,
g_with_ddr5 => False, g_with_ddr5 => False,
g_app_offset => x"0000_0000", g_app_offset => x"0000_0000",
g_num_user_irq => 0, g_num_user_irq => 0,
...@@ -213,8 +213,6 @@ begin ...@@ -213,8 +213,6 @@ begin
uart_txd_o => open, uart_txd_o => open,
plldac_sclk_o => open, plldac_sclk_o => open,
plldac_din_o => open, plldac_din_o => open,
pll25dac_cs_n_o => open,
pll20dac_cs_n_o => open,
pll20dac_din_o => open, pll20dac_din_o => open,
pll20dac_sclk_o => open, pll20dac_sclk_o => open,
pll20dac_sync_n_o => open, pll20dac_sync_n_o => open,
......
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