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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
7e0a206b
Commit
7e0a206b
authored
Apr 09, 2020
by
Tristan Gingold
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Rename template to base (in filenames).
parent
3da89c5c
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14 changed files
with
14 additions
and
14 deletions
+14
-14
Manifest.py
hdl/rtl/Manifest.py
+2
-2
svec_base_regs.cheby
hdl/rtl/svec_base_regs.cheby
+0
-0
svec_base_regs.vhd
hdl/rtl/svec_base_regs.vhd
+0
-0
svec_base_wr.vhd
hdl/rtl/svec_base_wr.vhd
+0
-0
Manifest.py
hdl/syn/common/Manifest.py
+10
-10
svec_base_common.ucf
hdl/syn/common/svec_base_common.ucf
+0
-0
svec_base_ddr4.ucf
hdl/syn/common/svec_base_ddr4.ucf
+0
-0
svec_base_ddr5.ucf
hdl/syn/common/svec_base_ddr5.ucf
+0
-0
svec_base_ddr_common.ucf
hdl/syn/common/svec_base_ddr_common.ucf
+0
-0
svec_base_gpio.ucf
hdl/syn/common/svec_base_gpio.ucf
+0
-0
svec_base_led.ucf
hdl/syn/common/svec_base_led.ucf
+0
-0
svec_base_wr.ucf
hdl/syn/common/svec_base_wr.ucf
+0
-0
Manifest.py
hdl/syn/golden/Manifest.py
+1
-1
Manifest.py
hdl/syn/golden_wr/Manifest.py
+1
-1
No files found.
hdl/rtl/Manifest.py
View file @
7e0a206b
files
=
[
"svec_
templat
e_regs.vhd"
,
"svec_
templat
e_wr.vhd"
,
"svec_
bas
e_regs.vhd"
,
"svec_
bas
e_wr.vhd"
,
]
hdl/rtl/svec_
templat
e_regs.cheby
→
hdl/rtl/svec_
bas
e_regs.cheby
View file @
7e0a206b
File moved
hdl/rtl/svec_
templat
e_regs.vhd
→
hdl/rtl/svec_
bas
e_regs.vhd
View file @
7e0a206b
File moved
hdl/rtl/svec_
templat
e_wr.vhd
→
hdl/rtl/svec_
bas
e_wr.vhd
View file @
7e0a206b
File moved
hdl/syn/common/Manifest.py
View file @
7e0a206b
# User should define the variable svec_
templat
e_ucf
# User should define the variable svec_
bas
e_ucf
files
=
[
"svec_
templat
e_common.ucf"
]
files
=
[
"svec_
bas
e_common.ucf"
]
ucf_dict
=
{
'ddr4'
:
"svec_
templat
e_ddr4.ucf"
,
'ddr5'
:
"svec_
templat
e_ddr5.ucf"
,
'wr'
:
"svec_
templat
e_wr.ucf"
,
'led'
:
"svec_
templat
e_led.ucf"
,
'gpio'
:
"svec_
templat
e_gpio.ucf"
,
'ddr4'
:
"svec_
bas
e_ddr4.ucf"
,
'ddr5'
:
"svec_
bas
e_ddr5.ucf"
,
'wr'
:
"svec_
bas
e_wr.ucf"
,
'led'
:
"svec_
bas
e_led.ucf"
,
'gpio'
:
"svec_
bas
e_gpio.ucf"
,
}
for
p
in
svec_
templat
e_ucf
:
for
p
in
svec_
bas
e_ucf
:
f
=
ucf_dict
.
get
(
p
,
None
)
assert
f
is
not
None
,
"unknown name {} in 'svec_
templat
e_ucf'"
.
format
(
p
)
assert
f
is
not
None
,
"unknown name {} in 'svec_
bas
e_ucf'"
.
format
(
p
)
if
p
==
'ddr4'
or
p
==
'ddr5'
:
files
.
append
(
'svec_
templat
e_ddr_common.ucf'
)
files
.
append
(
'svec_
bas
e_ddr_common.ucf'
)
files
.
append
(
f
)
hdl/syn/common/svec_
templat
e_common.ucf
→
hdl/syn/common/svec_
bas
e_common.ucf
View file @
7e0a206b
File moved
hdl/syn/common/svec_
templat
e_ddr4.ucf
→
hdl/syn/common/svec_
bas
e_ddr4.ucf
View file @
7e0a206b
File moved
hdl/syn/common/svec_
templat
e_ddr5.ucf
→
hdl/syn/common/svec_
bas
e_ddr5.ucf
View file @
7e0a206b
File moved
hdl/syn/common/svec_
templat
e_ddr_common.ucf
→
hdl/syn/common/svec_
bas
e_ddr_common.ucf
View file @
7e0a206b
File moved
hdl/syn/common/svec_
templat
e_gpio.ucf
→
hdl/syn/common/svec_
bas
e_gpio.ucf
View file @
7e0a206b
File moved
hdl/syn/common/svec_
templat
e_led.ucf
→
hdl/syn/common/svec_
bas
e_led.ucf
View file @
7e0a206b
File moved
hdl/syn/common/svec_
templat
e_wr.ucf
→
hdl/syn/common/svec_
bas
e_wr.ucf
View file @
7e0a206b
File moved
hdl/syn/golden/Manifest.py
View file @
7e0a206b
...
...
@@ -16,7 +16,7 @@ syn_top = "svec_golden"
board
=
"svec"
ctrls
=
[
"bank4_64b_32b"
]
svec_
templat
e_ucf
=
[
'ddr4'
]
svec_
bas
e_ucf
=
[
'ddr4'
]
files
=
[
"buildinfo_pkg.vhd"
]
...
...
hdl/syn/golden_wr/Manifest.py
View file @
7e0a206b
...
...
@@ -16,7 +16,7 @@ syn_top = "svec_golden_wr"
board
=
"svec"
ctrls
=
[
"bank4_64b_32b"
]
svec_
templat
e_ucf
=
[
'ddr4'
,
'wr'
,
'gpio'
,
'led'
]
svec_
bas
e_ucf
=
[
'ddr4'
,
'wr'
,
'gpio'
,
'led'
]
files
=
[
"buildinfo_pkg.vhd"
]
...
...
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