unittest: add a programming test

It takes a bitstream from the environment and it writes it. export BITSTREAM=/path/to/bitstream.bin export VME_SLOT=8 python -m unittest -v SvecTestProgramming.py Signed-off-by: Federico Vaga <federico.vaga@vaga.pv.it>

unittest: add a programming test
It takes a bitstream from the environment and it writes it. export BITSTREAM=/path/to/bitstream.bin export VME_SLOT=8 python -m unittest -v SvecTestProgramming.py Signed-off-by: Federico Vaga <federico.vaga@vaga.pv.it>
887a35e8 · Federico Vaga · 6cac76e5 · 887a35e8
Commit 887a35e8 authored Oct 13, 2017 by Federico Vaga
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SvecTestProgramming.py unittest/SvecTestProgramming.py +23 -0

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--- a/unittest/SvecTestProgramming.py
+++ b/unittest/SvecTestProgramming.py
+import os
+import unittest
+
+
+class SvecTestProgramming(unittest.TestCase):
+    def setUp(self):
+        slot = os.environ["VME_SLOT"]
+        self.file_path = "/sys/bus/vme/devices/vme.{}/svec/svec.{}/AFPGA/lock".format(slot, slot)
+        self.dev_path = "/dev/svec.{}".format(slot)
+        self.bitstream = os.environ["BITSTREAM"]
+
+    def test_01(self):
+        """It writes a dummy FPGA bitstream"""
+        with open(self.file_path, "w") as f:
+            f.write("unlock")
+
+        with open(self.bitstream, "rb") as d:
+            with open(self.dev_path, "wb") as f:
+                f.write(d.read())
+
+        with open(self.file_path, "r") as f:
+            val = f.read().strip()
+        self.assertEqual(val, "locked")