Add tester_wr design (board to test irq).

9a82c043 · Tristan Gingold · 1097ade4 · 9a82c043 · 9a82c043 · 9a82c043
Commit 9a82c043 authored Apr 07, 2020 by Tristan Gingold
7 changed files
--- a/hdl/syn/tester_wr/Manifest.py
+++ b/hdl/syn/tester_wr/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+  fetchto = "../../ip_cores"
+
+syn_device = "xc6slx150t"
+syn_grade = "-3"
+syn_package = "fgg900"
+syn_project = "svec_tester_wr.xise"
+syn_tool = "ise"
+syn_top = "svec_tester_wr"
+
+board = "svec"
+ctrls = ["bank4_64b_32b"]
+
+svec_base_ucf = ['wr', 'gpio', 'led']
+
+files = [ "buildinfo_pkg.vhd" ]
+
+modules = {
+  "local" : [
+      "../../top/tester_wr",
+      "../../syn/common",
+  ],
+  "git" : [
+      "https://ohwr.org/project/wr-cores.git",
+      "https://ohwr.org/project/general-cores.git",
+      "https://ohwr.org/project/vme64x-core.git",
+      "https://ohwr.org/project/ddr3-sp6-core.git",
+  ],
+}
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
--- a/hdl/syn/tester_wr/syn_extra_steps.tcl
+++ b/hdl/syn/tester_wr/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close
--- a/hdl/top/tester_wr/Manifest.py
+++ b/hdl/top/tester_wr/Manifest.py
+files = ["svec_tester_wr.vhd", "tester_wr_regs.vhd" ]
+modules = {'local': ["../../rtl"]}
--- a/hdl/top/tester_wr/svec_tester_wr.vhd
+++ b/hdl/top/tester_wr/svec_tester_wr.vhd
--- a/hdl/top/tester_wr/tester_wr_regs.cheby
+++ b/hdl/top/tester_wr/tester_wr_regs.cheby
+memory-map:
+  bus: wb-32-be
+  name: tester_wr_regs
+  description: Memory map of the SVEC tester board
+  x-hdl:
+    busgroup: True
+  children:
+    - reg:
+        name: status
+        description: General status
+        address: 0x2008
+        width: 32
+        access: ro
+        children:
+          - field:
+              name: time_valid
+              description: Set when WR has time
+              range: 0
+          - field:
+              name: link_valid
+              description: Set when WR has link
+              range: 1
+    - reg:
+       name: tm_tai
+       description: TAI from wr
+       width: 64
+       access: ro
+    - reg:
+       name: tm_cycles
+       description: number of cycles (16Mhz) within the second
+       width: 32
+       access: ro
+    - reg:
+       name: start_tai
+       description: absolute TAI (LSB) for interrupts
+       width: 32
+       access: rw
+    - reg:
+       name: start_cycles
+       description: absolute cycles for interrupts
+       width: 32
+       access: rw
+    - reg:
+       name: period_cycles
+       description: number of cycles between interrupts
+       width: 32
+       access: rw
+    - reg:
+       name: total_count
+       description: number of interrupts to deliver
+       width: 32
+       access: rw
+    - reg:
+       name: current_count
+       description: number of interrupts delivered.
+       width: 32
+       access: ro
+    - reg:
+       name: ack_int
+       description: the current number of interrupts must be written to ack the interrupt.
+       width: 32
+       access: wo
+       x-hdl:
+         write-strobe: True
+    - reg:
+       name: ack_count
+       description: number of interrupts successfully ack-ed; cleared at the start
+       width: 32
+       access: ro
--- a/hdl/top/tester_wr/tester_wr_regs.h
+++ b/hdl/top/tester_wr/tester_wr_regs.h
+#ifndef __CHEBY__TESTER_WR_REGS__H__
+#define __CHEBY__TESTER_WR_REGS__H__
+#define TESTER_WR_REGS_SIZE 8248
+
+/* General status */
+#define TESTER_WR_REGS_STATUS 0x2008UL
+#define TESTER_WR_REGS_STATUS_TIME_VALID 0x1UL
+#define TESTER_WR_REGS_STATUS_LINK_VALID 0x2UL
+
+/* TAI from wr */
+#define TESTER_WR_REGS_TM_TAI 0x2010UL
+
+/* number of cycles (16Mhz) within the second */
+#define TESTER_WR_REGS_TM_CYCLES 0x2018UL
+
+/* absolute TAI (LSB) for interrupts */
+#define TESTER_WR_REGS_START_TAI 0x201cUL
+
+/* absolute cycles for interrupts */
+#define TESTER_WR_REGS_START_CYCLES 0x2020UL
+
+/* number of cycles between interrupts */
+#define TESTER_WR_REGS_PERIOD_CYCLES 0x2024UL
+
+/* number of interrupts to deliver */
+#define TESTER_WR_REGS_TOTAL_COUNT 0x2028UL
+
+/* number of interrupts delivered. */
+#define TESTER_WR_REGS_CURRENT_COUNT 0x202cUL
+
+/* the current number of interrupts must be written to ack the interrupt. */
+#define TESTER_WR_REGS_ACK_INT 0x2030UL
+
+/* number of interrupts successfully ack-ed; cleared at the start */
+#define TESTER_WR_REGS_ACK_COUNT 0x2034UL
+
+struct tester_wr_regs {
+
+  /* padding to: 2050 words */
+  uint32_t __padding_0[2050];
+  /* [0x2008]: REG (ro) General status */
+  uint32_t status;
+
+  /* padding to: 2052 words */
+  uint32_t __padding_1[1];
+
+  /* [0x2010]: REG (ro) TAI from wr */
+  uint64_t tm_tai;
+
+  /* [0x2018]: REG (ro) number of cycles (16Mhz) within the second */
+  uint32_t tm_cycles;
+
+  /* [0x201c]: REG (rw) absolute TAI (LSB) for interrupts */
+  uint32_t start_tai;
+
+  /* [0x2020]: REG (rw) absolute cycles for interrupts */
+  uint32_t start_cycles;
+
+  /* [0x2024]: REG (rw) number of cycles between interrupts */
+  uint32_t period_cycles;
+
+  /* [0x2028]: REG (rw) number of interrupts to deliver */
+  uint32_t total_count;
+
+  /* [0x202c]: REG (ro) number of interrupts delivered. */
+  uint32_t current_count;
+
+  /* [0x2030]: REG (wo) the current number of interrupts must be written to ack the interrupt. */
+  uint32_t ack_int;
+
+  /* [0x2034]: REG (ro) number of interrupts successfully ack-ed; cleared at the start */
+  uint32_t ack_count;
+};
+
+#endif /* __CHEBY__TESTER_WR_REGS__H__ */
--- a/hdl/top/tester_wr/tester_wr_regs.vhd
+++ b/hdl/top/tester_wr/tester_wr_regs.vhd