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Simple VME FMC Carrier SVEC
Commit 9bde4b57 authored by Tristan Gingold's avatar Tristan Gingold
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vmecore_test: add interrupt status.

parent 6521663b
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Showing with 29 additions and 8 deletions
hdl/top/vmecore_test/vmecore_test.vhd
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...@@ -57,9 +57,11 @@ architecture rtl of vmecore_test is ...@@ -57,9 +57,11 @@ architecture rtl of vmecore_test is
-- 0x1004: nbr of write errors in pattern ram -- 0x1004: nbr of write errors in pattern ram
-- 0x1005: generates bus error. -- 0x1005: generates bus error.
-- 0x2000: counter (4B). Generate an interrupt when 0 is reached. -- 0x2000: counter (4B). Generate an interrupt when 0 is reached.
-- 0x2001: irq status (read to clear)
-- 0x3000: pattern ram (0x1000 * 4B) -- 0x3000: pattern ram (0x1000 * 4B)
-- 0x4000 - 0x3ff000: pattern ram -- 0x4000 - 0x3ff000: pattern ram
signal counter : unsigned(31 downto 0); signal counter : unsigned(31 downto 0);
signal irq_status : std_logic;
signal leds : std_logic_vector(15 downto 0); signal leds : std_logic_vector(15 downto 0);
signal last_trans : std_logic_vector (28 downto 0); signal last_trans : std_logic_vector (28 downto 0);
...@@ -111,10 +113,17 @@ begin ...@@ -111,10 +113,17 @@ begin
nbr_read <= (others => '0'); nbr_read <= (others => '0');
nbr_write <= (others => '0'); nbr_write <= (others => '0');
nbr_write_errors <= (others => '0'); nbr_write_errors <= (others => '0');
irq_status <= '1';
int_o <= '0';
else else
int_o <= '0';
-- Decrementer -- Decrementer
if counter /= (counter'range => '0') then if counter /= (counter'range => '0') then
counter <= counter - 1; counter <= counter - 1;
if counter = 1 then
int_o <= '1';
irq_status <= '1';
end if;
end if; end if;
if slave_i.stb = '1' and slave_i.cyc = '1' then if slave_i.stb = '1' and slave_i.cyc = '1' then
...@@ -161,12 +170,17 @@ begin ...@@ -161,12 +170,17 @@ begin
null; null;
end case; end case;
when "10" => when "10" =>
for i in 3 downto 0 loop case slave_i.adr(2 downto 0) is
if slave_i.sel (i) = '1' then when "000" =>
counter(8*i + 7 downto 8*i) <= for i in 3 downto 0 loop
unsigned(slave_i.dat(8*i + 7 downto 8*i)); if slave_i.sel (i) = '1' then
end if; counter(8*i + 7 downto 8*i) <=
end loop; unsigned(slave_i.dat(8*i + 7 downto 8*i));
end if;
end loop;
when others =>
null;
end case;
when "11" => when "11" =>
pattern_write; pattern_write;
when others => when others =>
...@@ -205,7 +219,15 @@ begin ...@@ -205,7 +219,15 @@ begin
null; null;
end case; end case;
when "10" => when "10" =>
slave_o.dat <= std_logic_vector(counter); case slave_i.adr(2 downto 0) is
when "000" =>
slave_o.dat <= std_logic_vector(counter);
when "001" =>
slave_o.dat <= (0 => irq_status, others => '0');
irq_status <= '0';
when others =>
slave_o.dat <= (others => '0');
end case;
when "11" => when "11" =>
slave_o.dat <= pattern; slave_o.dat <= pattern;
when others => when others =>
...@@ -222,7 +244,6 @@ begin ...@@ -222,7 +244,6 @@ begin
end process; end process;
leds_o <= leds; leds_o <= leds;
int_o <= '1' when counter = 1 else '0';
-- drive unused WB slave_o outputs -- drive unused WB slave_o outputs
slave_o.stall <= '0'; slave_o.stall <= '0';
......
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